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add hal lib for stm32f103rb
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pikastech
parent
faa03e4362
commit
8d7e118ea2
@ -1,5 +1,5 @@
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pikascript-core==v1.2.8
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pikascript-core==v1.2.8
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PikaStdLib==v1.2.4
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PikaStdLib==v1.2.4
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PikaStdDevice==v1.4.3
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PikaStdDevice==v1.4.3
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STM32F1==latest
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STM32F1==v1.0.0
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STM32F103RBBooter==latest
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STM32F103RBBooter==v1.0.0
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/**
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******************************************************************************
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* @file stm32_assert.h
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief STM32 assert template file.
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* This file should be copied to the application folder and renamed
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* to stm32_assert.h.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32_ASSERT_H
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#define __STM32_ASSERT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Includes ------------------------------------------------------------------*/
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/* Exported macro ------------------------------------------------------------*/
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#ifdef USE_FULL_ASSERT
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/**
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* @brief The assert_param macro is used for function's parameters check.
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* @param expr: If expr is false, it calls assert_failed function
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* which reports the name of the source file and the source
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* line number of the call that failed.
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* If expr is true, it returns no value.
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* @retval None
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*/
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#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
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/* Exported functions ------------------------------------------------------- */
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void assert_failed(uint8_t* file, uint32_t line);
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32_ASSERT_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -0,0 +1,967 @@
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/**
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******************************************************************************
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* @file stm32f1xx_hal_adc.h
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief Header file containing functions prototypes of ADC HAL library.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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|
* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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|
* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F1xx_HAL_ADC_H
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#define __STM32F1xx_HAL_ADC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal_def.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @addtogroup ADC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup ADC_Exported_Types ADC Exported Types
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* @{
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*/
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/**
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* @brief Structure definition of ADC and regular group initialization
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* @note Parameters of this structure are shared within 2 scopes:
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* - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
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* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
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* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
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* ADC can be either disabled or enabled without conversion on going on regular group.
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*/
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typedef struct
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{
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uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
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or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
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This parameter can be a value of @ref ADC_Data_align */
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uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
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This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
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If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
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Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
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If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
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Scan direction is upward: from rank1 to rank 'n'.
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This parameter can be a value of @ref ADC_Scan_mode
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Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
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or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
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the last conversion of the sequence. All previous conversions would be overwritten by the last one.
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Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
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uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
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after the selected trigger occurred (software start or external trigger).
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
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To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
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This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
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uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
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Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
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Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
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If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
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This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
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uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
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If set to ADC_SOFTWARE_START, external triggers are disabled.
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If set to external trigger source, triggering is on event rising edge.
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This parameter can be a value of @ref ADC_External_trigger_source_Regular */
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}ADC_InitTypeDef;
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/**
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* @brief Structure definition of ADC channel for regular group
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* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
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* ADC can be either disabled or enabled without conversion on going on regular group.
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*/
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typedef struct
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{
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uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
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This parameter can be a value of @ref ADC_channels
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Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
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Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
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Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
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It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
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Refer to errata sheet of these devices for more details. */
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uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
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This parameter can be a value of @ref ADC_regular_rank
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Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
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uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
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Unit: ADC clock cycles
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Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
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This parameter can be a value of @ref ADC_sampling_times
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Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
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If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
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Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
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sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
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Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
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}ADC_ChannelConfTypeDef;
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/**
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* @brief ADC Configuration analog watchdog definition
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* @note The setting of these parameters with function is conditioned to ADC state.
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* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
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*/
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typedef struct
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{
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uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
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This parameter can be a value of @ref ADC_analog_watchdog_mode. */
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uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
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This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
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This parameter can be a value of @ref ADC_channels. */
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uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
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uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
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uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
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}ADC_AnalogWDGConfTypeDef;
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/**
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* @brief HAL ADC state machine: ADC states definition (bitfields)
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*/
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/* States of ADC global scope */
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#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
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#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
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#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
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#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
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/* States of ADC errors */
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#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
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#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
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#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
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/* States of ADC group regular */
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#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
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external trigger, low power auto power-on, multimode ADC master control) */
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#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
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#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
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#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */
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/* States of ADC group injected */
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#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
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external trigger, low power auto power-on, multimode ADC master control) */
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#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
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#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
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/* States of ADC analog watchdogs */
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#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
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#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
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#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
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/* States of ADC multi-mode */
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#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
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/**
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* @brief ADC handle Structure definition
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*/
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typedef struct
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{
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ADC_TypeDef *Instance; /*!< Register base address */
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ADC_InitTypeDef Init; /*!< ADC required parameters */
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DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
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HAL_LockTypeDef Lock; /*!< ADC locking object */
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__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
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__IO uint32_t ErrorCode; /*!< ADC Error code */
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}ADC_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup ADC_Exported_Constants ADC Exported Constants
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* @{
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*/
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/** @defgroup ADC_Error_Code ADC Error Code
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* @{
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*/
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#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
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#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
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enable/disable, erroneous state */
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#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
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#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
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/**
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* @}
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*/
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/** @defgroup ADC_Data_align ADC data alignment
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* @{
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*/
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#define ADC_DATAALIGN_RIGHT 0x00000000U
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#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
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/**
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* @}
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*/
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/** @defgroup ADC_Scan_mode ADC scan mode
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* @{
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|
*/
|
||||||
|
/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
|
||||||
|
/* compatibility with other STM32 devices having a sequencer with */
|
||||||
|
/* additional options. */
|
||||||
|
#define ADC_SCAN_DISABLE 0x00000000U
|
||||||
|
#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
|
||||||
|
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_channels ADC channels
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Note: Depending on devices, some channels may not be available on package */
|
||||||
|
/* pins. Refer to device datasheet for channels availability. */
|
||||||
|
#define ADC_CHANNEL_0 0x00000000U
|
||||||
|
#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
|
||||||
|
#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
|
||||||
|
#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
|
||||||
|
#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
|
||||||
|
#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
|
||||||
|
#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
|
||||||
|
#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
|
||||||
|
#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
|
||||||
|
#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
|
||||||
|
#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 ))
|
||||||
|
#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
|
||||||
|
#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 ))
|
||||||
|
#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
|
||||||
|
#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
|
||||||
|
#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
|
||||||
|
#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
|
||||||
|
#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
|
||||||
|
|
||||||
|
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
|
||||||
|
#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_sampling_times ADC sampling times
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
|
||||||
|
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
|
||||||
|
#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */
|
||||||
|
#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
|
||||||
|
#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */
|
||||||
|
#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
|
||||||
|
#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */
|
||||||
|
#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_regular_rank ADC rank into regular group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_REGULAR_RANK_1 0x00000001U
|
||||||
|
#define ADC_REGULAR_RANK_2 0x00000002U
|
||||||
|
#define ADC_REGULAR_RANK_3 0x00000003U
|
||||||
|
#define ADC_REGULAR_RANK_4 0x00000004U
|
||||||
|
#define ADC_REGULAR_RANK_5 0x00000005U
|
||||||
|
#define ADC_REGULAR_RANK_6 0x00000006U
|
||||||
|
#define ADC_REGULAR_RANK_7 0x00000007U
|
||||||
|
#define ADC_REGULAR_RANK_8 0x00000008U
|
||||||
|
#define ADC_REGULAR_RANK_9 0x00000009U
|
||||||
|
#define ADC_REGULAR_RANK_10 0x0000000AU
|
||||||
|
#define ADC_REGULAR_RANK_11 0x0000000BU
|
||||||
|
#define ADC_REGULAR_RANK_12 0x0000000CU
|
||||||
|
#define ADC_REGULAR_RANK_13 0x0000000DU
|
||||||
|
#define ADC_REGULAR_RANK_14 0x0000000EU
|
||||||
|
#define ADC_REGULAR_RANK_15 0x0000000FU
|
||||||
|
#define ADC_REGULAR_RANK_16 0x00000010U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
|
||||||
|
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
|
||||||
|
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
|
||||||
|
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||||||
|
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
|
||||||
|
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
|
||||||
|
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_conversion_group ADC conversion group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
|
||||||
|
#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
|
||||||
|
#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_Event_type ADC Event type
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
|
||||||
|
|
||||||
|
#define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_interrupts_definition ADC interrupts definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
|
||||||
|
#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
|
||||||
|
#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_flags_definition ADC flags definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
|
||||||
|
#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
|
||||||
|
#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
|
||||||
|
#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
|
||||||
|
#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup ADC_Private_Constants ADC Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_conversion_cycles ADC conversion cycles
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* ADC conversion cycles (unit: ADC clock cycles) */
|
||||||
|
/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
|
||||||
|
/* resolution 12 bits) */
|
||||||
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
|
||||||
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
|
||||||
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
|
||||||
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
|
||||||
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
|
||||||
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
|
||||||
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
|
||||||
|
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
|
||||||
|
(ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
|
||||||
|
ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
|
||||||
|
ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
|
||||||
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
|
||||||
|
(ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
|
||||||
|
ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
|
||||||
|
|
||||||
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
|
||||||
|
(ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
|
||||||
|
ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
|
||||||
|
ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
|
||||||
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
|
||||||
|
(ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
|
||||||
|
ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
|
||||||
|
|
||||||
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
|
||||||
|
(ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
|
||||||
|
ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
|
||||||
|
ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
|
||||||
|
#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
|
||||||
|
(ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
|
||||||
|
ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
|
||||||
|
|
||||||
|
#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
|
||||||
|
#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
|
||||||
|
#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
|
||||||
|
#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
|
||||||
|
#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
|
||||||
|
#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
|
||||||
|
#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
|
||||||
|
#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
|
||||||
|
|
||||||
|
#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
|
||||||
|
#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
|
||||||
|
#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
|
||||||
|
#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
|
||||||
|
#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
|
||||||
|
#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
|
||||||
|
#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
|
||||||
|
#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
|
||||||
|
#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Macro for internal HAL driver usage, and possibly can be used into code of */
|
||||||
|
/* final user. */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the ADC peripheral
|
||||||
|
* @note ADC enable requires a delay for ADC stabilization time
|
||||||
|
* (refer to device datasheet, parameter tSTAB)
|
||||||
|
* @note On STM32F1, if ADC is already enabled this macro trigs a conversion
|
||||||
|
* SW start on regular group.
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_ADC_ENABLE(__HANDLE__) \
|
||||||
|
(SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the ADC peripheral
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_ADC_DISABLE(__HANDLE__) \
|
||||||
|
(CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
|
||||||
|
|
||||||
|
/** @brief Enable the ADC end of conversion interrupt.
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @param __INTERRUPT__: ADC Interrupt
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
|
||||||
|
* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
|
||||||
|
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||||
|
(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
|
||||||
|
|
||||||
|
/** @brief Disable the ADC end of conversion interrupt.
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @param __INTERRUPT__: ADC Interrupt
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
|
||||||
|
* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
|
||||||
|
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||||
|
(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
|
||||||
|
|
||||||
|
/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @param __INTERRUPT__: ADC interrupt source to check
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
|
||||||
|
* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
|
||||||
|
* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
|
||||||
|
(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||||
|
|
||||||
|
/** @brief Get the selected ADC's flag status.
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @param __FLAG__: ADC flag
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg ADC_FLAG_STRT: ADC Regular group start flag
|
||||||
|
* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
|
||||||
|
* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
|
||||||
|
* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
|
||||||
|
* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||||
|
((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clear the ADC's pending flags
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @param __FLAG__: ADC flag
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg ADC_FLAG_STRT: ADC Regular group start flag
|
||||||
|
* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
|
||||||
|
* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
|
||||||
|
* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
|
||||||
|
* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||||
|
(WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
|
||||||
|
|
||||||
|
/** @brief Reset ADC handle state
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
|
||||||
|
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_Private_Macros ADC Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
||||||
|
/* code of final user. */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Verification of ADC state: enabled or disabled
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval SET (ADC enabled) or RESET (ADC disabled)
|
||||||
|
*/
|
||||||
|
#define ADC_IS_ENABLE(__HANDLE__) \
|
||||||
|
((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
|
||||||
|
) ? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Test if conversion trigger of regular group is software start
|
||||||
|
* or external trigger.
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval SET (software start) or RESET (external trigger)
|
||||||
|
*/
|
||||||
|
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
|
||||||
|
(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Test if conversion trigger of injected group is software start
|
||||||
|
* or external trigger.
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval SET (software start) or RESET (external trigger)
|
||||||
|
*/
|
||||||
|
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
|
||||||
|
(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Simultaneously clears and sets specific bits of the handle State
|
||||||
|
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
|
||||||
|
* the first parameter is the ADC handle State, the second parameter is the
|
||||||
|
* bit field to clear, the third and last parameter is the bit field to set.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_STATE_CLR_SET MODIFY_REG
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear ADC error code (set it to error code: "no error")
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
|
||||||
|
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set ADC number of conversions into regular channel sequence length.
|
||||||
|
* @param _NbrOfConversion_: Regular channel sequence length
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
|
||||||
|
(((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
|
||||||
|
* @param _SAMPLETIME_: Sample time parameter.
|
||||||
|
* @param _CHANNELNB_: Channel number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
|
||||||
|
((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
|
||||||
|
* @param _SAMPLETIME_: Sample time parameter.
|
||||||
|
* @param _CHANNELNB_: Channel number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
|
||||||
|
((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the selected regular channel rank for rank between 1 and 6.
|
||||||
|
* @param _CHANNELNB_: Channel number.
|
||||||
|
* @param _RANKNB_: Rank number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
|
||||||
|
((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the selected regular channel rank for rank between 7 and 12.
|
||||||
|
* @param _CHANNELNB_: Channel number.
|
||||||
|
* @param _RANKNB_: Rank number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
|
||||||
|
((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the selected regular channel rank for rank between 13 and 16.
|
||||||
|
* @param _CHANNELNB_: Channel number.
|
||||||
|
* @param _RANKNB_: Rank number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
|
||||||
|
((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the injected sequence length.
|
||||||
|
* @param _JSQR_JL_: Sequence length.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
|
||||||
|
(((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the selected injected channel rank
|
||||||
|
* Note: on STM32F1 devices, channel rank position in JSQR register
|
||||||
|
* is depending on total number of ranks selected into
|
||||||
|
* injected sequencer (ranks sequence starting from 4-JL)
|
||||||
|
* @param _CHANNELNB_: Channel number.
|
||||||
|
* @param _RANKNB_: Rank number.
|
||||||
|
* @param _JSQR_JL_: Sequence length.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
|
||||||
|
((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable ADC continuous conversion mode.
|
||||||
|
* @param _CONTINUOUS_MODE_: Continuous mode.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
|
||||||
|
((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the number of discontinuous conversions for the regular group channels.
|
||||||
|
* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
|
||||||
|
(((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
|
||||||
|
* @param _SCAN_MODE_: Scan conversion mode.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
|
||||||
|
/* is equivalent to ADC_SCAN_ENABLE. */
|
||||||
|
#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
|
||||||
|
(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
|
||||||
|
)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
|
||||||
|
)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the maximum ADC conversion cycles on all channels.
|
||||||
|
* Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
|
||||||
|
* Approximation of sampling time within 4 ranges, returns the highest value:
|
||||||
|
* below 7.5 cycles {1.5 cycle; 7.5 cycles},
|
||||||
|
* between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
|
||||||
|
* between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
|
||||||
|
* equal to 239.5 cycles
|
||||||
|
* Unit: ADC clock cycles
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval ADC conversion cycles on all channels
|
||||||
|
*/
|
||||||
|
#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
|
||||||
|
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
|
||||||
|
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
|
||||||
|
\
|
||||||
|
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
|
||||||
|
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
|
||||||
|
ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
|
||||||
|
: \
|
||||||
|
((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
|
||||||
|
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
|
||||||
|
((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
|
||||||
|
(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
|
||||||
|
ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
|
||||||
|
((ALIGN) == ADC_DATAALIGN_LEFT) )
|
||||||
|
|
||||||
|
#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
|
||||||
|
((SCAN_MODE) == ADC_SCAN_ENABLE) )
|
||||||
|
|
||||||
|
#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
|
||||||
|
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
|
||||||
|
|
||||||
|
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_1) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_2) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_3) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_4) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_5) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_6) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_7) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_8) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_9) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_10) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_11) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_12) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_13) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_14) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_15) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_16) || \
|
||||||
|
((CHANNEL) == ADC_CHANNEL_17) )
|
||||||
|
|
||||||
|
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
|
||||||
|
((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
|
||||||
|
((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
|
||||||
|
((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
|
||||||
|
((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
|
||||||
|
((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
|
||||||
|
((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
|
||||||
|
((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
|
||||||
|
|
||||||
|
#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_10) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_11) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_12) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_13) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_14) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_15) || \
|
||||||
|
((CHANNEL) == ADC_REGULAR_RANK_16) )
|
||||||
|
|
||||||
|
#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
|
||||||
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||||
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||||
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||||
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||||||
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||||||
|
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
|
||||||
|
|
||||||
|
#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
|
||||||
|
((CONVERSION) == ADC_INJECTED_GROUP) || \
|
||||||
|
((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
|
||||||
|
|
||||||
|
#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup ADC_range_verification ADC range verification
|
||||||
|
* For a unique ADC resolution: 12 bits
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Include ADC HAL Extension module */
|
||||||
|
#include "stm32f1xx_hal_adc_ex.h"
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup ADC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ADC_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Initialization and de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
||||||
|
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
||||||
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
||||||
|
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* IO operation functions *****************************************************/
|
||||||
|
|
||||||
|
/** @addtogroup ADC_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Blocking mode: Polling */
|
||||||
|
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
||||||
|
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
||||||
|
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
||||||
|
|
||||||
|
/* Non-blocking mode: Interruption */
|
||||||
|
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
||||||
|
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
||||||
|
|
||||||
|
/* Non-blocking mode: DMA */
|
||||||
|
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||||||
|
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
||||||
|
|
||||||
|
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||||
|
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
||||||
|
|
||||||
|
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
|
||||||
|
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
||||||
|
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||||
|
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
||||||
|
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
||||||
|
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Peripheral Control functions ***********************************************/
|
||||||
|
/** @addtogroup ADC_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
||||||
|
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Peripheral State functions *************************************************/
|
||||||
|
/** @addtogroup ADC_Exported_Functions_Group4
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
||||||
|
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Internal HAL driver functions **********************************************/
|
||||||
|
/** @addtogroup ADC_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
|
||||||
|
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
|
||||||
|
void ADC_StabilizationTime(uint32_t DelayUs);
|
||||||
|
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
|
||||||
|
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
|
||||||
|
void ADC_DMAError(DMA_HandleTypeDef *hdma);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_ADC_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,728 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_adc_ex.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of ADC HAL extension module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_ADC_EX_H
|
||||||
|
#define __STM32F1xx_HAL_ADC_EX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ADCEx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC Configuration injected Channel structure definition
|
||||||
|
* @note Parameters of this structure are shared within 2 scopes:
|
||||||
|
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
|
||||||
|
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
|
||||||
|
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
|
||||||
|
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
|
||||||
|
* ADC state can be either:
|
||||||
|
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
|
||||||
|
* - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
|
||||||
|
This parameter can be a value of @ref ADC_channels
|
||||||
|
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
|
||||||
|
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
|
||||||
|
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
|
||||||
|
It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
|
||||||
|
Refer to errata sheet of these devices for more details. */
|
||||||
|
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
|
||||||
|
This parameter must be a value of @ref ADCEx_injected_rank
|
||||||
|
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
|
||||||
|
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||||
|
Unit: ADC clock cycles
|
||||||
|
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
|
||||||
|
This parameter can be a value of @ref ADC_sampling_times
|
||||||
|
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
|
||||||
|
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
|
||||||
|
Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
|
||||||
|
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||||
|
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
|
||||||
|
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
|
||||||
|
Offset value must be a positive number.
|
||||||
|
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
|
||||||
|
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
|
||||||
|
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
|
||||||
|
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||||
|
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||||
|
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||||
|
uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
||||||
|
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||||
|
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
|
||||||
|
This parameter can be set to ENABLE or DISABLE.
|
||||||
|
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
|
||||||
|
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||||
|
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||||
|
uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
|
||||||
|
This parameter can be set to ENABLE or DISABLE.
|
||||||
|
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||||
|
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
|
||||||
|
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
|
||||||
|
To maintain JAUTO always enabled, DMA must be configured in circular mode.
|
||||||
|
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||||
|
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||||
|
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
||||||
|
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
|
||||||
|
If set to external trigger source, triggering is on event rising edge.
|
||||||
|
This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
|
||||||
|
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||||
|
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
|
||||||
|
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||||
|
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||||
|
}ADC_InjectionConfTypeDef;
|
||||||
|
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/**
|
||||||
|
* @brief Structure definition of ADC multimode
|
||||||
|
* @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
|
||||||
|
* State of ADCs of the common group must be: disabled.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
|
||||||
|
This parameter can be a value of @ref ADCEx_Common_mode
|
||||||
|
Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
|
||||||
|
Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2.
|
||||||
|
Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode.
|
||||||
|
Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters).
|
||||||
|
The equivalences are:
|
||||||
|
- Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
|
||||||
|
- Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
|
||||||
|
|
||||||
|
|
||||||
|
}ADC_MultiModeTypeDef;
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_INJECTED_RANK_1 0x00000001U
|
||||||
|
#define ADC_INJECTED_RANK_2 0x00000002U
|
||||||
|
#define ADC_INJECTED_RANK_3 0x00000003U
|
||||||
|
#define ADC_INJECTED_RANK_4 0x00000004U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/*!< List of external triggers with generic trigger name, independently of */
|
||||||
|
/* ADC target, sorted by trigger name: */
|
||||||
|
|
||||||
|
/*!< External triggers of regular group for ADC1&ADC2 only */
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
|
||||||
|
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
|
||||||
|
|
||||||
|
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/*!< External triggers of regular group for ADC3 only */
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1
|
||||||
|
#endif /* STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/*!< External triggers of regular group for all ADC instances */
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
|
||||||
|
|
||||||
|
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
|
||||||
|
/* XL-density devices. */
|
||||||
|
/* To use it on ADC or ADC2, a remap of trigger must be done from */
|
||||||
|
/* EXTI line 11 to TIM8_TRGO with macro: */
|
||||||
|
/* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */
|
||||||
|
/* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */
|
||||||
|
|
||||||
|
/* Note for internal constant value management: If TIM8_TRGO is available, */
|
||||||
|
/* its definition is set to value for ADC1&ADC2 by default and changed to */
|
||||||
|
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
|
||||||
|
#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#define ADC_SOFTWARE_START ADC1_2_3_SWSTART
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/*!< List of external triggers with generic trigger name, independently of */
|
||||||
|
/* ADC target, sorted by trigger name: */
|
||||||
|
|
||||||
|
/*!< External triggers of injected group for ADC1&ADC2 only */
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
|
||||||
|
|
||||||
|
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/*!< External triggers of injected group for ADC3 only */
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4
|
||||||
|
#endif /* STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/*!< External triggers of injected group for all ADC instances */
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
|
||||||
|
|
||||||
|
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
|
||||||
|
/* XL-density devices. */
|
||||||
|
/* To use it on ADC1 or ADC2, a remap of trigger must be done from */
|
||||||
|
/* EXTI line 11 to TIM8_CC4 with macro: */
|
||||||
|
/* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */
|
||||||
|
/* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */
|
||||||
|
|
||||||
|
/* Note for internal constant value management: If TIM8_CC4 is available, */
|
||||||
|
/* its definition is set to value for ADC1&ADC2 by default and changed to */
|
||||||
|
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
|
||||||
|
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
|
||||||
|
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
|
||||||
|
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
|
||||||
|
#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
|
||||||
|
#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
|
||||||
|
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
|
||||||
|
#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
|
||||||
|
#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
|
||||||
|
#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
|
||||||
|
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */
|
||||||
|
/* instance is available on the selected device). */
|
||||||
|
/* (used internally by HAL driver. To not use into HAL structure parameters) */
|
||||||
|
|
||||||
|
/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
|
||||||
|
#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U
|
||||||
|
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))
|
||||||
|
#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||||
|
#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))
|
||||||
|
#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||||||
|
#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
|
||||||
|
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
|
||||||
|
/* XL-density devices. */
|
||||||
|
#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/* External triggers of regular group for ADC3 */
|
||||||
|
#define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
|
||||||
|
#define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2
|
||||||
|
#define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2
|
||||||
|
#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
|
||||||
|
#define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4
|
||||||
|
#define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
|
||||||
|
#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
|
||||||
|
#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */
|
||||||
|
/* instance is available on the selected device). */
|
||||||
|
/* (used internally by HAL driver. To not use into HAL structure parameters) */
|
||||||
|
|
||||||
|
/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
|
||||||
|
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
|
||||||
|
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||||
|
#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))
|
||||||
|
#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
|
||||||
|
#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
|
||||||
|
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
|
||||||
|
/* XL-density devices. */
|
||||||
|
#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/* External triggers of injected group for ADC3 */
|
||||||
|
#define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
|
||||||
|
#define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
|
||||||
|
#define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
|
||||||
|
#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
|
||||||
|
#define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
|
||||||
|
#endif /* STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
|
||||||
|
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
|
||||||
|
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))
|
||||||
|
#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
||||||
|
/* code of final user. */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief For devices with 3 ADCs: Defines the external trigger source
|
||||||
|
* for regular group according to ADC into common group ADC1&ADC2 or
|
||||||
|
* ADC3 (some triggers with same source have different value to
|
||||||
|
* be programmed into ADC EXTSEL bits of CR2 register).
|
||||||
|
* For devices with 2 ADCs or less: this macro makes no change.
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @param __EXT_TRIG_CONV__: External trigger selected for regular group.
|
||||||
|
* @retval External trigger to be programmed into EXTSEL bits of CR2 register
|
||||||
|
*/
|
||||||
|
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
|
||||||
|
(( (((__HANDLE__)->Instance) == ADC3) \
|
||||||
|
)? \
|
||||||
|
( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
|
||||||
|
)? \
|
||||||
|
(ADC3_EXTERNALTRIG_T8_TRGO) \
|
||||||
|
: \
|
||||||
|
(__EXT_TRIG_CONV__) \
|
||||||
|
) \
|
||||||
|
: \
|
||||||
|
(__EXT_TRIG_CONV__) \
|
||||||
|
)
|
||||||
|
#else
|
||||||
|
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
|
||||||
|
(__EXT_TRIG_CONV__)
|
||||||
|
#endif /* STM32F103xE || STM32F103xG */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief For devices with 3 ADCs: Defines the external trigger source
|
||||||
|
* for injected group according to ADC into common group ADC1&ADC2 or
|
||||||
|
* ADC3 (some triggers with same source have different value to
|
||||||
|
* be programmed into ADC JEXTSEL bits of CR2 register).
|
||||||
|
* For devices with 2 ADCs or less: this macro makes no change.
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
|
||||||
|
* @retval External trigger to be programmed into JEXTSEL bits of CR2 register
|
||||||
|
*/
|
||||||
|
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
|
||||||
|
(( (((__HANDLE__)->Instance) == ADC3) \
|
||||||
|
)? \
|
||||||
|
( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
|
||||||
|
)? \
|
||||||
|
(ADC3_EXTERNALTRIGINJEC_T8_CC4) \
|
||||||
|
: \
|
||||||
|
(__EXT_TRIG_INJECTCONV__) \
|
||||||
|
) \
|
||||||
|
: \
|
||||||
|
(__EXT_TRIG_INJECTCONV__) \
|
||||||
|
)
|
||||||
|
#else
|
||||||
|
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
|
||||||
|
(__EXT_TRIG_INJECTCONV__)
|
||||||
|
#endif /* STM32F103xE || STM32F103xG */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
|
||||||
|
*/
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
|
||||||
|
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
|
||||||
|
)? \
|
||||||
|
(ADC1->CR1 & ADC_CR1_DUALMOD) \
|
||||||
|
: \
|
||||||
|
(RESET) \
|
||||||
|
)
|
||||||
|
#else
|
||||||
|
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
|
||||||
|
(RESET)
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
|
||||||
|
(( (((__HANDLE__)->Instance) == ADC2) \
|
||||||
|
)? \
|
||||||
|
((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \
|
||||||
|
: \
|
||||||
|
(!RESET) \
|
||||||
|
)
|
||||||
|
#else
|
||||||
|
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
|
||||||
|
(!RESET)
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
|
||||||
|
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
|
||||||
|
)? \
|
||||||
|
(ADC1->CR1 & ADC_CR1_JAUTO) \
|
||||||
|
: \
|
||||||
|
(RESET) \
|
||||||
|
)
|
||||||
|
#else
|
||||||
|
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
|
||||||
|
(RESET)
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/**
|
||||||
|
* @brief Set handle of the other ADC sharing the common multimode settings
|
||||||
|
* @param __HANDLE__: ADC handle
|
||||||
|
* @param __HANDLE_OTHER_ADC__: other ADC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
|
||||||
|
((__HANDLE_OTHER_ADC__)->Instance = ADC2)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set handle of the ADC slave associated to the ADC master
|
||||||
|
* On STM32F1 devices, ADC slave is always ADC2 (this can be different
|
||||||
|
* on other STM32 devices)
|
||||||
|
* @param __HANDLE_MASTER__: ADC master handle
|
||||||
|
* @param __HANDLE_SLAVE__: ADC slave handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
|
||||||
|
((__HANDLE_SLAVE__)->Instance = ADC2)
|
||||||
|
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
|
||||||
|
((CHANNEL) == ADC_INJECTED_RANK_2) || \
|
||||||
|
((CHANNEL) == ADC_INJECTED_RANK_3) || \
|
||||||
|
((CHANNEL) == ADC_INJECTED_RANK_4))
|
||||||
|
|
||||||
|
#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
|
||||||
|
((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
|
||||||
|
|
||||||
|
/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||||
|
((REGTRIG) == ADC_SOFTWARE_START))
|
||||||
|
#endif
|
||||||
|
#if defined (STM32F101xE)
|
||||||
|
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_SOFTWARE_START))
|
||||||
|
#endif
|
||||||
|
#if defined (STM32F101xG)
|
||||||
|
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||||
|
((REGTRIG) == ADC_SOFTWARE_START))
|
||||||
|
#endif
|
||||||
|
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_SOFTWARE_START))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||||
|
#endif
|
||||||
|
#if defined (STM32F101xE)
|
||||||
|
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
|
||||||
|
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||||
|
#endif
|
||||||
|
#if defined (STM32F101xG)
|
||||||
|
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||||
|
#endif
|
||||||
|
#if defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
|
||||||
|
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
|
||||||
|
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
|
||||||
|
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
|
||||||
|
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
|
||||||
|
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
|
||||||
|
((MODE) == ADC_DUALMODE_INJECSIMULT) || \
|
||||||
|
((MODE) == ADC_DUALMODE_REGSIMULT) || \
|
||||||
|
((MODE) == ADC_DUALMODE_INTERLFAST) || \
|
||||||
|
((MODE) == ADC_DUALMODE_INTERLSLOW) || \
|
||||||
|
((MODE) == ADC_DUALMODE_ALTERTRIG) )
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup ADCEx_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* IO operation functions *****************************************************/
|
||||||
|
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ADC calibration */
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
|
||||||
|
|
||||||
|
/* Blocking mode: Polling */
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||||
|
|
||||||
|
/* Non-blocking mode: Interruption */
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
|
||||||
|
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/* ADC multimode */
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||||
|
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
|
||||||
|
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
|
||||||
|
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Peripheral Control functions ***********************************************/
|
||||||
|
/** @addtogroup ADCEx_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
|
||||||
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_ADC_EX_H */
|
||||||
|
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,798 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_can.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of CAN HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_CAN_H
|
||||||
|
#define __STM32F1xx_HAL_CAN_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
|
||||||
|
defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CAN
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup CAN_Exported_Types CAN Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
|
||||||
|
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
|
||||||
|
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
|
||||||
|
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
|
||||||
|
HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
|
||||||
|
HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
|
||||||
|
HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
|
||||||
|
HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
|
||||||
|
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
|
||||||
|
HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
|
||||||
|
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
|
||||||
|
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
|
||||||
|
|
||||||
|
}HAL_CAN_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CAN init structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
|
||||||
|
|
||||||
|
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
||||||
|
This parameter can be a value of @ref CAN_operating_mode */
|
||||||
|
|
||||||
|
uint32_t SJW; /*!< Specifies the maximum number of time quanta
|
||||||
|
the CAN hardware is allowed to lengthen or
|
||||||
|
shorten a bit to perform resynchronization.
|
||||||
|
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||||
|
|
||||||
|
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||||
|
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
|
||||||
|
|
||||||
|
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||||
|
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||||
|
|
||||||
|
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
|
||||||
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
|
|
||||||
|
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
|
|
||||||
|
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
|
|
||||||
|
uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
|
|
||||||
|
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||||
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
|
}CAN_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CAN Tx message structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
|
||||||
|
|
||||||
|
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
|
||||||
|
|
||||||
|
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||||
|
This parameter can be a value of @ref CAN_Identifier_Type */
|
||||||
|
|
||||||
|
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||||
|
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||||
|
|
||||||
|
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
|
||||||
|
|
||||||
|
uint8_t Data[8]; /*!< Contains the data to be transmitted.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
|
||||||
|
|
||||||
|
}CanTxMsgTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CAN Rx message structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
|
||||||
|
|
||||||
|
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
|
||||||
|
|
||||||
|
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
|
||||||
|
This parameter can be a value of @ref CAN_Identifier_Type */
|
||||||
|
|
||||||
|
uint32_t RTR; /*!< Specifies the type of frame for the received message.
|
||||||
|
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||||
|
|
||||||
|
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
|
||||||
|
|
||||||
|
uint8_t Data[8]; /*!< Contains the data to be received.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
|
||||||
|
|
||||||
|
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
|
||||||
|
|
||||||
|
uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
|
||||||
|
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
|
||||||
|
|
||||||
|
}CanRxMsgTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CAN handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
CAN_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
CAN_InitTypeDef Init; /*!< CAN required parameters */
|
||||||
|
|
||||||
|
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
|
||||||
|
|
||||||
|
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
|
||||||
|
|
||||||
|
CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
|
||||||
|
|
||||||
|
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< CAN locking object */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< CAN Error code */
|
||||||
|
|
||||||
|
}CAN_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup CAN_Exported_Constants CAN Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Error_Code CAN Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
|
||||||
|
#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
|
||||||
|
#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
|
||||||
|
#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
|
||||||
|
#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
|
||||||
|
#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
|
||||||
|
#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
|
||||||
|
#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
|
||||||
|
#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
|
||||||
|
#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
|
||||||
|
#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
|
||||||
|
#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
|
||||||
|
#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_InitStatus CAN initialization Status
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */
|
||||||
|
#define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_operating_mode CAN Operating Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
|
||||||
|
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
|
||||||
|
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
|
||||||
|
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
|
||||||
|
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
|
||||||
|
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
|
||||||
|
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
|
||||||
|
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
|
||||||
|
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
|
||||||
|
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
|
||||||
|
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
|
||||||
|
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
|
||||||
|
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
|
||||||
|
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
|
||||||
|
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
|
||||||
|
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
|
||||||
|
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
|
||||||
|
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
|
||||||
|
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
|
||||||
|
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
|
||||||
|
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
|
||||||
|
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
|
||||||
|
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
|
||||||
|
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
|
||||||
|
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
|
||||||
|
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
||||||
|
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
|
||||||
|
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
|
||||||
|
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_filter_mode CAN Filter Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
|
||||||
|
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_filter_scale CAN Filter Scale
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||||
|
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||||
|
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Identifier_Type CAN Identifier Type
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_ID_STD 0x00000000U /*!< Standard Id */
|
||||||
|
#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
|
||||||
|
#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_transmit_constants CAN Transmit Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||||
|
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_flags CAN Flags
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||||
|
and CAN_ClearFlag() functions. */
|
||||||
|
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||||
|
CAN_GetFlagStatus() function. */
|
||||||
|
|
||||||
|
/* Transmit Flags */
|
||||||
|
#define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */
|
||||||
|
#define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */
|
||||||
|
#define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */
|
||||||
|
#define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */
|
||||||
|
#define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */
|
||||||
|
#define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */
|
||||||
|
#define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
|
||||||
|
#define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
|
||||||
|
#define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
|
||||||
|
|
||||||
|
/* Receive Flags */
|
||||||
|
#define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */
|
||||||
|
#define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
|
||||||
|
|
||||||
|
#define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */
|
||||||
|
#define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
|
||||||
|
|
||||||
|
/* Operating Mode Flags */
|
||||||
|
#define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
|
||||||
|
#define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
|
||||||
|
#define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
|
||||||
|
|
||||||
|
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||||
|
In this case the SLAK bit can be polled.*/
|
||||||
|
|
||||||
|
/* Error Flags */
|
||||||
|
#define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */
|
||||||
|
#define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */
|
||||||
|
#define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Interrupts CAN Interrupts
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||||
|
|
||||||
|
/* Receive Interrupts */
|
||||||
|
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||||
|
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||||
|
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||||
|
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||||
|
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||||
|
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||||
|
|
||||||
|
/* Operating Mode Interrupts */
|
||||||
|
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||||
|
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||||
|
|
||||||
|
/* Error Interrupts */
|
||||||
|
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||||
|
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||||
|
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||||
|
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||||
|
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Private_Constants CAN Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* CAN intermediate shift values used for CAN flags */
|
||||||
|
#define TSR_REGISTER_INDEX 0x5U
|
||||||
|
#define RF0R_REGISTER_INDEX 0x2U
|
||||||
|
#define RF1R_REGISTER_INDEX 0x4U
|
||||||
|
#define MSR_REGISTER_INDEX 0x1U
|
||||||
|
#define ESR_REGISTER_INDEX 0x3U
|
||||||
|
|
||||||
|
/* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
|
||||||
|
/* Transmit Flags */
|
||||||
|
#define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
|
||||||
|
#define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
|
||||||
|
#define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
|
||||||
|
#define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
|
||||||
|
#define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
|
||||||
|
#define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
|
||||||
|
#define CAN_TSR_TME0_BIT_POSITION 0x0000001AU
|
||||||
|
#define CAN_TSR_TME1_BIT_POSITION 0x0000001BU
|
||||||
|
#define CAN_TSR_TME2_BIT_POSITION 0x0000001CU
|
||||||
|
|
||||||
|
/* Receive Flags */
|
||||||
|
#define CAN_RF0R_FF0_BIT_POSITION 0x00000003U
|
||||||
|
#define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
|
||||||
|
|
||||||
|
#define CAN_RF1R_FF1_BIT_POSITION 0x00000003U
|
||||||
|
#define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
|
||||||
|
|
||||||
|
/* Operating Mode Flags */
|
||||||
|
#define CAN_MSR_WKU_BIT_POSITION 0x00000003U
|
||||||
|
#define CAN_MSR_SLAK_BIT_POSITION 0x00000001U
|
||||||
|
#define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
|
||||||
|
|
||||||
|
/* Error Flags */
|
||||||
|
#define CAN_ESR_EWG_BIT_POSITION 0x00000000U
|
||||||
|
#define CAN_ESR_EPV_BIT_POSITION 0x00000001U
|
||||||
|
#define CAN_ESR_BOF_BIT_POSITION 0x00000002U
|
||||||
|
|
||||||
|
/* Mask used by macro to get/clear CAN flags*/
|
||||||
|
#define CAN_FLAG_MASK 0x000000FFU
|
||||||
|
|
||||||
|
/* Mailboxes definition */
|
||||||
|
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
|
||||||
|
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
|
||||||
|
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset CAN handle state
|
||||||
|
* @param __HANDLE__: CAN handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the specified CAN interrupts
|
||||||
|
* @param __HANDLE__: CAN handle.
|
||||||
|
* @param __INTERRUPT__: CAN Interrupt.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||||
|
* @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
|
||||||
|
* @arg CAN_IT_FF0 : FIFO 0 full interrupt
|
||||||
|
* @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
|
||||||
|
* @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
|
||||||
|
* @arg CAN_IT_FF1 : FIFO 1 full interrupt
|
||||||
|
* @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
|
||||||
|
* @arg CAN_IT_WKU : Wake-up interrupt
|
||||||
|
* @arg CAN_IT_SLK : Sleep acknowledge interrupt
|
||||||
|
* @arg CAN_IT_EWG : Error warning interrupt
|
||||||
|
* @arg CAN_IT_EPV : Error passive interrupt
|
||||||
|
* @arg CAN_IT_BOF : Bus-off interrupt
|
||||||
|
* @arg CAN_IT_LEC : Last error code interrupt
|
||||||
|
* @arg CAN_IT_ERR : Error Interrupt
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the specified CAN interrupts
|
||||||
|
* @param __HANDLE__: CAN handle.
|
||||||
|
* @param __INTERRUPT__: CAN Interrupt.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||||
|
* @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
|
||||||
|
* @arg CAN_IT_FF0 : FIFO 0 full interrupt
|
||||||
|
* @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
|
||||||
|
* @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
|
||||||
|
* @arg CAN_IT_FF1 : FIFO 1 full interrupt
|
||||||
|
* @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
|
||||||
|
* @arg CAN_IT_WKU : Wake-up interrupt
|
||||||
|
* @arg CAN_IT_SLK : Sleep acknowledge interrupt
|
||||||
|
* @arg CAN_IT_EWG : Error warning interrupt
|
||||||
|
* @arg CAN_IT_EPV : Error passive interrupt
|
||||||
|
* @arg CAN_IT_BOF : Bus-off interrupt
|
||||||
|
* @arg CAN_IT_LEC : Last error code interrupt
|
||||||
|
* @arg CAN_IT_ERR : Error Interrupt
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the number of pending received messages.
|
||||||
|
* @param __HANDLE__: CAN handle.
|
||||||
|
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||||
|
* @retval The number of pending message.
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||||
|
((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
|
||||||
|
|
||||||
|
/** @brief Check whether the specified CAN flag is set or not.
|
||||||
|
* @param __HANDLE__: specifies the CAN Handle.
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||||
|
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||||
|
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||||
|
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||||
|
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||||
|
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||||
|
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||||
|
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||||
|
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||||
|
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||||
|
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||||
|
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||||
|
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||||
|
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||||
|
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||||
|
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||||
|
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||||||
|
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||||
|
* @arg CAN_FLAG_EWG: Error Warning Flag
|
||||||
|
* @arg CAN_FLAG_EPV: Error Passive Flag
|
||||||
|
* @arg CAN_FLAG_BOF: Bus-Off Flag
|
||||||
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||||
|
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||||
|
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||||
|
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||||
|
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||||
|
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
|
||||||
|
|
||||||
|
/** @brief Clear the specified CAN pending flag.
|
||||||
|
* @param __HANDLE__: specifies the CAN Handle.
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
|
||||||
|
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
|
||||||
|
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
|
||||||
|
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
|
||||||
|
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
|
||||||
|
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
|
||||||
|
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
|
||||||
|
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
|
||||||
|
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
|
||||||
|
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||||||
|
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||||||
|
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||||||
|
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||||||
|
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||||||
|
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||||||
|
* @arg CAN_FLAG_WKU: Wake up Flag
|
||||||
|
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
|
||||||
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||||
|
((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||||
|
(((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||||
|
(((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||||
|
(((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
|
||||||
|
|
||||||
|
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||||
|
* @param __HANDLE__: specifies the CAN Handle.
|
||||||
|
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
|
||||||
|
* @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
|
||||||
|
* @arg CAN_IT_FF0 : FIFO 0 full interrupt
|
||||||
|
* @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
|
||||||
|
* @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
|
||||||
|
* @arg CAN_IT_FF1 : FIFO 1 full interrupt
|
||||||
|
* @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
|
||||||
|
* @arg CAN_IT_WKU : Wake-up interrupt
|
||||||
|
* @arg CAN_IT_SLK : Sleep acknowledge interrupt
|
||||||
|
* @arg CAN_IT_EWG : Error warning interrupt
|
||||||
|
* @arg CAN_IT_EPV : Error passive interrupt
|
||||||
|
* @arg CAN_IT_BOF : Bus-off interrupt
|
||||||
|
* @arg CAN_IT_LEC : Last error code interrupt
|
||||||
|
* @arg CAN_IT_ERR : Error Interrupt
|
||||||
|
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check the transmission status of a CAN Frame.
|
||||||
|
* @param __HANDLE__: specifies the CAN Handle.
|
||||||
|
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||||
|
* @retval The new status of transmission (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||||
|
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
|
||||||
|
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
|
||||||
|
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Release the specified receive FIFO.
|
||||||
|
* @param __HANDLE__: CAN handle.
|
||||||
|
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
|
||||||
|
((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cancel a transmit request.
|
||||||
|
* @param __HANDLE__: specifies the CAN Handle.
|
||||||
|
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
|
||||||
|
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
|
||||||
|
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
|
||||||
|
((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable or disables the DBG Freeze for CAN.
|
||||||
|
* @param __HANDLE__: specifies the CAN Handle.
|
||||||
|
* @param __NEWSTATE__: new state of the CAN peripheral.
|
||||||
|
* This parameter can be: ENABLE (CAN reception/transmission is frozen
|
||||||
|
* during debug. Reception FIFOs can still be accessed/controlled normally)
|
||||||
|
* or DISABLE (CAN is working during debug).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
|
||||||
|
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Include CAN HAL Extension module */
|
||||||
|
#include "stm32f1xx_hal_can_ex.h"
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup CAN_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CAN_Exported_Functions_Group1
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization and de-initialization functions *****************************/
|
||||||
|
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
|
||||||
|
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
|
||||||
|
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
|
||||||
|
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
|
||||||
|
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CAN_Exported_Functions_Group2
|
||||||
|
* @brief I/O operation functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* I/O operation functions *****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
|
||||||
|
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
|
||||||
|
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
|
||||||
|
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||||
|
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
|
||||||
|
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||||
|
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
|
||||||
|
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CAN_Exported_Functions_Group3
|
||||||
|
* @brief CAN Peripheral State functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral State and Error functions ***************************************/
|
||||||
|
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||||
|
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros --------------------------------------------------------*/
|
||||||
|
/** @defgroup CAN_Private_Macros CAN Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||||
|
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||||
|
((MODE) == CAN_MODE_SILENT) || \
|
||||||
|
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||||
|
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
|
||||||
|
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||||
|
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
|
||||||
|
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
|
||||||
|
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
|
||||||
|
|
||||||
|
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||||
|
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||||
|
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||||
|
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||||
|
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||||
|
((FIFO) == CAN_FILTER_FIFO1))
|
||||||
|
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
|
||||||
|
|
||||||
|
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||||
|
#define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
|
||||||
|
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
|
||||||
|
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||||
|
|
||||||
|
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||||
|
((IDTYPE) == CAN_ID_EXT))
|
||||||
|
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||||
|
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_CAN_H */
|
||||||
|
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,146 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_can_ex.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of CAN HAL Extension module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_CAN_EX_H
|
||||||
|
#define __STM32F1xx_HAL_CAN_EX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
|
||||||
|
defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CANEx CANEx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CAN filter configuration structure definition
|
||||||
|
*/
|
||||||
|
/* CAN filter banks differences over STM32F1 devices: */
|
||||||
|
/* - STM32F1 Connectivity line: 28 filter banks shared between CAN1 and CAN2 */
|
||||||
|
/* - Other STM32F10x devices: 14 filter banks */
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||||
|
configuration, first one for a 16-bit configuration).
|
||||||
|
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||||
|
|
||||||
|
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||||
|
configuration, second one for a 16-bit configuration).
|
||||||
|
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||||
|
|
||||||
|
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||||
|
according to the mode (MSBs for a 32-bit configuration,
|
||||||
|
first one for a 16-bit configuration).
|
||||||
|
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||||
|
|
||||||
|
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||||
|
according to the mode (LSBs for a 32-bit configuration,
|
||||||
|
second one for a 16-bit configuration).
|
||||||
|
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||||
|
|
||||||
|
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||||
|
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||||
|
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
|
||||||
|
#else
|
||||||
|
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 13. */
|
||||||
|
#endif /* STM32F105xC || STM32F107xC */
|
||||||
|
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||||
|
This parameter can be a value of @ref CAN_filter_mode */
|
||||||
|
|
||||||
|
uint32_t FilterScale; /*!< Specifies the filter scale.
|
||||||
|
This parameter can be a value of @ref CAN_filter_scale */
|
||||||
|
|
||||||
|
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||||
|
This parameter can be set to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
uint32_t BankNumber; /*!< Select the start slave bank filter
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
|
||||||
|
|
||||||
|
}CAN_FilterConfTypeDef;
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup CANEx_Private_Macros CAN Extended Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
|
||||||
|
#else
|
||||||
|
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U)
|
||||||
|
#endif /* STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_CAN_EX_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,518 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_cec.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of CEC HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_CEC_H
|
||||||
|
#define __STM32F1xx_HAL_CEC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F100xB) || defined(STM32F100xE)
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CEC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Exported_Types CEC Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief CEC Init Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
|
||||||
|
This parameter can be a value of @ref CEC_BitTimingErrorMode */
|
||||||
|
uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
|
||||||
|
This parameter can be a value of @ref CEC_BitPeriodErrorMode */
|
||||||
|
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||||
|
This parameter can be a value of @ref CEC_OWN_ADDRESS */
|
||||||
|
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
|
||||||
|
}CEC_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL CEC State structures definition
|
||||||
|
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
|
||||||
|
* - gState contains CEC state information related to global Handle management
|
||||||
|
* and also information related to Tx operations.
|
||||||
|
* gState value coding follow below described bitmap :
|
||||||
|
* b7 (not used)
|
||||||
|
* x : Should be set to 0
|
||||||
|
* b6 Error information
|
||||||
|
* 0 : No Error
|
||||||
|
* 1 : Error
|
||||||
|
* b5 IP initilisation status
|
||||||
|
* 0 : Reset (IP not initialized)
|
||||||
|
* 1 : Init done (IP initialized. HAL CEC Init function already called)
|
||||||
|
* b4-b3 (not used)
|
||||||
|
* xx : Should be set to 00
|
||||||
|
* b2 Intrinsic process state
|
||||||
|
* 0 : Ready
|
||||||
|
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||||
|
* b1 (not used)
|
||||||
|
* x : Should be set to 0
|
||||||
|
* b0 Tx state
|
||||||
|
* 0 : Ready (no Tx operation ongoing)
|
||||||
|
* 1 : Busy (Tx operation ongoing)
|
||||||
|
* - RxState contains information related to Rx operations.
|
||||||
|
* RxState value coding follow below described bitmap :
|
||||||
|
* b7-b6 (not used)
|
||||||
|
* xx : Should be set to 00
|
||||||
|
* b5 IP initilisation status
|
||||||
|
* 0 : Reset (IP not initialized)
|
||||||
|
* 1 : Init done (IP initialized)
|
||||||
|
* b4-b2 (not used)
|
||||||
|
* xxx : Should be set to 000
|
||||||
|
* b1 Rx state
|
||||||
|
* 0 : Ready (no Rx operation ongoing)
|
||||||
|
* 1 : Busy (Rx operation ongoing)
|
||||||
|
* b0 (not used)
|
||||||
|
* x : Should be set to 0.
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||||
|
Value is allowed for gState and RxState */
|
||||||
|
HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||||
|
Value is allowed for gState and RxState */
|
||||||
|
HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
||||||
|
Value is allowed for gState only */
|
||||||
|
HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||||
|
Value is allowed for RxState only */
|
||||||
|
HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||||
|
Value is allowed for gState only */
|
||||||
|
HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
|
||||||
|
Value is allowed for gState only */
|
||||||
|
HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
|
||||||
|
}HAL_CEC_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CEC handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
CEC_TypeDef *Instance; /*!< CEC registers base address */
|
||||||
|
|
||||||
|
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||||
|
|
||||||
|
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||||
|
|
||||||
|
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||||
|
|
||||||
|
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||||
|
|
||||||
|
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
||||||
|
and also related to Tx operations.
|
||||||
|
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||||
|
|
||||||
|
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
||||||
|
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||||
|
|
||||||
|
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
||||||
|
in case error is reported */
|
||||||
|
}CEC_HandleTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Exported_Constants CEC Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Error_Code CEC Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
|
||||||
|
#define HAL_CEC_ERROR_BTE CEC_ESR_BTE /*!< Bit Timing Error */
|
||||||
|
#define HAL_CEC_ERROR_BPE CEC_ESR_BPE /*!< Bit Period Error */
|
||||||
|
#define HAL_CEC_ERROR_RBTFE CEC_ESR_RBTFE /*!< Rx Block Transfer Finished Error */
|
||||||
|
#define HAL_CEC_ERROR_SBE CEC_ESR_SBE /*!< Start Bit Error */
|
||||||
|
#define HAL_CEC_ERROR_ACKE CEC_ESR_ACKE /*!< Block Acknowledge Error */
|
||||||
|
#define HAL_CEC_ERROR_LINE CEC_ESR_LINE /*!< Line Error */
|
||||||
|
#define HAL_CEC_ERROR_TBTFE CEC_ESR_TBTFE /*!< Tx Block Transfer Finished Error */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_BIT_TIMING_ERROR_MODE_STANDARD 0x00000000U /*!< Bit timing error Standard Mode */
|
||||||
|
#define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U /*!< Bit period error Standard Mode */
|
||||||
|
#define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_INITIATOR_LSB_POS 4U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_OWN_ADDRESS_NONE CEC_OWN_ADDRESS_0 /* Reset value */
|
||||||
|
#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0000U) /* Logical Address 0 */
|
||||||
|
#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0001U) /* Logical Address 1 */
|
||||||
|
#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0002U) /* Logical Address 2 */
|
||||||
|
#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0003U) /* Logical Address 3 */
|
||||||
|
#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0004U) /* Logical Address 4 */
|
||||||
|
#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0005U) /* Logical Address 5 */
|
||||||
|
#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0006U) /* Logical Address 6 */
|
||||||
|
#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0007U) /* Logical Address 7 */
|
||||||
|
#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0008U) /* Logical Address 8 */
|
||||||
|
#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0009U) /* Logical Address 9 */
|
||||||
|
#define CEC_OWN_ADDRESS_10 ((uint16_t)0x000AU) /* Logical Address 10 */
|
||||||
|
#define CEC_OWN_ADDRESS_11 ((uint16_t)0x000BU) /* Logical Address 11 */
|
||||||
|
#define CEC_OWN_ADDRESS_12 ((uint16_t)0x000CU) /* Logical Address 12 */
|
||||||
|
#define CEC_OWN_ADDRESS_13 ((uint16_t)0x000DU) /* Logical Address 13 */
|
||||||
|
#define CEC_OWN_ADDRESS_14 ((uint16_t)0x000EU) /* Logical Address 14 */
|
||||||
|
#define CEC_OWN_ADDRESS_15 ((uint16_t)0x000FU) /* Logical Address 15 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Interrupts_Definitions Interrupts definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_IT_IE CEC_CFGR_IE
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Flags_Definitions Flags definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_FLAG_TSOM CEC_CSR_TSOM
|
||||||
|
#define CEC_FLAG_TEOM CEC_CSR_TEOM
|
||||||
|
#define CEC_FLAG_TERR CEC_CSR_TERR
|
||||||
|
#define CEC_FLAG_TBTRF CEC_CSR_TBTRF
|
||||||
|
#define CEC_FLAG_RSOM CEC_CSR_RSOM
|
||||||
|
#define CEC_FLAG_REOM CEC_CSR_REOM
|
||||||
|
#define CEC_FLAG_RERR CEC_CSR_RERR
|
||||||
|
#define CEC_FLAG_RBTF CEC_CSR_RBTF
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Exported_Macros CEC Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset CEC handle gstate & RxState
|
||||||
|
* @param __HANDLE__: CEC handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||||
|
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||||
|
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* @arg CEC_FLAG_TERR: Tx Error
|
||||||
|
* @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
|
||||||
|
* @arg CEC_FLAG_RERR: Rx Error
|
||||||
|
* @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
|
||||||
|
* @retval ITStatus
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clears the CEC's pending flags.
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @param __FLAG__: specifies the flag to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg CEC_CSR_TERR: Tx Error
|
||||||
|
* @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
|
||||||
|
* @arg CEC_CSR_RERR: Rx Error
|
||||||
|
* @arg CEC_CSR_RBTF: Rx Block Transfer Finished
|
||||||
|
* @retval none
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||||
|
do { \
|
||||||
|
uint32_t tmp = 0x0U; \
|
||||||
|
tmp = (__HANDLE__)->Instance->CSR & 0x00000002U; \
|
||||||
|
(__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Enables the specified CEC interrupt.
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @param __INTERRUPT__: specifies the CEC interrupt to enable.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg CEC_IT_IE : Interrupt Enable.
|
||||||
|
* @retval none
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/** @brief Disables the specified CEC interrupt.
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @param __INTERRUPT__: specifies the CEC interrupt to disable.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg CEC_IT_IE : Interrupt Enable
|
||||||
|
* @retval none
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @param __INTERRUPT__: specifies the CEC interrupt to check.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg CEC_IT_IE : Interrupt Enable
|
||||||
|
* @retval FlagStatus
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/** @brief Enables the CEC device
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @retval none
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
|
||||||
|
|
||||||
|
/** @brief Disables the CEC device
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @retval none
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
|
||||||
|
|
||||||
|
/** @brief Set Transmission Start flag
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @retval none
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
|
||||||
|
|
||||||
|
/** @brief Set Transmission End flag
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @retval none
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
|
||||||
|
|
||||||
|
/** @brief Get Transmission Start flag
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @retval FlagStatus
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
|
||||||
|
|
||||||
|
/** @brief Get Transmission End flag
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @retval FlagStatus
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
|
||||||
|
|
||||||
|
/** @brief Clear OAR register
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @retval none
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
|
||||||
|
|
||||||
|
/** @brief Set OAR register
|
||||||
|
* @param __HANDLE__: specifies the CEC Handle.
|
||||||
|
* @param __ADDRESS__: Own Address value.
|
||||||
|
* @retval none
|
||||||
|
*/
|
||||||
|
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup CEC_Exported_Functions CEC Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization and de-initialization functions ****************************/
|
||||||
|
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||||||
|
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||||||
|
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
|
||||||
|
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||||||
|
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
|
||||||
|
* @brief CEC Transmit/Receive functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* I/O operation functions ***************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
|
||||||
|
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
|
||||||
|
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
|
||||||
|
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||||
|
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||||
|
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
|
||||||
|
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
|
||||||
|
* @brief CEC control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral State and Error functions ***************************************/
|
||||||
|
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
|
||||||
|
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Private_Types CEC Private Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Private_Variables CEC Private Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Private_Macros CEC Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
|
||||||
|
((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
|
||||||
|
|
||||||
|
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
|
||||||
|
((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
|
||||||
|
|
||||||
|
/** @brief Check CEC message size.
|
||||||
|
* The message size is the payload size: without counting the header,
|
||||||
|
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||||||
|
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||||||
|
* @param __SIZE__: CEC message size.
|
||||||
|
* @retval Test result (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
|
||||||
|
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||||||
|
* @param __ADDRESS__: CEC own address.
|
||||||
|
* @retval Test result (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
|
||||||
|
|
||||||
|
/** @brief Check CEC initiator or destination logical address setting.
|
||||||
|
* Initiator and destination addresses are coded over 4 bits.
|
||||||
|
* @param __ADDRESS__: CEC initiator or logical address.
|
||||||
|
* @retval Test result (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* defined(STM32F100xB) || defined(STM32F100xE) */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_CEC_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,383 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_conf.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief HAL configuration template file.
|
||||||
|
* This file should be copied to the application folder and renamed
|
||||||
|
* to stm32f1xx_hal_conf.h.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_CONF_H
|
||||||
|
#define __STM32F1xx_HAL_CONF_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* ########################## Module Selection ############################## */
|
||||||
|
/**
|
||||||
|
* @brief This is the list of modules to be used in the HAL driver
|
||||||
|
*/
|
||||||
|
#define HAL_MODULE_ENABLED
|
||||||
|
#define HAL_ADC_MODULE_ENABLED
|
||||||
|
#define HAL_CAN_MODULE_ENABLED
|
||||||
|
#define HAL_CEC_MODULE_ENABLED
|
||||||
|
#define HAL_CORTEX_MODULE_ENABLED
|
||||||
|
#define HAL_CRC_MODULE_ENABLED
|
||||||
|
#define HAL_DAC_MODULE_ENABLED
|
||||||
|
#define HAL_DMA_MODULE_ENABLED
|
||||||
|
#define HAL_ETH_MODULE_ENABLED
|
||||||
|
#define HAL_FLASH_MODULE_ENABLED
|
||||||
|
#define HAL_GPIO_MODULE_ENABLED
|
||||||
|
#define HAL_HCD_MODULE_ENABLED
|
||||||
|
#define HAL_I2C_MODULE_ENABLED
|
||||||
|
#define HAL_I2S_MODULE_ENABLED
|
||||||
|
#define HAL_IRDA_MODULE_ENABLED
|
||||||
|
#define HAL_IWDG_MODULE_ENABLED
|
||||||
|
#define HAL_NAND_MODULE_ENABLED
|
||||||
|
#define HAL_NOR_MODULE_ENABLED
|
||||||
|
#define HAL_PCCARD_MODULE_ENABLED
|
||||||
|
#define HAL_PCD_MODULE_ENABLED
|
||||||
|
#define HAL_PWR_MODULE_ENABLED
|
||||||
|
#define HAL_RCC_MODULE_ENABLED
|
||||||
|
#define HAL_RTC_MODULE_ENABLED
|
||||||
|
#define HAL_SD_MODULE_ENABLED
|
||||||
|
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||||
|
#define HAL_SPI_MODULE_ENABLED
|
||||||
|
#define HAL_SRAM_MODULE_ENABLED
|
||||||
|
#define HAL_TIM_MODULE_ENABLED
|
||||||
|
#define HAL_UART_MODULE_ENABLED
|
||||||
|
#define HAL_USART_MODULE_ENABLED
|
||||||
|
#define HAL_WWDG_MODULE_ENABLED
|
||||||
|
#define HAL_MMC_MODULE_ENABLED
|
||||||
|
|
||||||
|
/* ########################## Oscillator Values adaptation ####################*/
|
||||||
|
/**
|
||||||
|
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||||
|
* This value is used by the RCC HAL module to compute the system frequency
|
||||||
|
* (when HSE is used as system clock source, directly or through the PLL).
|
||||||
|
*/
|
||||||
|
#if !defined (HSE_VALUE)
|
||||||
|
#if defined(USE_STM3210C_EVAL)
|
||||||
|
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
|
||||||
|
#else
|
||||||
|
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
|
||||||
|
#endif
|
||||||
|
#endif /* HSE_VALUE */
|
||||||
|
|
||||||
|
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||||
|
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
|
||||||
|
#endif /* HSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Internal High Speed oscillator (HSI) value.
|
||||||
|
* This value is used by the RCC HAL module to compute the system frequency
|
||||||
|
* (when HSI is used as system clock source, directly or through the PLL).
|
||||||
|
*/
|
||||||
|
#if !defined (HSI_VALUE)
|
||||||
|
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
|
||||||
|
#endif /* HSI_VALUE */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Internal Low Speed oscillator (LSI) value.
|
||||||
|
*/
|
||||||
|
#if !defined (LSI_VALUE)
|
||||||
|
#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
|
||||||
|
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||||
|
The real value may vary depending on the variations
|
||||||
|
in voltage and temperature. */
|
||||||
|
/**
|
||||||
|
* @brief External Low Speed oscillator (LSE) value.
|
||||||
|
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||||
|
*/
|
||||||
|
#if !defined (LSE_VALUE)
|
||||||
|
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
|
||||||
|
#endif /* LSE_VALUE */
|
||||||
|
|
||||||
|
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||||
|
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
|
||||||
|
#endif /* LSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
|
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||||
|
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||||
|
|
||||||
|
/* ########################### System Configuration ######################### */
|
||||||
|
/**
|
||||||
|
* @brief This is the HAL system configuration section
|
||||||
|
*/
|
||||||
|
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
|
||||||
|
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
|
||||||
|
#define USE_RTOS 0U
|
||||||
|
#define PREFETCH_ENABLE 1U
|
||||||
|
|
||||||
|
/* ########################## Assert Selection ############################## */
|
||||||
|
/**
|
||||||
|
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||||
|
* HAL drivers code
|
||||||
|
*/
|
||||||
|
/* #define USE_FULL_ASSERT 1U */
|
||||||
|
|
||||||
|
/* ################## Ethernet peripheral configuration ##################### */
|
||||||
|
|
||||||
|
/* Section 1 : Ethernet peripheral configuration */
|
||||||
|
|
||||||
|
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||||
|
#define MAC_ADDR0 2U
|
||||||
|
#define MAC_ADDR1 0U
|
||||||
|
#define MAC_ADDR2 0U
|
||||||
|
#define MAC_ADDR3 0U
|
||||||
|
#define MAC_ADDR4 0U
|
||||||
|
#define MAC_ADDR5 0U
|
||||||
|
|
||||||
|
/* Definition of the Ethernet driver buffers size and count */
|
||||||
|
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||||
|
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||||
|
#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||||
|
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||||
|
|
||||||
|
/* Section 2: PHY configuration section */
|
||||||
|
|
||||||
|
/* DP83848 PHY Address*/
|
||||||
|
#define DP83848_PHY_ADDRESS 0x01U
|
||||||
|
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||||
|
#define PHY_RESET_DELAY 0x000000FFU
|
||||||
|
/* PHY Configuration delay */
|
||||||
|
#define PHY_CONFIG_DELAY 0x00000FFFU
|
||||||
|
|
||||||
|
#define PHY_READ_TO 0x0000FFFFU
|
||||||
|
#define PHY_WRITE_TO 0x0000FFFFU
|
||||||
|
|
||||||
|
/* Section 3: Common PHY Registers */
|
||||||
|
|
||||||
|
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
|
||||||
|
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
|
||||||
|
|
||||||
|
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
||||||
|
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
||||||
|
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||||
|
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||||
|
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||||
|
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||||
|
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
||||||
|
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
||||||
|
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
||||||
|
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
||||||
|
|
||||||
|
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||||
|
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
||||||
|
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||||
|
|
||||||
|
/* Section 4: Extended PHY Registers */
|
||||||
|
|
||||||
|
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
|
||||||
|
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
|
||||||
|
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
|
||||||
|
|
||||||
|
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
|
||||||
|
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
|
||||||
|
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
|
||||||
|
|
||||||
|
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
|
||||||
|
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
|
||||||
|
|
||||||
|
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
|
||||||
|
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
|
||||||
|
|
||||||
|
/* ################## SPI peripheral configuration ########################## */
|
||||||
|
|
||||||
|
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||||
|
* Activated: CRC code is present inside driver
|
||||||
|
* Deactivated: CRC code cleaned from driver
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USE_SPI_CRC 1U
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
/**
|
||||||
|
* @brief Include module's header file
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_RCC_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_rcc.h"
|
||||||
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_gpio.h"
|
||||||
|
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DMA_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_dma.h"
|
||||||
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_ETH_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_eth.h"
|
||||||
|
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CAN_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_can.h"
|
||||||
|
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CEC_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_cec.h"
|
||||||
|
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_cortex.h"
|
||||||
|
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_ADC_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_adc.h"
|
||||||
|
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CRC_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_crc.h"
|
||||||
|
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DAC_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_dac.h"
|
||||||
|
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_flash.h"
|
||||||
|
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_sram.h"
|
||||||
|
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_NOR_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_nor.h"
|
||||||
|
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_I2C_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_i2c.h"
|
||||||
|
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_I2S_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_i2s.h"
|
||||||
|
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_iwdg.h"
|
||||||
|
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_PWR_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_pwr.h"
|
||||||
|
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_RTC_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_rtc.h"
|
||||||
|
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_pccard.h"
|
||||||
|
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SD_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_sd.h"
|
||||||
|
#endif /* HAL_SD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_NAND_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_nand.h"
|
||||||
|
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_spi.h"
|
||||||
|
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_TIM_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_tim.h"
|
||||||
|
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_UART_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_uart.h"
|
||||||
|
#endif /* HAL_UART_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_USART_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_usart.h"
|
||||||
|
#endif /* HAL_USART_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_irda.h"
|
||||||
|
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_smartcard.h"
|
||||||
|
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_wwdg.h"
|
||||||
|
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_PCD_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_pcd.h"
|
||||||
|
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_HCD_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_hcd.h"
|
||||||
|
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_MMC_MODULE_ENABLED
|
||||||
|
#include "stm32f1xx_hal_mmc.h"
|
||||||
|
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
/**
|
||||||
|
* @brief The assert_param macro is used for function's parameters check.
|
||||||
|
* @param expr: If expr is false, it calls assert_failed function
|
||||||
|
* which reports the name of the source file and the source
|
||||||
|
* line number of the call that failed.
|
||||||
|
* If expr is true, it returns no value.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||||
|
/* Exported functions ------------------------------------------------------- */
|
||||||
|
void assert_failed(uint8_t* file, uint32_t line);
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif /* USE_FULL_ASSERT */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_CONF_H */
|
||||||
|
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,195 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_crc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of CRC HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_CRC_H
|
||||||
|
#define __STM32F1xx_HAL_CRC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CRC HAL State Structure definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||||
|
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||||
|
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||||
|
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||||
|
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||||
|
|
||||||
|
}HAL_CRC_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CRC handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
CRC_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< CRC locking object */
|
||||||
|
|
||||||
|
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||||
|
|
||||||
|
}CRC_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset CRC handle state
|
||||||
|
* @param __HANDLE__: CRC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Resets CRC Data Register.
|
||||||
|
* @param __HANDLE__: CRC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_CRC_DR_RESET(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||||
|
* @param __HANDLE__: CRC handle
|
||||||
|
* @param __VALUE__: 8-bit value to be stored in the ID register
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
|
||||||
|
* @param __HANDLE__: CRC handle
|
||||||
|
* @retval 8-bit value of the ID register
|
||||||
|
*/
|
||||||
|
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||||
|
HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
|
||||||
|
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||||
|
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Peripheral Control functions ************************************************/
|
||||||
|
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||||
|
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC_Exported_Functions_Group3
|
||||||
|
** @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Peripheral State functions **************************************************/
|
||||||
|
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_CRC_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,324 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_dac.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of DAC HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_DAC_H
|
||||||
|
#define __STM32F1xx_HAL_DAC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
|
||||||
|
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
|
||||||
|
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||||
|
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||||
|
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||||
|
|
||||||
|
}HAL_DAC_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DAC handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
DAC_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||||
|
|
||||||
|
}DAC_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DAC Configuration regular Channel structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||||
|
This parameter can be a value of @ref DACEx_trigger_selection
|
||||||
|
Note: For STM32F100x high-density value line devices, additional trigger sources are available. */
|
||||||
|
|
||||||
|
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref DAC_output_buffer */
|
||||||
|
|
||||||
|
}DAC_ChannelConfTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Error_Code DAC Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_DAC_ERROR_NONE 0x00000000U /*!< No error */
|
||||||
|
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x00000001U /*!< DAC channel1 DMA underrun error */
|
||||||
|
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x00000002U /*!< DAC channel2 DMA underrun error */
|
||||||
|
#define HAL_DAC_ERROR_DMA 0x00000004U /*!< DMA error */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_output_buffer DAC output buffer
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
|
||||||
|
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Channel_selection DAC Channel selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DAC_CHANNEL_1 0x00000000U
|
||||||
|
#define DAC_CHANNEL_2 0x00000010U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_data_alignement DAC data alignement
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DAC_ALIGN_12B_R 0x00000000U
|
||||||
|
#define DAC_ALIGN_12B_L 0x00000004U
|
||||||
|
#define DAC_ALIGN_8B_R 0x00000008U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset DAC handle state
|
||||||
|
* @param __HANDLE__: specifies the DAC handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||||
|
|
||||||
|
/** @brief Enable the DAC channel
|
||||||
|
* @param __HANDLE__: specifies the DAC handle.
|
||||||
|
* @param __DAC_Channel__: specifies the DAC channel
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||||
|
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
|
||||||
|
|
||||||
|
/** @brief Disable the DAC channel
|
||||||
|
* @param __HANDLE__: specifies the DAC handle
|
||||||
|
* @param __DAC_Channel__: specifies the DAC channel.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||||
|
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||||
|
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||||
|
|
||||||
|
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||||
|
((CHANNEL) == DAC_CHANNEL_2))
|
||||||
|
|
||||||
|
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||||
|
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||||
|
((ALIGN) == DAC_ALIGN_8B_R))
|
||||||
|
|
||||||
|
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
|
||||||
|
|
||||||
|
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
|
||||||
|
|
||||||
|
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
|
||||||
|
|
||||||
|
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Include DAC HAL Extension module */
|
||||||
|
#include "stm32f1xx_hal_dac_ex.h"
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization and de-initialization functions *****************************/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
|
||||||
|
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
|
||||||
|
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
|
||||||
|
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* IO operation functions *****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||||
|
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||||
|
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral Control functions ***********************************************/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_Exported_Functions_Group4
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral State functions *************************************************/
|
||||||
|
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
|
||||||
|
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||||
|
|
||||||
|
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||||
|
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
|
||||||
|
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_Private_Functions DAC Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||||
|
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||||
|
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /*__STM32F1xx_HAL_DAC_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
@ -0,0 +1,372 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_dac_ex.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of DAC HAL Extension module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_DAC_EX_H
|
||||||
|
#define __STM32F1xx_HAL_DAC_EX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DACEx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
|
||||||
|
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DACEx_trigger_selection DAC trigger selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||||
|
has been loaded, and not by external trigger */
|
||||||
|
#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
|
||||||
|
|
||||||
|
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
/* For STM32F10x high-density and XL-density devices: TIM8 */
|
||||||
|
#define DAC_TRIGGER_T8_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
/* For STM32F10x connectivity line devices and STM32F100x devices: TIM3 */
|
||||||
|
#define DAC_TRIGGER_T3_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#endif /* STM32F100xB || STM32F100xE || STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
/* Availability of trigger from TIM5 and TIM15: */
|
||||||
|
/* - For STM32F10x value line devices STM32F100xB: */
|
||||||
|
/* trigger from TIM15 is available, TIM5 not available. */
|
||||||
|
/* - For STM32F10x value line devices STM32F100xE: */
|
||||||
|
/* trigger from TIM15 and TIM5 are both available, */
|
||||||
|
/* selection depends on remap (with TIM5 as default configuration). */
|
||||||
|
/* - Other STM32F1 devices: */
|
||||||
|
/* trigger from TIM5 is available, TIM15 not available. */
|
||||||
|
#if defined (STM32F100xB)
|
||||||
|
#define DAC_TRIGGER_T15_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#else
|
||||||
|
|
||||||
|
#define DAC_TRIGGER_T5_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
|
||||||
|
#if defined (STM32F100xE)
|
||||||
|
/*!< DAC trigger availability depending on STM32F1 devices:
|
||||||
|
For STM32F100x high-density value line devices, the TIM15 TRGO event can be selected
|
||||||
|
as replacement of TIM5 TRGO if the MISC_REMAP bit in the AFIO_MAPR2 register is set.
|
||||||
|
Refer to macro "__HAL_AFIO_REMAP_MISC_ENABLE()/__HAL_AFIO_REMAP_MISC_DISABLE()".
|
||||||
|
Otherwise, TIM5 TRGO is used and TIM15 TRGO is not used (default case).
|
||||||
|
For more details please refer to the AFIO section. */
|
||||||
|
#define DAC_TRIGGER_T15_TRGO DAC_TRIGGER_T5_TRGO
|
||||||
|
#endif /* STM32F100xE */
|
||||||
|
|
||||||
|
#endif /* STM32F100xB */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE)
|
||||||
|
/** @defgroup DAC_flags_definition DAC flags definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||||
|
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_IT_definition DAC IT definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
|
||||||
|
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F100xB || STM32F100xE */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE)
|
||||||
|
/** @defgroup DACEx_Exported_Macros DACEx Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Enable the DAC interrupt
|
||||||
|
* @param __HANDLE__: specifies the DAC handle
|
||||||
|
* @param __INTERRUPT__: specifies the DAC interrupt.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||||
|
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||||
|
|
||||||
|
/** @brief Disable the DAC interrupt
|
||||||
|
* @param __HANDLE__: specifies the DAC handle
|
||||||
|
* @param __INTERRUPT__: specifies the DAC interrupt.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||||
|
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||||
|
|
||||||
|
/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
|
||||||
|
* @param __HANDLE__: DAC handle
|
||||||
|
* @param __INTERRUPT__: DAC interrupt source to check
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
|
||||||
|
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
|
||||||
|
* @retval State of interruption (SET or RESET)
|
||||||
|
*/
|
||||||
|
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||||
|
|
||||||
|
/** @brief Get the selected DAC's flag status.
|
||||||
|
* @param __HANDLE__: specifies the DAC handle.
|
||||||
|
* @param __FLAG__: specifies the DAC flag to get.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
|
||||||
|
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clear the DAC's flag.
|
||||||
|
* @param __HANDLE__: specifies the DAC handle.
|
||||||
|
* @param __FLAG__: specifies the DAC flag to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
|
||||||
|
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F100xB || STM32F100xE */
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup DACEx_Private_Macros DACEx Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||||
|
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
|
||||||
|
#if defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||||
|
#endif /* STM32F100xE || STM32F105xC || STM32F107xC */
|
||||||
|
#if defined (STM32F100xB)
|
||||||
|
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||||
|
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||||
|
#endif /* STM32F100xB */
|
||||||
|
|
||||||
|
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||||
|
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup DACEx_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DACEx_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Extension features functions ***********************************************/
|
||||||
|
|
||||||
|
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
|
||||||
|
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||||
|
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
|
||||||
|
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||||
|
|
||||||
|
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||||
|
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||||
|
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE)
|
||||||
|
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
|
||||||
|
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||||
|
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
|
||||||
|
#endif /* STM32F100xB) || defined (STM32F100xE) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DACEx_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||||
|
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||||
|
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__STM32F1xx_HAL_DAC_EX_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
2113
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_eth.h
Normal file
2113
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_eth.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,254 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_hcd.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of HCD HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_HCD_H
|
||||||
|
#define __STM32F1xx_HAL_HCD_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_usb.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup HCD
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup HCD_Exported_Types HCD Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HCD Status structure definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_HCD_STATE_RESET = 0x00U,
|
||||||
|
HAL_HCD_STATE_READY = 0x01U,
|
||||||
|
HAL_HCD_STATE_ERROR = 0x02U,
|
||||||
|
HAL_HCD_STATE_BUSY = 0x03U,
|
||||||
|
HAL_HCD_STATE_TIMEOUT = 0x04U
|
||||||
|
} HCD_StateTypeDef;
|
||||||
|
|
||||||
|
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
|
||||||
|
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
|
||||||
|
typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
|
||||||
|
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
|
||||||
|
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HCD Handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
HCD_TypeDef *Instance; /*!< Register base address */
|
||||||
|
HCD_InitTypeDef Init; /*!< HCD required parameters */
|
||||||
|
HCD_HCTypeDef hc[15U]; /*!< Host channels parameters */
|
||||||
|
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
|
||||||
|
__IO HCD_StateTypeDef State; /*!< HCD communication state */
|
||||||
|
void *pData; /*!< Pointer Stack Handler */
|
||||||
|
} HCD_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup HCD_Exported_Constants HCD Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup HCD_Speed HCD Speed
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HCD_SPEED_LOW 2U
|
||||||
|
#define HCD_SPEED_FULL 3U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup HCD_Exported_Macros HCD Exported Macros
|
||||||
|
* @brief macros to handle interrupts and specific clock configurations
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||||
|
#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
|
||||||
|
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||||
|
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
|
||||||
|
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||||
|
|
||||||
|
|
||||||
|
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
|
||||||
|
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
|
||||||
|
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
|
||||||
|
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
|
||||||
|
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Initialization/de-initialization functions ********************************/
|
||||||
|
/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
|
||||||
|
HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
|
||||||
|
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
|
||||||
|
uint8_t ch_num,
|
||||||
|
uint8_t epnum,
|
||||||
|
uint8_t dev_address,
|
||||||
|
uint8_t speed,
|
||||||
|
uint8_t ep_type,
|
||||||
|
uint16_t mps);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
|
||||||
|
uint8_t ch_num);
|
||||||
|
|
||||||
|
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
|
||||||
|
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* I/O operation functions ***************************************************/
|
||||||
|
/** @addtogroup HCD_Exported_Functions_Group2 IO operation functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
|
||||||
|
uint8_t pipe,
|
||||||
|
uint8_t direction,
|
||||||
|
uint8_t ep_type,
|
||||||
|
uint8_t token,
|
||||||
|
uint8_t* pbuff,
|
||||||
|
uint16_t length,
|
||||||
|
uint8_t do_ping);
|
||||||
|
|
||||||
|
/* Non-Blocking mode: Interrupt */
|
||||||
|
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
|
||||||
|
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
|
||||||
|
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
|
||||||
|
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
|
||||||
|
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
|
||||||
|
uint8_t chnum,
|
||||||
|
HCD_URBStateTypeDef urb_state);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Peripheral Control functions **********************************************/
|
||||||
|
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
|
||||||
|
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
|
||||||
|
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Peripheral State functions ************************************************/
|
||||||
|
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
|
||||||
|
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||||
|
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||||
|
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
|
||||||
|
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
|
||||||
|
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup HCD_Private_Macros HCD Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup HCD_Instance_definition HCD Instance definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_HCD_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,648 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_i2c.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of I2C HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_I2C_H
|
||||||
|
#define __STM32F1xx_HAL_I2C_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2C
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief I2C Configuration Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t ClockSpeed; /*!< Specifies the clock frequency.
|
||||||
|
This parameter must be set to a value lower than 400kHz */
|
||||||
|
|
||||||
|
uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||||
|
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||||
|
|
||||||
|
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||||
|
This parameter can be a 7-bit or 10-bit address. */
|
||||||
|
|
||||||
|
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||||
|
This parameter can be a value of @ref I2C_addressing_mode */
|
||||||
|
|
||||||
|
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||||
|
This parameter can be a value of @ref I2C_dual_addressing_mode */
|
||||||
|
|
||||||
|
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||||
|
This parameter can be a 7-bit address. */
|
||||||
|
|
||||||
|
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||||
|
This parameter can be a value of @ref I2C_general_call_addressing_mode */
|
||||||
|
|
||||||
|
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||||
|
This parameter can be a value of @ref I2C_nostretch_mode */
|
||||||
|
|
||||||
|
}I2C_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL State structure definition
|
||||||
|
* @note HAL I2C State value coding follow below described bitmap :
|
||||||
|
* b7-b6 Error information
|
||||||
|
* 00 : No Error
|
||||||
|
* 01 : Abort (Abort user request on going)
|
||||||
|
* 10 : Timeout
|
||||||
|
* 11 : Error
|
||||||
|
* b5 IP initilisation status
|
||||||
|
* 0 : Reset (IP not initialized)
|
||||||
|
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
|
||||||
|
* b4 (not used)
|
||||||
|
* x : Should be set to 0
|
||||||
|
* b3
|
||||||
|
* 0 : Ready or Busy (No Listen mode ongoing)
|
||||||
|
* 1 : Listen (IP in Address Listen Mode)
|
||||||
|
* b2 Intrinsic process state
|
||||||
|
* 0 : Ready
|
||||||
|
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||||
|
* b1 Rx state
|
||||||
|
* 0 : Ready (no Rx operation ongoing)
|
||||||
|
* 1 : Busy (Rx operation ongoing)
|
||||||
|
* b0 Tx state
|
||||||
|
* 0 : Ready (no Tx operation ongoing)
|
||||||
|
* 1 : Busy (Tx operation ongoing)
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||||
|
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||||
|
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||||
|
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||||
|
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||||
|
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||||
|
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||||
|
process is ongoing */
|
||||||
|
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||||
|
process is ongoing */
|
||||||
|
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||||
|
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||||
|
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||||
|
|
||||||
|
}HAL_I2C_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL Mode structure definition
|
||||||
|
* @note HAL I2C Mode value coding follow below described bitmap :
|
||||||
|
* b7 (not used)
|
||||||
|
* x : Should be set to 0
|
||||||
|
* b6
|
||||||
|
* 0 : None
|
||||||
|
* 1 : Memory (HAL I2C communication is in Memory Mode)
|
||||||
|
* b5
|
||||||
|
* 0 : None
|
||||||
|
* 1 : Slave (HAL I2C communication is in Slave Mode)
|
||||||
|
* b4
|
||||||
|
* 0 : None
|
||||||
|
* 1 : Master (HAL I2C communication is in Master Mode)
|
||||||
|
* b3-b2-b1-b0 (not used)
|
||||||
|
* xxxx : Should be set to 0000
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||||
|
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||||
|
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||||
|
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||||
|
|
||||||
|
}HAL_I2C_ModeTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief I2C handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||||
|
|
||||||
|
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||||
|
|
||||||
|
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||||
|
|
||||||
|
uint16_t XferSize; /*!< I2C transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||||
|
|
||||||
|
__IO uint32_t XferOptions; /*!< I2C transfer options */
|
||||||
|
|
||||||
|
__IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
|
||||||
|
context for internal usage */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||||
|
|
||||||
|
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||||
|
|
||||||
|
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||||
|
|
||||||
|
__IO uint32_t Devaddress; /*!< I2C Target device address */
|
||||||
|
|
||||||
|
__IO uint32_t Memaddress; /*!< I2C Target memory address */
|
||||||
|
|
||||||
|
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */
|
||||||
|
|
||||||
|
__IO uint32_t EventCount; /*!< I2C Event counter */
|
||||||
|
|
||||||
|
}I2C_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_Error_Code I2C Error Code
|
||||||
|
* @brief I2C Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
|
||||||
|
#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
|
||||||
|
#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
|
||||||
|
#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
|
||||||
|
#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
|
||||||
|
#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||||
|
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_DUTYCYCLE_2 0x00000000U
|
||||||
|
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_addressing_mode I2C addressing mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
|
||||||
|
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_DUALADDRESS_DISABLE 0x00000000U
|
||||||
|
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_GENERALCALL_DISABLE 0x00000000U
|
||||||
|
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_nostretch_mode I2C nostretch mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_NOSTRETCH_DISABLE 0x00000000U
|
||||||
|
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_MEMADD_SIZE_8BIT 0x00000001U
|
||||||
|
#define I2C_MEMADD_SIZE_16BIT 0x00000010U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_DIRECTION_RECEIVE 0x00000000U
|
||||||
|
#define I2C_DIRECTION_TRANSMIT 0x00000001U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_FIRST_FRAME 0x00000001U
|
||||||
|
#define I2C_NEXT_FRAME 0x00000002U
|
||||||
|
#define I2C_FIRST_AND_LAST_FRAME 0x00000004U
|
||||||
|
#define I2C_LAST_FRAME 0x00000008U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_IT_BUF I2C_CR2_ITBUFEN
|
||||||
|
#define I2C_IT_EVT I2C_CR2_ITEVTEN
|
||||||
|
#define I2C_IT_ERR I2C_CR2_ITERREN
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_FLAG_SMBALERT 0x00018000U
|
||||||
|
#define I2C_FLAG_TIMEOUT 0x00014000U
|
||||||
|
#define I2C_FLAG_PECERR 0x00011000U
|
||||||
|
#define I2C_FLAG_OVR 0x00010800U
|
||||||
|
#define I2C_FLAG_AF 0x00010400U
|
||||||
|
#define I2C_FLAG_ARLO 0x00010200U
|
||||||
|
#define I2C_FLAG_BERR 0x00010100U
|
||||||
|
#define I2C_FLAG_TXE 0x00010080U
|
||||||
|
#define I2C_FLAG_RXNE 0x00010040U
|
||||||
|
#define I2C_FLAG_STOPF 0x00010010U
|
||||||
|
#define I2C_FLAG_ADD10 0x00010008U
|
||||||
|
#define I2C_FLAG_BTF 0x00010004U
|
||||||
|
#define I2C_FLAG_ADDR 0x00010002U
|
||||||
|
#define I2C_FLAG_SB 0x00010001U
|
||||||
|
#define I2C_FLAG_DUALF 0x00100080U
|
||||||
|
#define I2C_FLAG_SMBHOST 0x00100040U
|
||||||
|
#define I2C_FLAG_SMBDEFAULT 0x00100020U
|
||||||
|
#define I2C_FLAG_GENCALL 0x00100010U
|
||||||
|
#define I2C_FLAG_TRA 0x00100004U
|
||||||
|
#define I2C_FLAG_BUSY 0x00100002U
|
||||||
|
#define I2C_FLAG_MSL 0x00100001U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset I2C handle state
|
||||||
|
* @param __HANDLE__: specifies the I2C Handle.
|
||||||
|
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||||
|
|
||||||
|
/** @brief Enable or disable the specified I2C interrupts.
|
||||||
|
* @param __HANDLE__: specifies the I2C Handle.
|
||||||
|
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||||
|
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg I2C_IT_BUF: Buffer interrupt enable
|
||||||
|
* @arg I2C_IT_EVT: Event interrupt enable
|
||||||
|
* @arg I2C_IT_ERR: Error interrupt enable
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||||
|
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
|
||||||
|
|
||||||
|
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
|
||||||
|
* @param __HANDLE__: specifies the I2C Handle.
|
||||||
|
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||||
|
* @param __INTERRUPT__: specifies the I2C interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg I2C_IT_BUF: Buffer interrupt enable
|
||||||
|
* @arg I2C_IT_EVT: Event interrupt enable
|
||||||
|
* @arg I2C_IT_ERR: Error interrupt enable
|
||||||
|
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||||
|
|
||||||
|
/** @brief Checks whether the specified I2C flag is set or not.
|
||||||
|
* @param __HANDLE__: specifies the I2C Handle.
|
||||||
|
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg I2C_FLAG_SMBALERT: SMBus Alert flag
|
||||||
|
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
|
||||||
|
* @arg I2C_FLAG_PECERR: PEC error in reception flag
|
||||||
|
* @arg I2C_FLAG_OVR: Overrun/Underrun flag
|
||||||
|
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||||
|
* @arg I2C_FLAG_ARLO: Arbitration lost flag
|
||||||
|
* @arg I2C_FLAG_BERR: Bus error flag
|
||||||
|
* @arg I2C_FLAG_TXE: Data register empty flag
|
||||||
|
* @arg I2C_FLAG_RXNE: Data register not empty flag
|
||||||
|
* @arg I2C_FLAG_STOPF: Stop detection flag
|
||||||
|
* @arg I2C_FLAG_ADD10: 10-bit header sent flag
|
||||||
|
* @arg I2C_FLAG_BTF: Byte transfer finished flag
|
||||||
|
* @arg I2C_FLAG_ADDR: Address sent flag
|
||||||
|
* Address matched flag
|
||||||
|
* @arg I2C_FLAG_SB: Start bit flag
|
||||||
|
* @arg I2C_FLAG_DUALF: Dual flag
|
||||||
|
* @arg I2C_FLAG_SMBHOST: SMBus host header
|
||||||
|
* @arg I2C_FLAG_SMBDEFAULT: SMBus default header
|
||||||
|
* @arg I2C_FLAG_GENCALL: General call header flag
|
||||||
|
* @arg I2C_FLAG_TRA: Transmitter/Receiver flag
|
||||||
|
* @arg I2C_FLAG_BUSY: Bus busy flag
|
||||||
|
* @arg I2C_FLAG_MSL: Master/Slave flag
|
||||||
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
|
||||||
|
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
|
||||||
|
|
||||||
|
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
|
||||||
|
* @param __HANDLE__: specifies the I2C Handle.
|
||||||
|
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||||
|
* @param __FLAG__: specifies the flag to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg I2C_FLAG_SMBALERT: SMBus Alert flag
|
||||||
|
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
|
||||||
|
* @arg I2C_FLAG_PECERR: PEC error in reception flag
|
||||||
|
* @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
|
||||||
|
* @arg I2C_FLAG_AF: Acknowledge failure flag
|
||||||
|
* @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
|
||||||
|
* @arg I2C_FLAG_BERR: Bus error flag
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
|
||||||
|
|
||||||
|
/** @brief Clears the I2C ADDR pending flag.
|
||||||
|
* @param __HANDLE__: specifies the I2C Handle.
|
||||||
|
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->SR1; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->SR2; \
|
||||||
|
UNUSED(tmpreg); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Clears the I2C STOPF pending flag.
|
||||||
|
* @param __HANDLE__: specifies the I2C Handle.
|
||||||
|
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->SR1; \
|
||||||
|
(__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
|
||||||
|
UNUSED(tmpreg); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Enable the I2C peripheral.
|
||||||
|
* @param __HANDLE__: specifies the I2C Handle.
|
||||||
|
* This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
|
||||||
|
|
||||||
|
/** @brief Disable the I2C peripheral.
|
||||||
|
* @param __HANDLE__: specifies the I2C Handle.
|
||||||
|
* This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup I2C_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2C_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2C_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* I/O operation functions *****************************************************/
|
||||||
|
/******* Blocking mode: Polling */
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||||
|
|
||||||
|
/******* Non-Blocking mode: Interrupt */
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||||
|
|
||||||
|
/******* Non-Blocking mode: DMA */
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||||
|
|
||||||
|
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||||
|
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||||
|
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||||
|
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2C_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral State, Mode and Errors functions *********************************/
|
||||||
|
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||||
|
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||||
|
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2C_FLAG_MASK 0x0000FFFFU
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup I2C_Private_Macros I2C Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
|
||||||
|
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
|
||||||
|
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
|
||||||
|
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
|
||||||
|
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
|
||||||
|
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
|
||||||
|
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
|
||||||
|
|
||||||
|
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
|
||||||
|
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
|
||||||
|
|
||||||
|
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||||
|
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
|
||||||
|
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
|
||||||
|
|
||||||
|
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
|
||||||
|
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||||
|
|
||||||
|
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
|
||||||
|
((CYCLE) == I2C_DUTYCYCLE_16_9))
|
||||||
|
#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||||
|
((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
|
||||||
|
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||||
|
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||||
|
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||||
|
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||||
|
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||||
|
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||||
|
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||||
|
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||||
|
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
|
||||||
|
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
|
||||||
|
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
|
||||||
|
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||||
|
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||||
|
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||||
|
((REQUEST) == I2C_LAST_FRAME))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_I2C_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,493 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_i2s.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of I2S HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_I2S_H
|
||||||
|
#define __STM32F1xx_HAL_I2S_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2S
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup I2S_Exported_Types I2S Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief I2S Init structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Mode; /*!< Specifies the I2S operating mode.
|
||||||
|
This parameter can be a value of @ref I2S_Mode */
|
||||||
|
|
||||||
|
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Standard */
|
||||||
|
|
||||||
|
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Data_Format */
|
||||||
|
|
||||||
|
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||||
|
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||||
|
|
||||||
|
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||||
|
|
||||||
|
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||||
|
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||||
|
}I2S_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
|
||||||
|
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
|
||||||
|
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
|
||||||
|
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||||
|
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||||
|
HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
|
||||||
|
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
|
||||||
|
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
|
||||||
|
|
||||||
|
}HAL_I2S_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief I2S handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct __I2S_HandleTypeDef
|
||||||
|
{
|
||||||
|
SPI_TypeDef *Instance; /*!< I2S registers base address */
|
||||||
|
|
||||||
|
I2S_InitTypeDef Init; /*!< I2S communication parameters */
|
||||||
|
|
||||||
|
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
|
||||||
|
|
||||||
|
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
|
||||||
|
|
||||||
|
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
|
||||||
|
|
||||||
|
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
|
||||||
|
(This field is initialized at the
|
||||||
|
same value as transfer size at the
|
||||||
|
beginning of the transfer and
|
||||||
|
decremented when a sample is received
|
||||||
|
NbSamplesReceived = RxBufferSize-RxBufferCount) */
|
||||||
|
|
||||||
|
void (*IrqHandlerISR) (struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
|
||||||
|
|
||||||
|
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
|
||||||
|
|
||||||
|
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< I2S Error code
|
||||||
|
This parameter can be a value of @ref I2S_ErrorCode */
|
||||||
|
|
||||||
|
}I2S_HandleTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup I2S_Exported_Constants I2S Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @defgroup I2S_ErrorCode I2S Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_I2S_ERROR_NONE 0x00000000U /*!< No error */
|
||||||
|
#define HAL_I2S_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
|
||||||
|
#define HAL_I2S_ERROR_OVR 0x00000002U /*!< OVR error */
|
||||||
|
#define HAL_I2S_ERROR_UDR 0x00000004U /*!< UDR error */
|
||||||
|
#define HAL_I2S_ERROR_DMA 0x00000008U /*!< DMA transfer error */
|
||||||
|
#define HAL_I2S_ERROR_PRESCALER 0x00000010U /*!< Prescaler Calculation error */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Mode I2S Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2S_MODE_SLAVE_TX 0x00000000U
|
||||||
|
#define I2S_MODE_SLAVE_RX ((uint32_t)SPI_I2SCFGR_I2SCFG_0)
|
||||||
|
#define I2S_MODE_MASTER_TX ((uint32_t)SPI_I2SCFGR_I2SCFG_1)
|
||||||
|
#define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Standard I2S Standard
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2S_STANDARD_PHILIPS 0x00000000U
|
||||||
|
#define I2S_STANDARD_MSB ((uint32_t)SPI_I2SCFGR_I2SSTD_0)
|
||||||
|
#define I2S_STANDARD_LSB ((uint32_t)SPI_I2SCFGR_I2SSTD_1)
|
||||||
|
#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
|
||||||
|
#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Data_Format I2S Data Format
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2S_DATAFORMAT_16B 0x00000000U
|
||||||
|
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)SPI_I2SCFGR_CHLEN)
|
||||||
|
#define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
|
||||||
|
#define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_MCLK_Output I2S Mclk Output
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
|
||||||
|
#define I2S_MCLKOUTPUT_DISABLE 0x00000000U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2S_AUDIOFREQ_192K 192000U
|
||||||
|
#define I2S_AUDIOFREQ_96K 96000U
|
||||||
|
#define I2S_AUDIOFREQ_48K 48000U
|
||||||
|
#define I2S_AUDIOFREQ_44K 44100U
|
||||||
|
#define I2S_AUDIOFREQ_32K 32000U
|
||||||
|
#define I2S_AUDIOFREQ_22K 22050U
|
||||||
|
#define I2S_AUDIOFREQ_16K 16000U
|
||||||
|
#define I2S_AUDIOFREQ_11K 11025U
|
||||||
|
#define I2S_AUDIOFREQ_8K 8000U
|
||||||
|
#define I2S_AUDIOFREQ_DEFAULT 2U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2S_CPOL_LOW 0x00000000U
|
||||||
|
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2S_IT_TXE SPI_CR2_TXEIE
|
||||||
|
#define I2S_IT_RXNE SPI_CR2_RXNEIE
|
||||||
|
#define I2S_IT_ERR SPI_CR2_ERRIE
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Flags_Definition I2S Flags Definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define I2S_FLAG_TXE SPI_SR_TXE
|
||||||
|
#define I2S_FLAG_RXNE SPI_SR_RXNE
|
||||||
|
|
||||||
|
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||||
|
#define I2S_FLAG_OVR SPI_SR_OVR
|
||||||
|
#define I2S_FLAG_FRE SPI_SR_FRE
|
||||||
|
|
||||||
|
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||||
|
#define I2S_FLAG_BSY SPI_SR_BSY
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup I2S_Exported_Macros I2S Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset I2S handle state
|
||||||
|
* @param __HANDLE__: specifies the I2S Handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
|
||||||
|
|
||||||
|
/** @brief Enable the specified SPI peripheral (in I2S mode).
|
||||||
|
* @param __HANDLE__: specifies the I2S Handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
||||||
|
|
||||||
|
/** @brief Disable the specified SPI peripheral (in I2S mode).
|
||||||
|
* @param __HANDLE__: specifies the I2S Handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
|
||||||
|
|
||||||
|
/** @brief Enable the specified I2S interrupts.
|
||||||
|
* @param __HANDLE__: specifies the I2S Handle.
|
||||||
|
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||||
|
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||||
|
* @arg I2S_IT_ERR: Error interrupt enable
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
||||||
|
|
||||||
|
/** @brief Disable the specified I2S interrupts.
|
||||||
|
* @param __HANDLE__: specifies the I2S Handle.
|
||||||
|
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||||
|
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||||
|
* @arg I2S_IT_ERR: Error interrupt enable
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
|
||||||
|
|
||||||
|
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
|
||||||
|
* @param __HANDLE__: specifies the I2S Handle.
|
||||||
|
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
|
||||||
|
* @param __INTERRUPT__: specifies the I2S interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
|
||||||
|
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
|
||||||
|
* @arg I2S_IT_ERR: Error interrupt enable
|
||||||
|
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||||
|
|
||||||
|
/** @brief Checks whether the specified I2S flag is set or not.
|
||||||
|
* @param __HANDLE__: specifies the I2S Handle.
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
|
||||||
|
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
|
||||||
|
* @arg I2S_FLAG_UDR: Underrun flag
|
||||||
|
* @arg I2S_FLAG_OVR: Overrun flag
|
||||||
|
* @arg I2S_FLAG_FRE: Frame error flag
|
||||||
|
* @arg I2S_FLAG_CHSIDE: Channel Side flag
|
||||||
|
* @arg I2S_FLAG_BSY: Busy flag
|
||||||
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clears the I2S OVR pending flag.
|
||||||
|
* @param __HANDLE__: specifies the I2S Handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||||
|
UNUSED(tmpreg); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Clears the I2S UDR pending flag.
|
||||||
|
* @param __HANDLE__: specifies the I2S Handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||||
|
UNUSED(tmpreg); \
|
||||||
|
} while(0U)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup I2S_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2S_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/de-initialization functions ********************************/
|
||||||
|
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
|
||||||
|
HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
|
||||||
|
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
|
||||||
|
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2S_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* I/O operation functions ***************************************************/
|
||||||
|
/* Blocking mode: Polling */
|
||||||
|
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
|
||||||
|
/* Non-Blocking mode: Interrupt */
|
||||||
|
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||||
|
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
|
||||||
|
|
||||||
|
/* Non-Blocking mode: DMA */
|
||||||
|
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
|
||||||
|
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
|
||||||
|
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
|
||||||
|
|
||||||
|
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
|
||||||
|
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||||
|
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||||
|
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||||
|
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
|
||||||
|
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2S_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral Control and State functions ************************************/
|
||||||
|
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
|
||||||
|
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup I2S_Private_Constants I2S Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
|
||||||
|
((MODE) == I2S_MODE_SLAVE_RX) || \
|
||||||
|
((MODE) == I2S_MODE_MASTER_TX) || \
|
||||||
|
((MODE) == I2S_MODE_MASTER_RX))
|
||||||
|
|
||||||
|
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
|
||||||
|
((STANDARD) == I2S_STANDARD_MSB) || \
|
||||||
|
((STANDARD) == I2S_STANDARD_LSB) || \
|
||||||
|
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
|
||||||
|
((STANDARD) == I2S_STANDARD_PCM_LONG))
|
||||||
|
|
||||||
|
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
|
||||||
|
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
|
||||||
|
((FORMAT) == I2S_DATAFORMAT_24B) || \
|
||||||
|
((FORMAT) == I2S_DATAFORMAT_32B))
|
||||||
|
|
||||||
|
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||||
|
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
|
||||||
|
|
||||||
|
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
|
||||||
|
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
|
||||||
|
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
|
||||||
|
|
||||||
|
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
|
||||||
|
((CPOL) == I2S_CPOL_HIGH))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private Fonctions ---------------------------------------------------------*/
|
||||||
|
/** @defgroup I2S_Private_Functions I2S Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Private functions are defined in stm32f1xx_hal_i2s.c file */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_I2S_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,599 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_irda.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of IRDA HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_IRDA_H
|
||||||
|
#define __STM32F1xx_HAL_IRDA_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup IRDA
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief IRDA Init Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||||
|
The baud rate is computed using the following formula:
|
||||||
|
- IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate)))
|
||||||
|
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||||
|
|
||||||
|
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||||
|
This parameter can be a value of @ref IRDA_Word_Length */
|
||||||
|
|
||||||
|
|
||||||
|
uint32_t Parity; /*!< Specifies the parity mode.
|
||||||
|
This parameter can be a value of @ref IRDA_Parity
|
||||||
|
@note When parity is enabled, the computed parity is inserted
|
||||||
|
at the MSB position of the transmitted data (9th bit when
|
||||||
|
the word length is set to 9 data bits; 8th bit when the
|
||||||
|
word length is set to 8 data bits). */
|
||||||
|
|
||||||
|
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref IRDA_Transfer_Mode */
|
||||||
|
|
||||||
|
uint8_t Prescaler; /*!< Specifies the Prescaler value prescaler value to be programmed
|
||||||
|
in the IrDA low-power Baud Register, for defining pulse width on which
|
||||||
|
burst acceptance/rejection will be decided. This value is used as divisor
|
||||||
|
of system clock to achieve required pulse width. */
|
||||||
|
|
||||||
|
uint32_t IrDAMode; /*!< Specifies the IrDA mode
|
||||||
|
This parameter can be a value of @ref IRDA_Low_Power */
|
||||||
|
}IRDA_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL IRDA State structures definition
|
||||||
|
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
|
||||||
|
* - gState contains IRDA state information related to global Handle management
|
||||||
|
* and also information related to Tx operations.
|
||||||
|
* gState value coding follow below described bitmap :
|
||||||
|
* b7-b6 Error information
|
||||||
|
* 00 : No Error
|
||||||
|
* 01 : (Not Used)
|
||||||
|
* 10 : Timeout
|
||||||
|
* 11 : Error
|
||||||
|
* b5 IP initilisation status
|
||||||
|
* 0 : Reset (IP not initialized)
|
||||||
|
* 1 : Init done (IP not initialized. HAL IRDA Init function already called)
|
||||||
|
* b4-b3 (not used)
|
||||||
|
* xx : Should be set to 00
|
||||||
|
* b2 Intrinsic process state
|
||||||
|
* 0 : Ready
|
||||||
|
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||||
|
* b1 (not used)
|
||||||
|
* x : Should be set to 0
|
||||||
|
* b0 Tx state
|
||||||
|
* 0 : Ready (no Tx operation ongoing)
|
||||||
|
* 1 : Busy (Tx operation ongoing)
|
||||||
|
* - RxState contains information related to Rx operations.
|
||||||
|
* RxState value coding follow below described bitmap :
|
||||||
|
* b7-b6 (not used)
|
||||||
|
* xx : Should be set to 00
|
||||||
|
* b5 IP initilisation status
|
||||||
|
* 0 : Reset (IP not initialized)
|
||||||
|
* 1 : Init done (IP not initialized)
|
||||||
|
* b4-b2 (not used)
|
||||||
|
* xxx : Should be set to 000
|
||||||
|
* b1 Rx state
|
||||||
|
* 0 : Ready (no Rx operation ongoing)
|
||||||
|
* 1 : Busy (Rx operation ongoing)
|
||||||
|
* b0 (not used)
|
||||||
|
* x : Should be set to 0.
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||||
|
Value is allowed for gState and RxState */
|
||||||
|
HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||||
|
Value is allowed for gState and RxState */
|
||||||
|
HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
|
||||||
|
Value is allowed for gState only */
|
||||||
|
HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||||
|
Value is allowed for gState only */
|
||||||
|
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||||
|
Value is allowed for RxState only */
|
||||||
|
HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||||
|
Not to be used for neither gState nor RxState.
|
||||||
|
Value is result of combination (Or) between gState and RxState values */
|
||||||
|
HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||||
|
Value is allowed for gState only */
|
||||||
|
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
|
||||||
|
Value is allowed for gState only */
|
||||||
|
}HAL_IRDA_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief IRDA handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||||
|
|
||||||
|
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
|
||||||
|
|
||||||
|
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
|
||||||
|
|
||||||
|
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
|
||||||
|
|
||||||
|
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
|
||||||
|
|
||||||
|
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||||
|
|
||||||
|
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
|
||||||
|
and also related to Tx operations.
|
||||||
|
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||||
|
|
||||||
|
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
|
||||||
|
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< IRDA Error code */
|
||||||
|
}IRDA_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup IRDA_Exported_Constants IRDA Exported constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup IRDA_Error_Code IRDA Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
|
||||||
|
#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
|
||||||
|
#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
|
||||||
|
#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
|
||||||
|
#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
|
||||||
|
#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IRDA_Word_Length IRDA Word Length
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IRDA_WORDLENGTH_8B 0x00000000U
|
||||||
|
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IRDA_Parity IRDA Parity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IRDA_PARITY_NONE 0x00000000U
|
||||||
|
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||||
|
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||||
|
#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||||
|
#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
|
||||||
|
#define IRDA_POWERMODE_NORMAL 0x00000000U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IRDA_Flags IRDA Flags
|
||||||
|
* Elements values convention: 0xXXXX
|
||||||
|
* - 0xXXXX : Flag mask in the SR register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)
|
||||||
|
#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC)
|
||||||
|
#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
|
||||||
|
#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
|
||||||
|
#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)
|
||||||
|
#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE)
|
||||||
|
#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE)
|
||||||
|
#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
|
||||||
|
* Elements values convention: 0xY000XXXX
|
||||||
|
* - XXXX : Interrupt mask in the XX register
|
||||||
|
* - Y : Interrupt source register (2bits)
|
||||||
|
* - 01: CR1 register
|
||||||
|
* - 10: CR2 register
|
||||||
|
* - 11: CR3 register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
|
||||||
|
#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
|
||||||
|
#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
|
||||||
|
#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
|
||||||
|
#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
|
||||||
|
|
||||||
|
#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
|
||||||
|
|
||||||
|
#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
|
||||||
|
#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset IRDA handle gstate & RxState
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||||
|
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||||
|
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Flush the IRDA DR register
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
|
||||||
|
|
||||||
|
/** @brief Check whether the specified IRDA flag is set or not.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg IRDA_FLAG_TXE: Transmit data register empty flag
|
||||||
|
* @arg IRDA_FLAG_TC: Transmission Complete flag
|
||||||
|
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag
|
||||||
|
* @arg IRDA_FLAG_IDLE: Idle Line detection flag
|
||||||
|
* @arg IRDA_FLAG_ORE: OverRun Error flag
|
||||||
|
* @arg IRDA_FLAG_NE: Noise Error flag
|
||||||
|
* @arg IRDA_FLAG_FE: Framing Error flag
|
||||||
|
* @arg IRDA_FLAG_PE: Parity Error flag
|
||||||
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clear the specified IRDA pending flag.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg IRDA_FLAG_TC: Transmission Complete flag.
|
||||||
|
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
|
||||||
|
*
|
||||||
|
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||||
|
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||||
|
* sequence: a read operation to USART_SR register followed by a read
|
||||||
|
* operation to USART_DR register.
|
||||||
|
* @note RXNE flag can be also cleared by a read to the USART_DR register.
|
||||||
|
* @note TC flag can be also cleared by software sequence: a read operation to
|
||||||
|
* USART_SR register followed by a write operation to USART_DR register.
|
||||||
|
* @note TXE flag is cleared only by a write to the USART_DR register.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clear the IRDA PE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||||
|
UNUSED(tmpreg); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Clear the IRDA FE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Clear the IRDA NE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Clear the IRDA ORE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Clear the IRDA IDLE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Enable the specified IRDA interrupt.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
* @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||||
|
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||||
|
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||||
|
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||||
|
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||||
|
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||||
|
(((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||||
|
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
|
||||||
|
/** @brief Disable the specified IRDA interrupt.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
* @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||||
|
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||||
|
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||||
|
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||||
|
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||||
|
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||||
|
(((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
|
||||||
|
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
|
||||||
|
|
||||||
|
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
* @param __IT__: specifies the IRDA interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
|
||||||
|
* @arg IRDA_IT_TC: Transmission complete interrupt
|
||||||
|
* @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
|
||||||
|
* @arg IRDA_IT_IDLE: Idle line detection interrupt
|
||||||
|
* @arg IRDA_IT_ERR: Error interrupt
|
||||||
|
* @arg IRDA_IT_PE: Parity Error interrupt
|
||||||
|
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
|
||||||
|
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
|
||||||
|
|
||||||
|
/** @brief Enable UART/USART associated to IRDA Handle
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
|
||||||
|
|
||||||
|
/** @brief Disable UART/USART associated to IRDA Handle
|
||||||
|
* @param __HANDLE__: specifies the IRDA Handle.
|
||||||
|
* IRDA Handle selects the USARTx or UARTy peripheral
|
||||||
|
* (USART,UART availability and x,y values depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup IRDA_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup IRDA_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup IRDA_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* IO operation functions *******************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
||||||
|
/* Transfer Abort functions */
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
|
||||||
|
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
|
||||||
|
|
||||||
|
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||||
|
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup IRDA_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral State functions **************************************************/
|
||||||
|
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
|
||||||
|
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup IRDA_Private_Constants IRDA Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief IRDA interruptions flag mask
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define IRDA_IT_MASK 0x0000FFFFU
|
||||||
|
|
||||||
|
#define IRDA_CR1_REG_INDEX 1U
|
||||||
|
#define IRDA_CR2_REG_INDEX 2U
|
||||||
|
#define IRDA_CR3_REG_INDEX 3U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros --------------------------------------------------------*/
|
||||||
|
/** @defgroup IRDA_Private_Macros IRDA Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
|
||||||
|
((LENGTH) == IRDA_WORDLENGTH_9B))
|
||||||
|
#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
|
||||||
|
((PARITY) == IRDA_PARITY_EVEN) || \
|
||||||
|
((PARITY) == IRDA_PARITY_ODD))
|
||||||
|
#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
|
||||||
|
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
|
||||||
|
((MODE) == IRDA_POWERMODE_NORMAL))
|
||||||
|
#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
|
||||||
|
|
||||||
|
#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
|
||||||
|
#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
|
||||||
|
#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
|
||||||
|
/* UART BRR = mantissa + overflow + fraction
|
||||||
|
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
|
||||||
|
#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
|
||||||
|
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
|
||||||
|
(IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/** @defgroup IRDA_Private_Functions IRDA Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_IRDA_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,240 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_iwdg.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of IWDG HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_IWDG_H
|
||||||
|
#define __STM32F1xx_HAL_IWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup IWDG
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief IWDG Init structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||||
|
This parameter can be a value of @ref IWDG_Prescaler */
|
||||||
|
|
||||||
|
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||||
|
|
||||||
|
} IWDG_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief IWDG Handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||||
|
|
||||||
|
}IWDG_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
|
||||||
|
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||||
|
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||||
|
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||||
|
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||||
|
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||||
|
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the IWDG peripheral.
|
||||||
|
* @param __HANDLE__ IWDG handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reload IWDG counter with value defined in the reload register
|
||||||
|
* (write access to IWDG_PR & IWDG_RLR registers disabled).
|
||||||
|
* @param __HANDLE__ IWDG handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/Start functions ********************************************/
|
||||||
|
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* I/O operation functions ****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief IWDG Key Register BitMask
|
||||||
|
*/
|
||||||
|
#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
|
||||||
|
#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
|
||||||
|
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
|
||||||
|
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable write access to IWDG_PR and IWDG_RLR registers.
|
||||||
|
* @param __HANDLE__ IWDG handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable write access to IWDG_PR and IWDG_RLR registers.
|
||||||
|
* @param __HANDLE__ IWDG handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check IWDG prescaler value.
|
||||||
|
* @param __PRESCALER__ IWDG prescaler value
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
||||||
|
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
||||||
|
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
||||||
|
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
||||||
|
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
||||||
|
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
||||||
|
((__PRESCALER__) == IWDG_PRESCALER_256))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check IWDG reload value.
|
||||||
|
* @param __RELOAD__ IWDG reload value
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_IWDG_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,718 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_mmc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of MMC HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_MMC_H
|
||||||
|
#define __STM32F1xx_HAL_MMC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F103xE) || defined(STM32F103xG)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_sdmmc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC MMC
|
||||||
|
* @brief MMC HAL module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Exported_Types MMC Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
|
||||||
|
HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
|
||||||
|
HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
|
||||||
|
HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
|
||||||
|
HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
|
||||||
|
HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
|
||||||
|
HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
|
||||||
|
HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
|
||||||
|
}HAL_MMC_StateTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_MMC_CARD_READY = 0x00000001U, /*!< Card state is ready */
|
||||||
|
HAL_MMC_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
|
||||||
|
HAL_MMC_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
|
||||||
|
HAL_MMC_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
|
||||||
|
HAL_MMC_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
|
||||||
|
HAL_MMC_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
|
||||||
|
HAL_MMC_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
|
||||||
|
HAL_MMC_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
|
||||||
|
HAL_MMC_CARD_ERROR = 0x000000FFU /*!< Card response Error */
|
||||||
|
}HAL_MMC_CardStateTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MMC_InitTypeDef SDIO_InitTypeDef
|
||||||
|
#define MMC_TypeDef SDIO_TypeDef
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief MMC Card Information Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t CardType; /*!< Specifies the card Type */
|
||||||
|
|
||||||
|
uint32_t Class; /*!< Specifies the class of the card class */
|
||||||
|
|
||||||
|
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
|
||||||
|
|
||||||
|
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
|
||||||
|
|
||||||
|
uint32_t BlockSize; /*!< Specifies one block size in bytes */
|
||||||
|
|
||||||
|
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
|
||||||
|
|
||||||
|
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
|
||||||
|
|
||||||
|
}HAL_MMC_CardInfoTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief MMC handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
MMC_TypeDef *Instance; /*!< MMC registers base address */
|
||||||
|
|
||||||
|
MMC_InitTypeDef Init; /*!< MMC required parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< MMC locking object */
|
||||||
|
|
||||||
|
uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
|
||||||
|
|
||||||
|
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
|
||||||
|
|
||||||
|
uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
|
||||||
|
|
||||||
|
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
|
||||||
|
|
||||||
|
__IO uint32_t Context; /*!< MMC transfer context */
|
||||||
|
|
||||||
|
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
|
||||||
|
|
||||||
|
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
|
||||||
|
|
||||||
|
uint32_t CSD[4U]; /*!< MMC card specific data table */
|
||||||
|
|
||||||
|
uint32_t CID[4U]; /*!< MMC card identification number table */
|
||||||
|
|
||||||
|
}MMC_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint8_t CSDStruct; /*!< CSD structure */
|
||||||
|
__IO uint8_t SysSpecVersion; /*!< System specification version */
|
||||||
|
__IO uint8_t Reserved1; /*!< Reserved */
|
||||||
|
__IO uint8_t TAAC; /*!< Data read access time 1 */
|
||||||
|
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
|
||||||
|
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
|
||||||
|
__IO uint16_t CardComdClasses; /*!< Card command classes */
|
||||||
|
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
|
||||||
|
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
|
||||||
|
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
|
||||||
|
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
|
||||||
|
__IO uint8_t DSRImpl; /*!< DSR implemented */
|
||||||
|
__IO uint8_t Reserved2; /*!< Reserved */
|
||||||
|
__IO uint32_t DeviceSize; /*!< Device Size */
|
||||||
|
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
|
||||||
|
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
|
||||||
|
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
|
||||||
|
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
|
||||||
|
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
|
||||||
|
__IO uint8_t EraseGrSize; /*!< Erase group size */
|
||||||
|
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
|
||||||
|
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
|
||||||
|
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
|
||||||
|
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
|
||||||
|
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
|
||||||
|
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
|
||||||
|
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
|
||||||
|
__IO uint8_t Reserved3; /*!< Reserved */
|
||||||
|
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
|
||||||
|
__IO uint8_t FileFormatGrouop; /*!< File format group */
|
||||||
|
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
|
||||||
|
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
|
||||||
|
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
|
||||||
|
__IO uint8_t FileFormat; /*!< File format */
|
||||||
|
__IO uint8_t ECC; /*!< ECC code */
|
||||||
|
__IO uint8_t CSD_CRC; /*!< CSD CRC */
|
||||||
|
__IO uint8_t Reserved4; /*!< Always 1 */
|
||||||
|
|
||||||
|
}HAL_MMC_CardCSDTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||||
|
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
|
||||||
|
__IO uint32_t ProdName1; /*!< Product Name part1 */
|
||||||
|
__IO uint8_t ProdName2; /*!< Product Name part2 */
|
||||||
|
__IO uint8_t ProdRev; /*!< Product Revision */
|
||||||
|
__IO uint32_t ProdSN; /*!< Product Serial Number */
|
||||||
|
__IO uint8_t Reserved1; /*!< Reserved1 */
|
||||||
|
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
|
||||||
|
__IO uint8_t CID_CRC; /*!< CID CRC */
|
||||||
|
__IO uint8_t Reserved2; /*!< Always 1 */
|
||||||
|
|
||||||
|
}HAL_MMC_CardCIDTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Types_Group6 MMC Card Status returned by ACMD13
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
|
||||||
|
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
|
||||||
|
__IO uint16_t CardType; /*!< Carries information about card type */
|
||||||
|
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
|
||||||
|
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
|
||||||
|
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
|
||||||
|
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
|
||||||
|
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
|
||||||
|
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
|
||||||
|
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
|
||||||
|
|
||||||
|
}HAL_MMC_CardStatusTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Exported_Constants Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
|
||||||
|
|
||||||
|
#define CAPACITY 0x400000U /*!< Log Block Nuumber for 2 G bytes Cards */
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
|
||||||
|
#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
|
||||||
|
#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
|
||||||
|
#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
|
||||||
|
#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
|
||||||
|
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
|
||||||
|
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
|
||||||
|
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
|
||||||
|
#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
|
||||||
|
number of transferred bytes does not match the block length */
|
||||||
|
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
|
||||||
|
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
|
||||||
|
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
|
||||||
|
#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
|
||||||
|
command or if there was an attempt to access a locked card */
|
||||||
|
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
|
||||||
|
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
|
||||||
|
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
|
||||||
|
#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
|
||||||
|
#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
|
||||||
|
#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
|
||||||
|
#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
|
||||||
|
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
|
||||||
|
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
|
||||||
|
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
|
||||||
|
#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
|
||||||
|
of erase sequence command was received */
|
||||||
|
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
|
||||||
|
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
|
||||||
|
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
|
||||||
|
#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
|
||||||
|
#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
|
||||||
|
#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
|
||||||
|
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
|
||||||
|
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
|
||||||
|
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration structure
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
|
||||||
|
#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
|
||||||
|
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
|
||||||
|
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
|
||||||
|
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
|
||||||
|
#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
|
||||||
|
#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief
|
||||||
|
*/
|
||||||
|
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
|
||||||
|
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
|
||||||
|
#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
|
||||||
|
#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
|
||||||
|
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MMC_HIGH_VOLTAGE_CARD 0x00000000U
|
||||||
|
#define MMC_DUAL_VOLTAGE_CARD 0x00000001U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Exported_macros MMC Exported Macros
|
||||||
|
* @brief macros to handle interrupts and specific clock configurations
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the MMC device.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the MMC device.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the SDMMC DMA transfer.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the SDMMC DMA transfer.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the MMC device interrupt.
|
||||||
|
* @param __HANDLE__: MMC Handle
|
||||||
|
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||||
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||||
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the MMC device interrupt.
|
||||||
|
* @param __HANDLE__: MMC Handle
|
||||||
|
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||||
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||||
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified MMC flag is set or not.
|
||||||
|
* @param __HANDLE__: MMC Handle
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||||
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||||
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||||
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||||
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||||
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
||||||
|
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
||||||
|
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
||||||
|
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||||
|
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||||
|
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
||||||
|
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
||||||
|
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
||||||
|
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
||||||
|
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
||||||
|
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
||||||
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||||
|
* @retval The new state of MMC FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the MMC's pending flags.
|
||||||
|
* @param __HANDLE__: MMC Handle
|
||||||
|
* @param __FLAG__: specifies the flag to clear.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||||
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||||
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||||
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||||
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||||
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified MMC interrupt has occurred or not.
|
||||||
|
* @param __HANDLE__: MMC Handle
|
||||||
|
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||||
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||||
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @retval The new state of MMC IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the MMC's interrupt pending bits.
|
||||||
|
* @param __HANDLE__: MMC Handle
|
||||||
|
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Exported_Functions MMC Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
|
||||||
|
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
|
||||||
|
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Blocking mode: Polling */
|
||||||
|
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
|
||||||
|
/* Non-Blocking mode: IT */
|
||||||
|
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||||
|
/* Non-Blocking mode: DMA */
|
||||||
|
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||||
|
|
||||||
|
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
|
||||||
|
|
||||||
|
/* Callback in non blocking modes (DMA) */
|
||||||
|
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
|
||||||
|
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
|
||||||
|
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
|
||||||
|
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
|
||||||
|
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
|
||||||
|
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Private_Types MMC Private Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private defines -----------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Private_Defines MMC Private Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Private_Variables MMC Private Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Private_Constants MMC Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Private_Macros MMC Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions prototypes ----------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/** @defgroup MMC_Private_Functions MMC Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F103xE || STM32F103xG */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_MMC_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,347 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_nand.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of NAND HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_NAND_H
|
||||||
|
#define __STM32F1xx_HAL_NAND_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_fsmc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
|
||||||
|
/** @addtogroup NAND
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported typedef ----------------------------------------------------------*/
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup NAND_Exported_Types NAND Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL NAND State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
|
||||||
|
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
|
||||||
|
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
|
||||||
|
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
|
||||||
|
}HAL_NAND_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NAND Memory electronic signature Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
/*<! NAND memory electronic signature maker and device IDs */
|
||||||
|
|
||||||
|
uint8_t Maker_Id;
|
||||||
|
|
||||||
|
uint8_t Device_Id;
|
||||||
|
|
||||||
|
uint8_t Third_Id;
|
||||||
|
|
||||||
|
uint8_t Fourth_Id;
|
||||||
|
}NAND_IDTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NAND Memory address Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t Page; /*!< NAND memory Page address */
|
||||||
|
|
||||||
|
uint16_t Plane; /*!< NAND memory Plane address */
|
||||||
|
|
||||||
|
uint16_t Block; /*!< NAND memory Block address */
|
||||||
|
|
||||||
|
}NAND_AddressTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NAND Memory info Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
|
||||||
|
for 8 bits adressing or words for 16 bits addressing */
|
||||||
|
|
||||||
|
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
|
||||||
|
for 8 bits adressing or words for 16 bits addressing */
|
||||||
|
|
||||||
|
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
|
||||||
|
|
||||||
|
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
|
||||||
|
|
||||||
|
uint32_t PlaneNbr; /*!< NAND memory number of planes */
|
||||||
|
|
||||||
|
uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */
|
||||||
|
|
||||||
|
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
|
||||||
|
parameter is mandatory for some NAND parts after the read
|
||||||
|
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
|
||||||
|
Example: Toshiba THTH58BYG3S0HBAI6.
|
||||||
|
This parameter could be ENABLE or DISABLE
|
||||||
|
Please check the Read Mode sequnece in the NAND device datasheet */
|
||||||
|
}NAND_DeviceConfigTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NAND handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
FSMC_NAND_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< NAND locking object */
|
||||||
|
|
||||||
|
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
|
||||||
|
|
||||||
|
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
|
||||||
|
|
||||||
|
}NAND_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/** @defgroup NAND_Exported_Macros NAND Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset NAND handle state
|
||||||
|
* @param __HANDLE__: specifies the NAND handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Initialization/de-initialization functions ********************************/
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
|
||||||
|
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
|
||||||
|
|
||||||
|
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
|
||||||
|
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
|
||||||
|
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
|
||||||
|
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* IO operation functions ****************************************************/
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||||
|
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
||||||
|
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* NAND Control functions ****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
|
||||||
|
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
|
||||||
|
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* NAND State functions *******************************************************/
|
||||||
|
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
|
||||||
|
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @addtogroup NAND_Private_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define NAND_DEVICE1 FSMC_BANK2
|
||||||
|
#define NAND_DEVICE2 FSMC_BANK3
|
||||||
|
#define NAND_WRITE_TIMEOUT 1000U
|
||||||
|
|
||||||
|
#define CMD_AREA (1U<<16U) /* A16 = CLE high */
|
||||||
|
#define ADDR_AREA (1U<<17U) /* A17 = ALE high */
|
||||||
|
|
||||||
|
#define NAND_CMD_AREA_A ((uint8_t)0x00)
|
||||||
|
#define NAND_CMD_AREA_B ((uint8_t)0x01)
|
||||||
|
#define NAND_CMD_AREA_C ((uint8_t)0x50)
|
||||||
|
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
|
||||||
|
|
||||||
|
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
|
||||||
|
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
|
||||||
|
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
|
||||||
|
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
|
||||||
|
#define NAND_CMD_READID ((uint8_t)0x90)
|
||||||
|
#define NAND_CMD_STATUS ((uint8_t)0x70)
|
||||||
|
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
|
||||||
|
#define NAND_CMD_RESET ((uint8_t)0xFF)
|
||||||
|
|
||||||
|
/* NAND memory status */
|
||||||
|
#define NAND_VALID_ADDRESS 0x00000100U
|
||||||
|
#define NAND_INVALID_ADDRESS 0x00000200U
|
||||||
|
#define NAND_TIMEOUT_ERROR 0x00000400U
|
||||||
|
#define NAND_BUSY 0x00000000U
|
||||||
|
#define NAND_ERROR 0x00000001U
|
||||||
|
#define NAND_READY 0x00000040U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @addtogroup NAND_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NAND memory address computation.
|
||||||
|
* @param __ADDRESS__: NAND memory address.
|
||||||
|
* @param __HANDLE__ : NAND handle.
|
||||||
|
* @retval NAND Raw address value
|
||||||
|
*/
|
||||||
|
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
|
||||||
|
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NAND memory Column address computation.
|
||||||
|
* @param __HANDLE__: NAND handle.
|
||||||
|
* @retval NAND Raw address value
|
||||||
|
*/
|
||||||
|
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NAND memory address cycling.
|
||||||
|
* @param __ADDRESS__: NAND memory address.
|
||||||
|
* @retval NAND address cycling value.
|
||||||
|
*/
|
||||||
|
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
|
||||||
|
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */
|
||||||
|
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */
|
||||||
|
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NAND memory Columns cycling.
|
||||||
|
* @param __ADDRESS__: NAND memory address.
|
||||||
|
* @retval NAND Column address cycling value.
|
||||||
|
*/
|
||||||
|
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
|
||||||
|
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd Column addressing cycle */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_NAND_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,306 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_nor.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of NOR HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_NOR_H
|
||||||
|
#define __STM32F1xx_HAL_NOR_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_fsmc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
|
||||||
|
/** @addtogroup NOR
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup NOR_Private_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* NOR device IDs addresses */
|
||||||
|
#define MC_ADDRESS ((uint16_t)0x0000)
|
||||||
|
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
|
||||||
|
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
|
||||||
|
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
|
||||||
|
|
||||||
|
/* NOR CFI IDs addresses */
|
||||||
|
#define CFI1_ADDRESS ((uint16_t)0x10)
|
||||||
|
#define CFI2_ADDRESS ((uint16_t)0x11)
|
||||||
|
#define CFI3_ADDRESS ((uint16_t)0x12)
|
||||||
|
#define CFI4_ADDRESS ((uint16_t)0x13)
|
||||||
|
|
||||||
|
/* NOR operation wait timeout */
|
||||||
|
#define NOR_TMEOUT ((uint16_t)0xFFFF)
|
||||||
|
|
||||||
|
/* NOR memory data width */
|
||||||
|
#define NOR_MEMORY_8B ((uint8_t)0x0)
|
||||||
|
#define NOR_MEMORY_16B ((uint8_t)0x1)
|
||||||
|
|
||||||
|
/* NOR memory device read/write start address */
|
||||||
|
#define NOR_MEMORY_ADRESS1 FSMC_BANK1_1
|
||||||
|
#define NOR_MEMORY_ADRESS2 FSMC_BANK1_2
|
||||||
|
#define NOR_MEMORY_ADRESS3 FSMC_BANK1_3
|
||||||
|
#define NOR_MEMORY_ADRESS4 FSMC_BANK1_4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup NOR_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NOR memory address shifting.
|
||||||
|
* @param __NOR_ADDRESS: NOR base address
|
||||||
|
* @param __NOR_MEMORY_WIDTH_: NOR memory width
|
||||||
|
* @param __ADDRESS__: NOR memory address
|
||||||
|
* @retval NOR shifted address value
|
||||||
|
*/
|
||||||
|
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
|
||||||
|
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
|
||||||
|
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
|
||||||
|
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NOR memory write data to specified address.
|
||||||
|
* @param __ADDRESS__: NOR memory address
|
||||||
|
* @param __DATA__: Data to write
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported typedef ----------------------------------------------------------*/
|
||||||
|
/** @defgroup NOR_Exported_Types NOR Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL SRAM State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
|
||||||
|
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
|
||||||
|
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
|
||||||
|
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
|
||||||
|
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
|
||||||
|
}HAL_NOR_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FSMC NOR Status typedef
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_NOR_STATUS_SUCCESS = 0U,
|
||||||
|
HAL_NOR_STATUS_ONGOING,
|
||||||
|
HAL_NOR_STATUS_ERROR,
|
||||||
|
HAL_NOR_STATUS_TIMEOUT
|
||||||
|
}HAL_NOR_StatusTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FSMC NOR ID typedef
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
|
||||||
|
|
||||||
|
uint16_t Device_Code1;
|
||||||
|
|
||||||
|
uint16_t Device_Code2;
|
||||||
|
|
||||||
|
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
|
||||||
|
These codes can be accessed by performing read operations with specific
|
||||||
|
control signals and addresses set.They can also be accessed by issuing
|
||||||
|
an Auto Select command */
|
||||||
|
}NOR_IDTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FSMC NOR CFI typedef
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
/*!< Defines the information stored in the memory's Common flash interface
|
||||||
|
which contains a description of various electrical and timing parameters,
|
||||||
|
density information and functions supported by the memory */
|
||||||
|
|
||||||
|
uint16_t CFI_1;
|
||||||
|
|
||||||
|
uint16_t CFI_2;
|
||||||
|
|
||||||
|
uint16_t CFI_3;
|
||||||
|
|
||||||
|
uint16_t CFI_4;
|
||||||
|
}NOR_CFITypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NOR handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||||
|
|
||||||
|
FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< NOR locking object */
|
||||||
|
|
||||||
|
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
|
||||||
|
|
||||||
|
}NOR_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup NOR_Exported_macro NOR Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset NOR handle state
|
||||||
|
* @param __HANDLE__: NOR handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup NOR_Exported_Functions NOR Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup NOR_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||||
|
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
|
||||||
|
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
|
||||||
|
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
|
||||||
|
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup NOR_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* I/O operation functions ***************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
|
||||||
|
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
|
||||||
|
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||||
|
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
|
||||||
|
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
|
||||||
|
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup NOR_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* NOR Control functions *****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
|
||||||
|
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup NOR_Exported_Functions_Group4
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* NOR State functions ********************************************************/
|
||||||
|
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
|
||||||
|
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_NOR_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,248 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_pccard.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of PCCARD HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_PCCARD_H
|
||||||
|
#define __STM32F1xx_HAL_PCCARD_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_fsmc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
|
||||||
|
/** @addtogroup PCCARD
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PCCARD_Private_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PCCARD_DEVICE_ADDRESS FSMC_BANK4
|
||||||
|
#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x08000000U)) /* Attribute space size to @0x9BFF FFFF */
|
||||||
|
#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
|
||||||
|
#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x0C000000U)) /* IO space size to @0x9FFF FFFF */
|
||||||
|
#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FSMC_BANK4 + 0x0C0001F0U)) /* IO space size to @0x9FFF FFFF */
|
||||||
|
|
||||||
|
/* Compact Flash-ATA registers description */
|
||||||
|
#define ATA_DATA ((uint8_t)0x00) /* Data register */
|
||||||
|
#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
|
||||||
|
#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
|
||||||
|
#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
|
||||||
|
#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
|
||||||
|
#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
|
||||||
|
#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
|
||||||
|
#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
|
||||||
|
#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
|
||||||
|
#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
|
||||||
|
|
||||||
|
/* Compact Flash-ATA commands */
|
||||||
|
#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
|
||||||
|
#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
|
||||||
|
#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
|
||||||
|
#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
|
||||||
|
|
||||||
|
/* Compact Flash status */
|
||||||
|
#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
|
||||||
|
#define PCCARD_BUSY ((uint8_t)0x80)
|
||||||
|
#define PCCARD_PROGR ((uint8_t)0x01)
|
||||||
|
#define PCCARD_READY ((uint8_t)0x40)
|
||||||
|
|
||||||
|
#define PCCARD_SECTOR_SIZE 255U /* In half words */
|
||||||
|
|
||||||
|
|
||||||
|
/* Compact Flash redefinition */
|
||||||
|
#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
|
||||||
|
#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
|
||||||
|
#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
|
||||||
|
#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
|
||||||
|
#define HAL_CF_Reset HAL_PCCARD_Reset
|
||||||
|
|
||||||
|
#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
|
||||||
|
#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
|
||||||
|
|
||||||
|
#define CF_SUCCESS HAL_PCCARD_STATUS_SUCCESS
|
||||||
|
#define CF_ONGOING HAL_PCCARD_STATUS_ONGOING
|
||||||
|
#define CF_ERROR HAL_PCCARD_STATUS_ERROR
|
||||||
|
#define CF_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
|
||||||
|
#define CF_StatusTypedef HAL_PCCARD_StatusTypeDef
|
||||||
|
|
||||||
|
#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
|
||||||
|
#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
|
||||||
|
#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
|
||||||
|
#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
|
||||||
|
#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
|
||||||
|
|
||||||
|
#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
|
||||||
|
#define CF_BUSY PCCARD_BUSY
|
||||||
|
#define CF_PROGR PCCARD_PROGR
|
||||||
|
#define CF_READY PCCARD_READY
|
||||||
|
|
||||||
|
#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported typedef ----------------------------------------------------------*/
|
||||||
|
/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL PCCARD State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
|
||||||
|
HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
|
||||||
|
HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
|
||||||
|
HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
|
||||||
|
}HAL_PCCARD_StateTypeDef;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_PCCARD_STATUS_SUCCESS = 0U,
|
||||||
|
HAL_PCCARD_STATUS_ONGOING,
|
||||||
|
HAL_PCCARD_STATUS_ERROR,
|
||||||
|
HAL_PCCARD_STATUS_TIMEOUT
|
||||||
|
}HAL_PCCARD_StatusTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FSMC_PCCARD handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
|
||||||
|
|
||||||
|
FSMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
|
||||||
|
|
||||||
|
__IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
|
||||||
|
|
||||||
|
}PCCARD_HandleTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset PCCARD handle state
|
||||||
|
* @param __HANDLE__: specifies the PCCARD handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
|
||||||
|
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
|
||||||
|
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* IO operation functions *****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
|
||||||
|
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
|
||||||
|
void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* PCCARD State functions *******************************************************/
|
||||||
|
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
|
||||||
|
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
|
||||||
|
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_PCCARD_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,853 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_pcd.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of PCD HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_PCD_H
|
||||||
|
#define __STM32F1xx_HAL_PCD_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F102x6) || defined(STM32F102xB) || \
|
||||||
|
defined(STM32F103x6) || defined(STM32F103xB) || \
|
||||||
|
defined(STM32F103xE) || defined(STM32F103xG) || \
|
||||||
|
defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_usb.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PCD
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup PCD_Exported_Types PCD Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PCD State structure definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_PCD_STATE_RESET = 0x00U,
|
||||||
|
HAL_PCD_STATE_READY = 0x01U,
|
||||||
|
HAL_PCD_STATE_ERROR = 0x02U,
|
||||||
|
HAL_PCD_STATE_BUSY = 0x03U,
|
||||||
|
HAL_PCD_STATE_TIMEOUT = 0x04U
|
||||||
|
} PCD_StateTypeDef;
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
/**
|
||||||
|
* @brief PCD double buffered endpoint direction
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
PCD_EP_DBUF_OUT,
|
||||||
|
PCD_EP_DBUF_IN,
|
||||||
|
PCD_EP_DBUF_ERR,
|
||||||
|
}PCD_EP_DBUF_DIR;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PCD endpoint buffer number
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
PCD_EP_NOBUF,
|
||||||
|
PCD_EP_BUF0,
|
||||||
|
PCD_EP_BUF1
|
||||||
|
}PCD_EP_BUF_NUM;
|
||||||
|
#endif /* USB */
|
||||||
|
|
||||||
|
#if defined (USB_OTG_FS)
|
||||||
|
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
|
||||||
|
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
|
||||||
|
typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
|
||||||
|
#endif /* USB_OTG_FS */
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
typedef USB_TypeDef PCD_TypeDef;
|
||||||
|
typedef USB_CfgTypeDef PCD_InitTypeDef;
|
||||||
|
typedef USB_EPTypeDef PCD_EPTypeDef;
|
||||||
|
#endif /* USB */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PCD Handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
PCD_TypeDef *Instance; /*!< Register base address */
|
||||||
|
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||||
|
__IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */
|
||||||
|
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
|
||||||
|
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
|
||||||
|
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||||
|
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||||
|
uint32_t Setup[12U]; /*!< Setup packet buffer */
|
||||||
|
void *pData; /*!< Pointer to upper stack Handler */
|
||||||
|
} PCD_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Include PCD HAL Extension module */
|
||||||
|
#include "stm32f1xx_hal_pcd_ex.h"
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCD_Speed PCD Speed
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define PCD_SPEED_HIGH 0U /* Not Supported */
|
||||||
|
#define PCD_SPEED_HIGH_IN_FULL 1U /* Not Supported */
|
||||||
|
#define PCD_SPEED_FULL 2U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCD_PHY_Module PCD PHY Module
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define PCD_PHY_EMBEDDED 2U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#ifndef USBD_FS_TRDT_VALUE
|
||||||
|
#define USBD_FS_TRDT_VALUE 5U
|
||||||
|
#endif /* USBD_FS_TRDT_VALUE */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||||
|
* @brief macros to handle interrupts and specific clock configurations
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB_OTG_FS)
|
||||||
|
|
||||||
|
#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||||
|
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||||
|
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
|
||||||
|
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
|
||||||
|
|
||||||
|
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
|
||||||
|
~(USB_OTG_PCGCCTL_STOPCLK)
|
||||||
|
|
||||||
|
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
|
||||||
|
|
||||||
|
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
|
||||||
|
|
||||||
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||||
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||||
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||||
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
|
||||||
|
|
||||||
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||||
|
do{ \
|
||||||
|
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \
|
||||||
|
do{ \
|
||||||
|
EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||||
|
do{ \
|
||||||
|
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||||
|
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
|
||||||
|
#endif /* USB_OTG_FS */
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||||
|
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||||
|
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||||
|
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
|
||||||
|
|
||||||
|
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
|
||||||
|
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
|
||||||
|
#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
|
||||||
|
#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
|
||||||
|
|
||||||
|
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
|
||||||
|
do{ \
|
||||||
|
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \
|
||||||
|
do{ \
|
||||||
|
EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||||
|
do{ \
|
||||||
|
EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
|
||||||
|
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
|
||||||
|
EXTI->FTSR |= USB_WAKEUP_EXTI_LINE; \
|
||||||
|
} while(0U)
|
||||||
|
#endif /* USB */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Initialization/de-initialization functions ********************************/
|
||||||
|
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* I/O operation functions ***************************************************/
|
||||||
|
/* Non-Blocking mode: Interrupt */
|
||||||
|
/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||||
|
|
||||||
|
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||||
|
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||||
|
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||||
|
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||||
|
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Peripheral Control functions **********************************************/
|
||||||
|
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||||
|
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||||
|
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Peripheral State functions ************************************************/
|
||||||
|
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup PCD_Private_Constants PCD Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB_OTG_FS)
|
||||||
|
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
|
||||||
|
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
|
||||||
|
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
|
||||||
|
|
||||||
|
#define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */
|
||||||
|
#endif /* USB_OTG_FS */
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
#define USB_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */
|
||||||
|
#endif /* USB */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define PCD_EP0MPS_64 DEP0CTL_MPS_64
|
||||||
|
#define PCD_EP0MPS_32 DEP0CTL_MPS_32
|
||||||
|
#define PCD_EP0MPS_16 DEP0CTL_MPS_16
|
||||||
|
#define PCD_EP0MPS_08 DEP0CTL_MPS_8
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCD_ENDP PCD ENDP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define PCD_ENDP0 ((uint8_t)0)
|
||||||
|
#define PCD_ENDP1 ((uint8_t)1)
|
||||||
|
#define PCD_ENDP2 ((uint8_t)2)
|
||||||
|
#define PCD_ENDP3 ((uint8_t)3)
|
||||||
|
#define PCD_ENDP4 ((uint8_t)4)
|
||||||
|
#define PCD_ENDP5 ((uint8_t)5)
|
||||||
|
#define PCD_ENDP6 ((uint8_t)6)
|
||||||
|
#define PCD_ENDP7 ((uint8_t)7)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define PCD_SNG_BUF 0U
|
||||||
|
#define PCD_DBL_BUF 1U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* USB */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @addtogroup PCD_Private_Macros PCD Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB)
|
||||||
|
/* SetENDPOINT */
|
||||||
|
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2U)= (uint16_t)(wRegValue))
|
||||||
|
|
||||||
|
/* GetENDPOINT */
|
||||||
|
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2U))
|
||||||
|
|
||||||
|
/* ENDPOINT transfer */
|
||||||
|
#define USB_EP0StartXfer USB_EPStartXfer
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param wType: Endpoint Type.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||||
|
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval Endpoint Type
|
||||||
|
*/
|
||||||
|
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief free buffer used from the application realizing it to the line
|
||||||
|
toggles bit SW_BUF in the double buffered endpoint register
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param bDir: Direction
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
|
||||||
|
{\
|
||||||
|
if ((bDir) == PCD_EP_DBUF_OUT)\
|
||||||
|
{ /* OUT double buffered endpoint */\
|
||||||
|
PCD_TX_DTOG((USBx), (bEpNum));\
|
||||||
|
}\
|
||||||
|
else if ((bDir) == PCD_EP_DBUF_IN)\
|
||||||
|
{ /* IN double buffered endpoint */\
|
||||||
|
PCD_RX_DTOG((USBx), (bEpNum));\
|
||||||
|
}\
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief gets direction of the double buffered endpoint
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval EP_DBUF_OUT, EP_DBUF_IN,
|
||||||
|
* EP_DBUF_ERR if the endpoint counter not yet programmed.
|
||||||
|
*/
|
||||||
|
#define PCD_GET_DB_DIR(USBx, bEpNum)\
|
||||||
|
{\
|
||||||
|
if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
|
||||||
|
return(PCD_EP_DBUF_OUT);\
|
||||||
|
else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
|
||||||
|
return(PCD_EP_DBUF_IN);\
|
||||||
|
else\
|
||||||
|
return(PCD_EP_DBUF_ERR);\
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param wState: new state
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
|
||||||
|
\
|
||||||
|
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
|
||||||
|
/* toggle first bit ? */ \
|
||||||
|
if((USB_EPTX_DTOG1 & (wState))!= 0U)\
|
||||||
|
{ \
|
||||||
|
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||||
|
} \
|
||||||
|
/* toggle second bit ? */ \
|
||||||
|
if((USB_EPTX_DTOG2 & (wState))!= 0U) \
|
||||||
|
{ \
|
||||||
|
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||||
|
} \
|
||||||
|
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
|
||||||
|
} /* PCD_SET_EP_TX_STATUS */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param wState: new state
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
|
||||||
|
register uint16_t _wRegVal; \
|
||||||
|
\
|
||||||
|
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
|
||||||
|
/* toggle first bit ? */ \
|
||||||
|
if((USB_EPRX_DTOG1 & (wState))!= 0U) \
|
||||||
|
{ \
|
||||||
|
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||||
|
} \
|
||||||
|
/* toggle second bit ? */ \
|
||||||
|
if((USB_EPRX_DTOG2 & (wState))!= 0U) \
|
||||||
|
{ \
|
||||||
|
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||||
|
} \
|
||||||
|
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
|
||||||
|
} /* PCD_SET_EP_RX_STATUS */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param wStaterx: new state.
|
||||||
|
* @param wStatetx: new state.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
|
||||||
|
register uint32_t _wRegVal; \
|
||||||
|
\
|
||||||
|
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
|
||||||
|
/* toggle first bit ? */ \
|
||||||
|
if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
|
||||||
|
{ \
|
||||||
|
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||||
|
} \
|
||||||
|
/* toggle second bit ? */ \
|
||||||
|
if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
|
||||||
|
{ \
|
||||||
|
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||||
|
} \
|
||||||
|
/* toggle first bit ? */ \
|
||||||
|
if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
|
||||||
|
{ \
|
||||||
|
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||||
|
} \
|
||||||
|
/* toggle second bit ? */ \
|
||||||
|
if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
|
||||||
|
{ \
|
||||||
|
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||||
|
} \
|
||||||
|
PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
|
||||||
|
} /* PCD_SET_EP_TXRX_STATUS */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
|
||||||
|
* /STAT_RX[1:0])
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval status
|
||||||
|
*/
|
||||||
|
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
|
||||||
|
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief sets directly the VALID tx/rx-status into the endpoint register
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
|
||||||
|
#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief checks stall condition in an endpoint.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval TRUE = endpoint in stall condition.
|
||||||
|
*/
|
||||||
|
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
|
||||||
|
== USB_EP_TX_STALL)
|
||||||
|
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
|
||||||
|
== USB_EP_RX_STALL)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief set & clear EP_KIND bit.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||||
|
(USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
|
||||||
|
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||||
|
(USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
|
||||||
|
#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
|
||||||
|
#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||||
|
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
|
||||||
|
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||||
|
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||||
|
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
|
||||||
|
#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||||
|
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0U)\
|
||||||
|
{ \
|
||||||
|
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||||
|
}
|
||||||
|
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0U)\
|
||||||
|
{ \
|
||||||
|
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets address in an endpoint register.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param bAddr: Address.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||||
|
USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
|
||||||
|
|
||||||
|
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
|
||||||
|
|
||||||
|
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U)*2U+ ((uint32_t)(USBx) + 0x400U)))
|
||||||
|
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+2U)*2U+ ((uint32_t)(USBx) + 0x400U)))
|
||||||
|
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+4U)*2U+ ((uint32_t)(USBx) + 0x400U)))
|
||||||
|
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+6U)*2U+ ((uint32_t)(USBx) + 0x400U)))
|
||||||
|
|
||||||
|
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
|
||||||
|
uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
|
||||||
|
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief sets address of the tx/rx buffer.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param wAddr: address to be set (must be word aligned).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
|
||||||
|
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Gets address of the tx/rx buffer.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval address of the buffer.
|
||||||
|
*/
|
||||||
|
#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
|
||||||
|
#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets counter of rx buffer with no. of blocks.
|
||||||
|
* @param dwReg: Register
|
||||||
|
* @param wCount: Counter.
|
||||||
|
* @param wNBlocks: no. of Blocks.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
|
||||||
|
(wNBlocks) = (wCount) >> 5U;\
|
||||||
|
if(((wCount) & 0x1FU) == 0U)\
|
||||||
|
{ \
|
||||||
|
(wNBlocks)--;\
|
||||||
|
} \
|
||||||
|
*pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | 0x8000U); \
|
||||||
|
}/* PCD_CALC_BLK32 */
|
||||||
|
|
||||||
|
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
|
||||||
|
(wNBlocks) = (wCount) >> 1U;\
|
||||||
|
if(((wCount) & 0x01U) != 0U)\
|
||||||
|
{ \
|
||||||
|
(wNBlocks)++;\
|
||||||
|
} \
|
||||||
|
*pdwReg = (uint16_t)((wNBlocks) << 10U);\
|
||||||
|
}/* PCD_CALC_BLK2 */
|
||||||
|
|
||||||
|
#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
|
||||||
|
uint16_t wNBlocks;\
|
||||||
|
if((wCount) > 62U) \
|
||||||
|
{ \
|
||||||
|
PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \
|
||||||
|
} \
|
||||||
|
else \
|
||||||
|
{ \
|
||||||
|
PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \
|
||||||
|
} \
|
||||||
|
}/* PCD_SET_EP_CNT_RX_REG */
|
||||||
|
|
||||||
|
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
|
||||||
|
uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
|
||||||
|
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief sets counter for the tx/rx buffer.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param wCount: Counter value.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief gets counter of the tx buffer.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval Counter value
|
||||||
|
*/
|
||||||
|
#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3FFU)
|
||||||
|
#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3FFU)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets buffer 0/1 address in a double buffer endpoint.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param wBuf0Addr: buffer 0 address.
|
||||||
|
* @retval Counter value
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
|
||||||
|
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets addresses in a double buffer endpoint.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param wBuf0Addr: buffer 0 address.
|
||||||
|
* @param wBuf1Addr = buffer 1 address.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
|
||||||
|
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
|
||||||
|
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
|
||||||
|
} /* PCD_SET_EP_DBUF_ADDR */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
|
||||||
|
#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @param bDir: endpoint dir EP_DBUF_OUT = OUT
|
||||||
|
* EP_DBUF_IN = IN
|
||||||
|
* @param wCount: Counter value
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
|
||||||
|
if((bDir) == PCD_EP_DBUF_OUT)\
|
||||||
|
/* OUT endpoint */ \
|
||||||
|
{PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
|
||||||
|
else if((bDir) == PCD_EP_DBUF_IN)\
|
||||||
|
/* IN endpoint */ \
|
||||||
|
*PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
|
||||||
|
} /* SetEPDblBuf0Count*/
|
||||||
|
|
||||||
|
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
|
||||||
|
if((bDir) == PCD_EP_DBUF_OUT)\
|
||||||
|
{/* OUT endpoint */ \
|
||||||
|
PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \
|
||||||
|
} \
|
||||||
|
else if((bDir) == PCD_EP_DBUF_IN)\
|
||||||
|
{/* IN endpoint */ \
|
||||||
|
*PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
|
||||||
|
} \
|
||||||
|
} /* SetEPDblBuf1Count */
|
||||||
|
|
||||||
|
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
|
||||||
|
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||||
|
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||||
|
} /* PCD_SET_EP_DBUF_CNT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
|
||||||
|
* @param USBx: USB peripheral instance register address.
|
||||||
|
* @param bEpNum: Endpoint Number.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
|
||||||
|
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
|
||||||
|
|
||||||
|
#endif /* USB */
|
||||||
|
|
||||||
|
/** @defgroup PCD_Instance_definition PCD Instance definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F102x6 || STM32F102xB || */
|
||||||
|
/* STM32F103x6 || STM32F103xB || */
|
||||||
|
/* STM32F103xE || STM32F103xG || */
|
||||||
|
/* STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_PCD_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,116 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_pcd_ex.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of Extended PCD HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_PCD_EX_H
|
||||||
|
#define __STM32F1xx_HAL_PCD_EX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F102x6) || defined(STM32F102xB) || \
|
||||||
|
defined(STM32F103x6) || defined(STM32F103xB) || \
|
||||||
|
defined(STM32F103xE) || defined(STM32F103xG) || \
|
||||||
|
defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PCDEx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB_OTG_FS)
|
||||||
|
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
|
||||||
|
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
|
||||||
|
#endif /* USB_OTG_FS */
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
|
||||||
|
uint16_t ep_addr,
|
||||||
|
uint16_t ep_kind,
|
||||||
|
uint32_t pmaadress);
|
||||||
|
#endif /* USB */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PCDEx_Exported_Functions_Group2 Peripheral State functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F102x6 || STM32F102xB || */
|
||||||
|
/* STM32F103x6 || STM32F103xB || */
|
||||||
|
/* STM32F103xE || STM32F103xG || */
|
||||||
|
/* STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_PCD_EX_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,578 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_rtc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of RTC HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_RTC_H
|
||||||
|
#define __STM32F1xx_HAL_RTC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RTC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RTC_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND))
|
||||||
|
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
|
||||||
|
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
|
||||||
|
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
|
||||||
|
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
|
||||||
|
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
|
||||||
|
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
|
||||||
|
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
|
||||||
|
#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
|
||||||
|
#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \
|
||||||
|
((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \
|
||||||
|
((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \
|
||||||
|
((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RTC_Private_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup RTC_Timeout_Value Default Timeout Value
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_TIMEOUT_VALUE 1000U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup RTC_Exported_Types RTC Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief RTC Time structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
|
||||||
|
|
||||||
|
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||||
|
|
||||||
|
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||||
|
|
||||||
|
}RTC_TimeTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief RTC Alarm structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
|
||||||
|
|
||||||
|
uint32_t Alarm; /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1).
|
||||||
|
This parameter can be a value of @ref RTC_Alarms_Definitions */
|
||||||
|
}RTC_AlarmTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
|
||||||
|
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
|
||||||
|
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
|
||||||
|
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
|
||||||
|
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
|
||||||
|
|
||||||
|
}HAL_RTCStateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief RTC Configuration Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||||
|
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF or RTC_AUTO_1_SECOND
|
||||||
|
If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */
|
||||||
|
|
||||||
|
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC Tamper pin.
|
||||||
|
This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */
|
||||||
|
|
||||||
|
}RTC_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief RTC Date structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate).
|
||||||
|
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||||
|
|
||||||
|
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||||
|
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||||
|
|
||||||
|
uint8_t Date; /*!< Specifies the RTC Date.
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||||
|
|
||||||
|
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
|
||||||
|
|
||||||
|
}RTC_DateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Time Handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
RTC_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
RTC_InitTypeDef Init; /*!< RTC required parameters */
|
||||||
|
|
||||||
|
RTC_DateTypeDef DateToUpdate; /*!< Current date set by user and updated automatically */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< RTC locking object */
|
||||||
|
|
||||||
|
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
|
||||||
|
|
||||||
|
}RTC_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_AUTO_1_SECOND 0xFFFFFFFFU
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_FORMAT_BIN 0x000000000U
|
||||||
|
#define RTC_FORMAT_BCD 0x000000001U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Month_Date_Definitions Month Definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Coded in BCD format */
|
||||||
|
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
|
||||||
|
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
|
||||||
|
#define RTC_MONTH_MARCH ((uint8_t)0x03)
|
||||||
|
#define RTC_MONTH_APRIL ((uint8_t)0x04)
|
||||||
|
#define RTC_MONTH_MAY ((uint8_t)0x05)
|
||||||
|
#define RTC_MONTH_JUNE ((uint8_t)0x06)
|
||||||
|
#define RTC_MONTH_JULY ((uint8_t)0x07)
|
||||||
|
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
|
||||||
|
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
|
||||||
|
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
|
||||||
|
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
|
||||||
|
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
|
||||||
|
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
|
||||||
|
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
|
||||||
|
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
|
||||||
|
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
|
||||||
|
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
|
||||||
|
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x00)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Alarms_Definitions Alarms Definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_ALARM_A 0U /*!< Specify alarm ID (mainly for legacy purposes) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RTC_OUTPUTSOURCE_NONE 0x00000000U /*!< No output on the TAMPER pin */
|
||||||
|
#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */
|
||||||
|
#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */
|
||||||
|
#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_IT_OW RTC_CRH_OWIE /*!< Overflow interrupt */
|
||||||
|
#define RTC_IT_ALRA RTC_CRH_ALRIE /*!< Alarm interrupt */
|
||||||
|
#define RTC_IT_SEC RTC_CRH_SECIE /*!< Second interrupt */
|
||||||
|
#define RTC_IT_TAMP1 BKP_CSR_TPIE /*!< TAMPER Pin interrupt enable */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Flags_Definitions Flags Definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_FLAG_RTOFF RTC_CRL_RTOFF /*!< RTC Operation OFF flag */
|
||||||
|
#define RTC_FLAG_RSF RTC_CRL_RSF /*!< Registers Synchronized flag */
|
||||||
|
#define RTC_FLAG_OW RTC_CRL_OWF /*!< Overflow flag */
|
||||||
|
#define RTC_FLAG_ALRAF RTC_CRL_ALRF /*!< Alarm flag */
|
||||||
|
#define RTC_FLAG_SEC RTC_CRL_SECF /*!< Second flag */
|
||||||
|
#define RTC_FLAG_TAMP1F BKP_CSR_TEF /*!< Tamper Interrupt Flag */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup RTC_Exported_macros RTC Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset RTC handle state
|
||||||
|
* @param __HANDLE__: RTC handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the write protection for RTC registers.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the write protection for RTC registers.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the RTC Alarm interrupt.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the RTC Alarm interrupt.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the selected RTC Alarm's flag status.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_FLAG_ALRAF
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the RTC Alarm's pending flags.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_FLAG_ALRAF
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable interrupt on ALARM Exti Line 17.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable interrupt on ALARM Exti Line 17.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable event on ALARM Exti Line 17.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable event on ALARM Exti Line 17.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ALARM EXTI line configuration: set falling edge trigger.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the ALARM Extended Interrupt Falling Trigger.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ALARM EXTI line configuration: set rising edge trigger.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the ALARM Extended Interrupt Rising Trigger.
|
||||||
|
* This parameter can be:
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ALARM EXTI line configuration: set rising & falling edge trigger.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||||
|
do{ \
|
||||||
|
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
|
||||||
|
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger.
|
||||||
|
* This parameter can be:
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||||
|
do{ \
|
||||||
|
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
|
||||||
|
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified ALARM EXTI interrupt flag is set or not.
|
||||||
|
* @retval EXTI ALARM Line Status.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the ALARM EXTI flag.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Generate a Software interrupt on selected EXTI line.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Include RTC HAL Extension module */
|
||||||
|
#include "stm32f1xx_hal_rtc_ex.h"
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup RTC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Initialization and de-initialization functions ****************************/
|
||||||
|
/** @addtogroup RTC_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
||||||
|
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
||||||
|
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||||
|
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* RTC Time and Date functions ************************************************/
|
||||||
|
/** @addtogroup RTC_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||||
|
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||||
|
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||||
|
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* RTC Alarm functions ********************************************************/
|
||||||
|
/** @addtogroup RTC_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||||
|
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||||
|
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
|
||||||
|
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
||||||
|
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||||
|
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||||
|
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Peripheral State functions *************************************************/
|
||||||
|
/** @addtogroup RTC_Exported_Functions_Group4
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Peripheral Control functions ***********************************************/
|
||||||
|
/** @addtogroup RTC_Exported_Functions_Group5
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_RTC_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,430 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_rtc_ex.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of RTC HAL Extension module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_RTC_EX_H
|
||||||
|
#define __STM32F1xx_HAL_RTC_EX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RTCEx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RTCEx_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
|
||||||
|
|
||||||
|
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
|
||||||
|
((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
|
||||||
|
|
||||||
|
#if RTC_BKP_NUMBER > 10U
|
||||||
|
#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42)))
|
||||||
|
#else
|
||||||
|
#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER)
|
||||||
|
#endif
|
||||||
|
#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief RTC Tamper structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Tamper; /*!< Specifies the Tamper Pin.
|
||||||
|
This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
|
||||||
|
|
||||||
|
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
|
||||||
|
This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
|
||||||
|
|
||||||
|
}RTC_TamperTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_TAMPER_1 BKP_CR_TPE /*!< Select tamper to be enabled (mainly for legacy purposes) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
|
||||||
|
#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if RTC_BKP_NUMBER > 0U
|
||||||
|
#define RTC_BKP_DR1 0x00000001U
|
||||||
|
#define RTC_BKP_DR2 0x00000002U
|
||||||
|
#define RTC_BKP_DR3 0x00000003U
|
||||||
|
#define RTC_BKP_DR4 0x00000004U
|
||||||
|
#define RTC_BKP_DR5 0x00000005U
|
||||||
|
#define RTC_BKP_DR6 0x00000006U
|
||||||
|
#define RTC_BKP_DR7 0x00000007U
|
||||||
|
#define RTC_BKP_DR8 0x00000008U
|
||||||
|
#define RTC_BKP_DR9 0x00000009U
|
||||||
|
#define RTC_BKP_DR10 0x0000000AU
|
||||||
|
#endif /* RTC_BKP_NUMBER > 0 */
|
||||||
|
|
||||||
|
#if RTC_BKP_NUMBER > 10U
|
||||||
|
#define RTC_BKP_DR11 0x00000010U
|
||||||
|
#define RTC_BKP_DR12 0x00000011U
|
||||||
|
#define RTC_BKP_DR13 0x00000012U
|
||||||
|
#define RTC_BKP_DR14 0x00000013U
|
||||||
|
#define RTC_BKP_DR15 0x00000014U
|
||||||
|
#define RTC_BKP_DR16 0x00000015U
|
||||||
|
#define RTC_BKP_DR17 0x00000016U
|
||||||
|
#define RTC_BKP_DR18 0x00000017U
|
||||||
|
#define RTC_BKP_DR19 0x00000018U
|
||||||
|
#define RTC_BKP_DR20 0x00000019U
|
||||||
|
#define RTC_BKP_DR21 0x0000001AU
|
||||||
|
#define RTC_BKP_DR22 0x0000001BU
|
||||||
|
#define RTC_BKP_DR23 0x0000001CU
|
||||||
|
#define RTC_BKP_DR24 0x0000001DU
|
||||||
|
#define RTC_BKP_DR25 0x0000001EU
|
||||||
|
#define RTC_BKP_DR26 0x0000001FU
|
||||||
|
#define RTC_BKP_DR27 0x00000020U
|
||||||
|
#define RTC_BKP_DR28 0x00000021U
|
||||||
|
#define RTC_BKP_DR29 0x00000022U
|
||||||
|
#define RTC_BKP_DR30 0x00000023U
|
||||||
|
#define RTC_BKP_DR31 0x00000024U
|
||||||
|
#define RTC_BKP_DR32 0x00000025U
|
||||||
|
#define RTC_BKP_DR33 0x00000026U
|
||||||
|
#define RTC_BKP_DR34 0x00000027U
|
||||||
|
#define RTC_BKP_DR35 0x00000028U
|
||||||
|
#define RTC_BKP_DR36 0x00000029U
|
||||||
|
#define RTC_BKP_DR37 0x0000002AU
|
||||||
|
#define RTC_BKP_DR38 0x0000002BU
|
||||||
|
#define RTC_BKP_DR39 0x0000002CU
|
||||||
|
#define RTC_BKP_DR40 0x0000002DU
|
||||||
|
#define RTC_BKP_DR41 0x0000002EU
|
||||||
|
#define RTC_BKP_DR42 0x0000002FU
|
||||||
|
#endif /* RTC_BKP_NUMBER > 10 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the RTC Tamper interrupt.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_TAMP1: Tamper A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the RTC Tamper interrupt.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_TAMP1: Tamper A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_IT_TAMP1
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the selected RTC Tamper's flag status.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_FLAG_TAMP1F
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the selected RTC Tamper's flag status.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_IT_TAMP1
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the RTC Tamper's pending flags.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_FLAG_TAMP1F
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the RTC Second interrupt.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_SEC: Second A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the RTC Second interrupt.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_SEC: Second A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified RTC Second interrupt has occurred or not.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_IT_SEC: Second A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the selected RTC Second's flag status.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_FLAG_SEC
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the RTC Second's pending flags.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_FLAG_SEC
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the RTC Overflow interrupt.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_OW: Overflow A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the RTC Overflow interrupt.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_OW: Overflow A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified RTC Overflow interrupt has occurred or not.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_IT_OW: Overflow A interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the selected RTC Overflow's flag status.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_FLAG_OW
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the RTC Overflow's pending flags.
|
||||||
|
* @param __HANDLE__: specifies the RTC handle.
|
||||||
|
* @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg RTC_FLAG_OW
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup RTCEx_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* RTC Tamper functions *****************************************/
|
||||||
|
/** @addtogroup RTCEx_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
|
||||||
|
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||||
|
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* RTC Second functions *****************************************/
|
||||||
|
/** @addtogroup RTCEx_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc);
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc);
|
||||||
|
void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef* hrtc);
|
||||||
|
void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc);
|
||||||
|
void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Extension Control functions ************************************************/
|
||||||
|
/** @addtogroup RTCEx_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
|
||||||
|
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_RTC_EX_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,717 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_sd.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of SD HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_SD_H
|
||||||
|
#define __STM32F1xx_HAL_SD_H
|
||||||
|
|
||||||
|
#if defined(STM32F103xE) || defined(STM32F103xG)
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_sdmmc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD SD
|
||||||
|
* @brief SD HAL module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Exported_Types SD Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
|
||||||
|
HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
|
||||||
|
HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
|
||||||
|
HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
|
||||||
|
HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
|
||||||
|
HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receinving State */
|
||||||
|
HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
|
||||||
|
HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
|
||||||
|
}HAL_SD_StateTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_SD_CARD_READY = 0x00000001U, /*!< Card state is ready */
|
||||||
|
HAL_SD_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
|
||||||
|
HAL_SD_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
|
||||||
|
HAL_SD_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
|
||||||
|
HAL_SD_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
|
||||||
|
HAL_SD_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
|
||||||
|
HAL_SD_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
|
||||||
|
HAL_SD_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
|
||||||
|
HAL_SD_CARD_ERROR = 0x000000FFU /*!< Card response Error */
|
||||||
|
}HAL_SD_CardStateTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SD_InitTypeDef SDIO_InitTypeDef
|
||||||
|
#define SD_TypeDef SDIO_TypeDef
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SD Card Information Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t CardType; /*!< Specifies the card Type */
|
||||||
|
|
||||||
|
uint32_t CardVersion; /*!< Specifies the card version */
|
||||||
|
|
||||||
|
uint32_t Class; /*!< Specifies the class of the card class */
|
||||||
|
|
||||||
|
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
|
||||||
|
|
||||||
|
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
|
||||||
|
|
||||||
|
uint32_t BlockSize; /*!< Specifies one block size in bytes */
|
||||||
|
|
||||||
|
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
|
||||||
|
|
||||||
|
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
|
||||||
|
|
||||||
|
}HAL_SD_CardInfoTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SD handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
SD_TypeDef *Instance; /*!< SD registers base address */
|
||||||
|
|
||||||
|
SD_InitTypeDef Init; /*!< SD required parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< SD locking object */
|
||||||
|
|
||||||
|
uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
|
||||||
|
|
||||||
|
uint32_t TxXferSize; /*!< SD Tx Transfer size */
|
||||||
|
|
||||||
|
uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
|
||||||
|
|
||||||
|
uint32_t RxXferSize; /*!< SD Rx Transfer size */
|
||||||
|
|
||||||
|
__IO uint32_t Context; /*!< SD transfer context */
|
||||||
|
|
||||||
|
__IO HAL_SD_StateTypeDef State; /*!< SD card State */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
|
||||||
|
|
||||||
|
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
|
||||||
|
|
||||||
|
uint32_t CSD[4]; /*!< SD card specific data table */
|
||||||
|
|
||||||
|
uint32_t CID[4]; /*!< SD card identification number table */
|
||||||
|
|
||||||
|
}SD_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint8_t CSDStruct; /*!< CSD structure */
|
||||||
|
__IO uint8_t SysSpecVersion; /*!< System specification version */
|
||||||
|
__IO uint8_t Reserved1; /*!< Reserved */
|
||||||
|
__IO uint8_t TAAC; /*!< Data read access time 1 */
|
||||||
|
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
|
||||||
|
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
|
||||||
|
__IO uint16_t CardComdClasses; /*!< Card command classes */
|
||||||
|
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
|
||||||
|
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
|
||||||
|
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
|
||||||
|
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
|
||||||
|
__IO uint8_t DSRImpl; /*!< DSR implemented */
|
||||||
|
__IO uint8_t Reserved2; /*!< Reserved */
|
||||||
|
__IO uint32_t DeviceSize; /*!< Device Size */
|
||||||
|
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
|
||||||
|
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
|
||||||
|
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
|
||||||
|
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
|
||||||
|
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
|
||||||
|
__IO uint8_t EraseGrSize; /*!< Erase group size */
|
||||||
|
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
|
||||||
|
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
|
||||||
|
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
|
||||||
|
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
|
||||||
|
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
|
||||||
|
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
|
||||||
|
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
|
||||||
|
__IO uint8_t Reserved3; /*!< Reserved */
|
||||||
|
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
|
||||||
|
__IO uint8_t FileFormatGrouop; /*!< File format group */
|
||||||
|
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
|
||||||
|
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
|
||||||
|
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
|
||||||
|
__IO uint8_t FileFormat; /*!< File format */
|
||||||
|
__IO uint8_t ECC; /*!< ECC code */
|
||||||
|
__IO uint8_t CSD_CRC; /*!< CSD CRC */
|
||||||
|
__IO uint8_t Reserved4; /*!< Always 1 */
|
||||||
|
|
||||||
|
}HAL_SD_CardCSDTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
|
||||||
|
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
|
||||||
|
__IO uint32_t ProdName1; /*!< Product Name part1 */
|
||||||
|
__IO uint8_t ProdName2; /*!< Product Name part2 */
|
||||||
|
__IO uint8_t ProdRev; /*!< Product Revision */
|
||||||
|
__IO uint32_t ProdSN; /*!< Product Serial Number */
|
||||||
|
__IO uint8_t Reserved1; /*!< Reserved1 */
|
||||||
|
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
|
||||||
|
__IO uint8_t CID_CRC; /*!< CID CRC */
|
||||||
|
__IO uint8_t Reserved2; /*!< Always 1 */
|
||||||
|
|
||||||
|
}HAL_SD_CardCIDTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
|
||||||
|
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
|
||||||
|
__IO uint16_t CardType; /*!< Carries information about card type */
|
||||||
|
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
|
||||||
|
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
|
||||||
|
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
|
||||||
|
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
|
||||||
|
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
|
||||||
|
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
|
||||||
|
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
|
||||||
|
|
||||||
|
}HAL_SD_CardStatusTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Exported_Constants Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
|
||||||
|
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
|
||||||
|
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
|
||||||
|
#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
|
||||||
|
#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
|
||||||
|
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
|
||||||
|
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
|
||||||
|
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
|
||||||
|
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
|
||||||
|
number of transferred bytes does not match the block length */
|
||||||
|
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
|
||||||
|
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
|
||||||
|
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
|
||||||
|
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
|
||||||
|
command or if there was an attempt to access a locked card */
|
||||||
|
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
|
||||||
|
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
|
||||||
|
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
|
||||||
|
#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
|
||||||
|
#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
|
||||||
|
#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
|
||||||
|
#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
|
||||||
|
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
|
||||||
|
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
|
||||||
|
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
|
||||||
|
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
|
||||||
|
of erase sequence command was received */
|
||||||
|
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
|
||||||
|
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
|
||||||
|
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
|
||||||
|
#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
|
||||||
|
#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
|
||||||
|
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
|
||||||
|
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
|
||||||
|
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
|
||||||
|
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SD_CONTEXT_NONE 0x00000000U /*!< None */
|
||||||
|
#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
|
||||||
|
#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
|
||||||
|
#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
|
||||||
|
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
|
||||||
|
#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
|
||||||
|
#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CARD_SDSC 0x00000000U
|
||||||
|
#define CARD_SDHC_SDXC 0x00000001U
|
||||||
|
#define CARD_SECURED 0x00000003U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CARD_V1_X 0x00000000U
|
||||||
|
#define CARD_V2_X 0x00000001U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Exported_macros SD Exported Macros
|
||||||
|
* @brief macros to handle interrupts and specific clock configurations
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the SD device.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the SD device.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the SDMMC DMA transfer.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the SDMMC DMA transfer.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the SD device interrupt.
|
||||||
|
* @param __HANDLE__: SD Handle
|
||||||
|
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||||
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||||
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the SD device interrupt.
|
||||||
|
* @param __HANDLE__: SD Handle
|
||||||
|
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||||
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||||
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified SD flag is set or not.
|
||||||
|
* @param __HANDLE__: SD Handle
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||||
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||||
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||||
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||||
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||||
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
||||||
|
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
||||||
|
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
||||||
|
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||||
|
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||||
|
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
||||||
|
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
||||||
|
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
||||||
|
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
||||||
|
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
||||||
|
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
||||||
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||||
|
* @retval The new state of SD FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the SD's pending flags.
|
||||||
|
* @param __HANDLE__: SD Handle
|
||||||
|
* @param __FLAG__: specifies the flag to clear.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||||
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||||
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||||
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||||
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||||
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified SD interrupt has occurred or not.
|
||||||
|
* @param __HANDLE__: SD Handle
|
||||||
|
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||||
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||||
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @retval The new state of SD IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the SD's interrupt pending bits.
|
||||||
|
* @param __HANDLE__: SD Handle
|
||||||
|
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Exported_Functions SD Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
|
||||||
|
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
|
||||||
|
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
|
||||||
|
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
|
||||||
|
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Blocking mode: Polling */
|
||||||
|
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
|
||||||
|
/* Non-Blocking mode: IT */
|
||||||
|
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||||
|
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||||
|
/* Non-Blocking mode: DMA */
|
||||||
|
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||||
|
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
|
||||||
|
|
||||||
|
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
|
||||||
|
|
||||||
|
/* Callback in non blocking modes (DMA) */
|
||||||
|
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
|
||||||
|
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
|
||||||
|
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
|
||||||
|
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
|
||||||
|
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
|
||||||
|
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
|
||||||
|
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
|
||||||
|
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
|
||||||
|
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
|
||||||
|
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
|
||||||
|
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Private_Types SD Private Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private defines -----------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Private_Defines SD Private Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Private_Variables SD Private Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Private_Constants SD Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Private_Macros SD Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions prototypes ----------------------------------------------*/
|
||||||
|
/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/** @defgroup SD_Private_Functions SD Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32F103xE || STM32F103xG */
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_SD_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,685 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_smartcard.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of SMARTCARD HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_SMARTCARD_H
|
||||||
|
#define __STM32F1xx_HAL_SMARTCARD_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SMARTCARD
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SMARTCARD Init Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
|
||||||
|
The baud rate is computed using the following formula:
|
||||||
|
- IntegerDivider = ((PCLKx) / (16 * (hsmartcard->Init.BaudRate)))
|
||||||
|
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||||
|
|
||||||
|
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||||
|
This parameter can be a value of @ref SMARTCARD_Word_Length */
|
||||||
|
|
||||||
|
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||||
|
This parameter can be a value of @ref SMARTCARD_Stop_Bits */
|
||||||
|
|
||||||
|
uint32_t Parity; /*!< Specifies the parity mode.
|
||||||
|
This parameter can be a value of @ref SMARTCARD_Parity
|
||||||
|
@note When parity is enabled, the computed parity is inserted
|
||||||
|
at the MSB position of the transmitted data (9th bit when
|
||||||
|
the word length is set to 9 data bits; 8th bit when the
|
||||||
|
word length is set to 8 data bits).*/
|
||||||
|
|
||||||
|
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SMARTCARD_Mode */
|
||||||
|
|
||||||
|
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
||||||
|
This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
|
||||||
|
|
||||||
|
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||||
|
This parameter can be a value of @ref SMARTCARD_Clock_Phase */
|
||||||
|
|
||||||
|
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||||
|
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||||
|
This parameter can be a value of @ref SMARTCARD_Last_Bit */
|
||||||
|
|
||||||
|
uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
|
||||||
|
to provide the smartcard clock. The value given in the register (5 significant bits)
|
||||||
|
is multiplied by 2 to give the division factor of the source clock frequency.
|
||||||
|
This parameter can be a value of @ref SMARTCARD_Prescaler */
|
||||||
|
|
||||||
|
uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
|
||||||
|
|
||||||
|
uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state
|
||||||
|
This parameter can be a value of @ref SMARTCARD_NACK_State */
|
||||||
|
}SMARTCARD_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL SMARTCARD State structures definition
|
||||||
|
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
|
||||||
|
* - gState contains SMARTCARD state information related to global Handle management
|
||||||
|
* and also information related to Tx operations.
|
||||||
|
* gState value coding follow below described bitmap :
|
||||||
|
* b7-b6 Error information
|
||||||
|
* 00 : No Error
|
||||||
|
* 01 : (Not Used)
|
||||||
|
* 10 : Timeout
|
||||||
|
* 11 : Error
|
||||||
|
* b5 IP initilisation status
|
||||||
|
* 0 : Reset (IP not initialized)
|
||||||
|
* 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
|
||||||
|
* b4-b3 (not used)
|
||||||
|
* xx : Should be set to 00
|
||||||
|
* b2 Intrinsic process state
|
||||||
|
* 0 : Ready
|
||||||
|
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||||
|
* b1 (not used)
|
||||||
|
* x : Should be set to 0
|
||||||
|
* b0 Tx state
|
||||||
|
* 0 : Ready (no Tx operation ongoing)
|
||||||
|
* 1 : Busy (Tx operation ongoing)
|
||||||
|
* - RxState contains information related to Rx operations.
|
||||||
|
* RxState value coding follow below described bitmap :
|
||||||
|
* b7-b6 (not used)
|
||||||
|
* xx : Should be set to 00
|
||||||
|
* b5 IP initilisation status
|
||||||
|
* 0 : Reset (IP not initialized)
|
||||||
|
* 1 : Init done (IP not initialized)
|
||||||
|
* b4-b2 (not used)
|
||||||
|
* xxx : Should be set to 000
|
||||||
|
* b1 Rx state
|
||||||
|
* 0 : Ready (no Rx operation ongoing)
|
||||||
|
* 1 : Busy (Rx operation ongoing)
|
||||||
|
* b0 (not used)
|
||||||
|
* x : Should be set to 0.
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
|
||||||
|
Value is allowed for gState and RxState */
|
||||||
|
HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
|
||||||
|
Value is allowed for gState and RxState */
|
||||||
|
HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
|
||||||
|
Value is allowed for gState only */
|
||||||
|
HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
|
||||||
|
Value is allowed for gState only */
|
||||||
|
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
|
||||||
|
Value is allowed for RxState only */
|
||||||
|
HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
|
||||||
|
Not to be used for neither gState nor RxState.
|
||||||
|
Value is result of combination (Or) between gState and RxState values */
|
||||||
|
HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
|
||||||
|
Value is allowed for gState only */
|
||||||
|
HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
|
||||||
|
Value is allowed for gState only */
|
||||||
|
}HAL_SMARTCARD_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SMARTCARD handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||||
|
|
||||||
|
SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
|
||||||
|
|
||||||
|
uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
|
||||||
|
|
||||||
|
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
|
||||||
|
|
||||||
|
uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
|
||||||
|
|
||||||
|
uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||||
|
|
||||||
|
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
|
||||||
|
and also related to Tx operations.
|
||||||
|
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||||
|
|
||||||
|
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
|
||||||
|
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
|
||||||
|
}SMARTCARD_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
|
||||||
|
#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
|
||||||
|
#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
|
||||||
|
#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
|
||||||
|
#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< OverRun error */
|
||||||
|
#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
|
||||||
|
#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||||
|
#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_Mode SMARTCARD Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||||
|
#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||||
|
#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_POLARITY_LOW 0x00000000U
|
||||||
|
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_PHASE_1EDGE 0x00000000U
|
||||||
|
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
|
||||||
|
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
|
||||||
|
#define SMARTCARD_NACK_DISABLE 0x00000000U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
|
||||||
|
#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
|
||||||
|
#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SmartCard_Flags SMARTCARD Flags
|
||||||
|
* Elements values convention: 0xXXXX
|
||||||
|
* - 0xXXXX : Flag mask in the SR register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
|
||||||
|
#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
|
||||||
|
#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
|
||||||
|
#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
|
||||||
|
#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)
|
||||||
|
#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)
|
||||||
|
#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)
|
||||||
|
#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
|
||||||
|
* Elements values convention: 0xY000XXXX
|
||||||
|
* - XXXX : Interrupt mask in the XX register
|
||||||
|
* - Y : Interrupt source register (2bits)
|
||||||
|
* - 01: CR1 register
|
||||||
|
* - 11: CR3 register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
|
||||||
|
#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
|
||||||
|
#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
|
||||||
|
#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
|
||||||
|
#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
|
||||||
|
#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset SMARTCARD handle gstate & RxState
|
||||||
|
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||||
|
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
|
||||||
|
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Flush the Smartcard DR register
|
||||||
|
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
|
||||||
|
|
||||||
|
/** @brief Check whether the specified Smartcard flag is set or not.
|
||||||
|
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
|
||||||
|
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
|
||||||
|
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
|
||||||
|
* @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
|
||||||
|
* @arg SMARTCARD_FLAG_ORE: OverRun Error flag
|
||||||
|
* @arg SMARTCARD_FLAG_NE: Noise Error flag
|
||||||
|
* @arg SMARTCARD_FLAG_FE: Framing Error flag
|
||||||
|
* @arg SMARTCARD_FLAG_PE: Parity Error flag
|
||||||
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clear the specified Smartcard pending flags.
|
||||||
|
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
|
||||||
|
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
|
||||||
|
*
|
||||||
|
* @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
|
||||||
|
* error) flags are cleared by software sequence: a read operation to
|
||||||
|
* USART_SR register followed by a read operation to USART_DR register.
|
||||||
|
* @note RXNE flag can be also cleared by a read to the USART_DR register.
|
||||||
|
* @note TC flag can be also cleared by software sequence: a read operation to
|
||||||
|
* USART_SR register followed by a write operation to USART_DR register.
|
||||||
|
* @note TXE flag is cleared only by a write to the USART_DR register.
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clear the SMARTCARD PE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||||
|
UNUSED(tmpreg); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Clear the SMARTCARD FE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Clear the SMARTCARD NE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Clear the SMARTCARD ORE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Clear the SMARTCARD IDLE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Enable the specified SmartCard interrupt.
|
||||||
|
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||||
|
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||||
|
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||||
|
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
|
||||||
|
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||||
|
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error)
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
|
||||||
|
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
|
||||||
|
|
||||||
|
/** @brief Disable the specified SmartCard interrupt.
|
||||||
|
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||||
|
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||||
|
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||||
|
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
|
||||||
|
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||||
|
* @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error)
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
|
||||||
|
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
|
||||||
|
|
||||||
|
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
|
||||||
|
* @param __HANDLE__: specifies the SmartCard Handle.
|
||||||
|
* @param __IT__: specifies the SMARTCARD interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
|
||||||
|
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
|
||||||
|
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
|
||||||
|
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
|
||||||
|
* @arg SMARTCARD_IT_ERR: Error interrupt
|
||||||
|
* @arg SMARTCARD_IT_PE: Parity Error interrupt
|
||||||
|
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
|
||||||
|
|
||||||
|
/** @brief Enable the USART associated to the SMARTCARD Handle
|
||||||
|
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||||
|
|
||||||
|
/** @brief Disable the USART associated to the SMARTCARD Handle
|
||||||
|
* @param __HANDLE__: specifies the SMARTCARD Handle.
|
||||||
|
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||||
|
|
||||||
|
/** @brief Macros to enable the SmartCard DMA request.
|
||||||
|
* @param __HANDLE__: specifies the SmartCard Handle.
|
||||||
|
* @param __REQUEST__: specifies the SmartCard DMA request.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
|
||||||
|
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
|
||||||
|
|
||||||
|
/** @brief Macros to disable the SmartCard DMA request.
|
||||||
|
* @param __HANDLE__: specifies the SmartCard Handle.
|
||||||
|
* @param __REQUEST__: specifies the SmartCard DMA request.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
|
||||||
|
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
|
||||||
|
*/
|
||||||
|
#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup SMARTCARD_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SMARTCARD_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SMARTCARD_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* IO operation functions *******************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
|
||||||
|
/* Transfer Abort functions */
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
|
||||||
|
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SMARTCARD_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral State functions **************************************************/
|
||||||
|
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief SMARTCARD interruptions flag mask
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define SMARTCARD_IT_MASK 0x0000FFFFU
|
||||||
|
|
||||||
|
#define SMARTCARD_CR1_REG_INDEX 1U
|
||||||
|
#define SMARTCARD_CR3_REG_INDEX 3U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros --------------------------------------------------------*/
|
||||||
|
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
|
||||||
|
#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
|
||||||
|
((STOPBITS) == SMARTCARD_STOPBITS_1_5))
|
||||||
|
#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
|
||||||
|
((PARITY) == SMARTCARD_PARITY_ODD))
|
||||||
|
#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
|
||||||
|
#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
|
||||||
|
#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
|
||||||
|
#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
|
||||||
|
((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
|
||||||
|
#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
|
||||||
|
((NACK) == SMARTCARD_NACK_DISABLE))
|
||||||
|
#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
|
||||||
|
|
||||||
|
#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
|
||||||
|
#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
|
||||||
|
#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
|
||||||
|
/* SMARTCARD BRR = mantissa + overflow + fraction
|
||||||
|
= (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
|
||||||
|
#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
|
||||||
|
(SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
|
||||||
|
(SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_SMARTCARD_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,589 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_spi.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of SPI HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_SPI_H
|
||||||
|
#define __STM32F1xx_HAL_SPI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SPI_Exported_Types SPI Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SPI Configuration Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
||||||
|
This parameter can be a value of @ref SPI_Mode */
|
||||||
|
|
||||||
|
uint32_t Direction; /*!< Specifies the SPI Directional mode state.
|
||||||
|
This parameter can be a value of @ref SPI_Direction */
|
||||||
|
|
||||||
|
uint32_t DataSize; /*!< Specifies the SPI data size.
|
||||||
|
This parameter can be a value of @ref SPI_Data_Size */
|
||||||
|
|
||||||
|
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
||||||
|
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||||
|
|
||||||
|
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
||||||
|
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||||
|
|
||||||
|
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
||||||
|
hardware (NSS pin) or by software using the SSI bit.
|
||||||
|
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||||
|
|
||||||
|
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||||
|
used to configure the transmit and receive SCK clock.
|
||||||
|
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||||
|
@note The communication clock is derived from the master
|
||||||
|
clock. The slave clock does not need to be set. */
|
||||||
|
|
||||||
|
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||||
|
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||||
|
|
||||||
|
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
||||||
|
This parameter can be a value of @ref SPI_TI_mode */
|
||||||
|
|
||||||
|
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
||||||
|
This parameter can be a value of @ref SPI_CRC_Calculation */
|
||||||
|
|
||||||
|
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
|
||||||
|
}SPI_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL SPI State structure definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
|
||||||
|
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||||
|
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||||
|
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
||||||
|
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
||||||
|
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
|
||||||
|
HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
|
||||||
|
}HAL_SPI_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SPI handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct __SPI_HandleTypeDef
|
||||||
|
{
|
||||||
|
SPI_TypeDef *Instance; /*!< SPI registers base address */
|
||||||
|
|
||||||
|
SPI_InitTypeDef Init; /*!< SPI communication parameters */
|
||||||
|
|
||||||
|
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
||||||
|
|
||||||
|
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
|
||||||
|
|
||||||
|
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
|
||||||
|
|
||||||
|
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
|
||||||
|
|
||||||
|
void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */
|
||||||
|
|
||||||
|
void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||||
|
|
||||||
|
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< SPI Error code */
|
||||||
|
|
||||||
|
}SPI_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Error_Code SPI Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
|
||||||
|
#define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
|
||||||
|
#define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
|
||||||
|
#define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
|
||||||
|
#define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
|
||||||
|
#define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||||
|
#define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Mode SPI Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_MODE_SLAVE 0x00000000U
|
||||||
|
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Direction SPI Direction Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_DIRECTION_2LINES 0x00000000U
|
||||||
|
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
|
||||||
|
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Data_Size SPI Data Size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_DATASIZE_8BIT 0x00000000U
|
||||||
|
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_POLARITY_LOW 0x00000000U
|
||||||
|
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_PHASE_1EDGE 0x00000000U
|
||||||
|
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_NSS_SOFT SPI_CR1_SSM
|
||||||
|
#define SPI_NSS_HARD_INPUT 0x00000000U
|
||||||
|
#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_BAUDRATEPRESCALER_2 0x00000000U
|
||||||
|
#define SPI_BAUDRATEPRESCALER_4 SPI_CR1_BR_0
|
||||||
|
#define SPI_BAUDRATEPRESCALER_8 SPI_CR1_BR_1
|
||||||
|
#define SPI_BAUDRATEPRESCALER_16 (uint32_t)(SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
||||||
|
#define SPI_BAUDRATEPRESCALER_32 SPI_CR1_BR_2
|
||||||
|
#define SPI_BAUDRATEPRESCALER_64 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_0)
|
||||||
|
#define SPI_BAUDRATEPRESCALER_128 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1)
|
||||||
|
#define SPI_BAUDRATEPRESCALER_256 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_FIRSTBIT_MSB 0x00000000U
|
||||||
|
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_TI_mode SPI TI Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_TIMODE_DISABLE 0x00000000U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_CRCCALCULATION_DISABLE 0x00000000U
|
||||||
|
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_IT_TXE SPI_CR2_TXEIE
|
||||||
|
#define SPI_IT_RXNE SPI_CR2_RXNEIE
|
||||||
|
#define SPI_IT_ERR SPI_CR2_ERRIE
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Flags_definition SPI Flags Definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
|
||||||
|
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
|
||||||
|
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
|
||||||
|
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
|
||||||
|
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
|
||||||
|
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset SPI handle state.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
||||||
|
|
||||||
|
/** @brief Enable the specified SPI interrupts.
|
||||||
|
* @param __HANDLE__: specifies the SPI handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @param __INTERRUPT__: specifies the interrupt source to enable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||||
|
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||||
|
* @arg SPI_IT_ERR: Error interrupt enable
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
|
||||||
|
|
||||||
|
/** @brief Disable the specified SPI interrupts.
|
||||||
|
* @param __HANDLE__: specifies the SPI handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @param __INTERRUPT__: specifies the interrupt source to disable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||||
|
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||||
|
* @arg SPI_IT_ERR: Error interrupt enable
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
|
||||||
|
|
||||||
|
/** @brief Check whether the specified SPI interrupt source is enabled or not.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @param __INTERRUPT__: specifies the SPI interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
||||||
|
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
||||||
|
* @arg SPI_IT_ERR: Error interrupt enable
|
||||||
|
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||||
|
|
||||||
|
/** @brief Check whether the specified SPI flag is set or not.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
||||||
|
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
||||||
|
* @arg SPI_FLAG_CRCERR: CRC error flag
|
||||||
|
* @arg SPI_FLAG_MODF: Mode fault flag
|
||||||
|
* @arg SPI_FLAG_OVR: Overrun flag
|
||||||
|
* @arg SPI_FLAG_BSY: Busy flag
|
||||||
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clear the SPI CRCERR pending flag.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
|
||||||
|
|
||||||
|
/** @brief Clear the SPI MODF pending flag.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
__IO uint32_t tmpreg_modf = 0x00U; \
|
||||||
|
tmpreg_modf = (__HANDLE__)->Instance->SR; \
|
||||||
|
(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
|
||||||
|
UNUSED(tmpreg_modf); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Clear the SPI OVR pending flag.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
__IO uint32_t tmpreg_ovr = 0x00U; \
|
||||||
|
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
||||||
|
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
||||||
|
UNUSED(tmpreg_ovr); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
|
||||||
|
/** @brief Enable the SPI peripheral.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
|
||||||
|
|
||||||
|
/** @brief Disable the SPI peripheral.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup SPI_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* I/O operation functions *****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
|
||||||
|
/* Transfer Abort functions */
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
|
||||||
|
|
||||||
|
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
|
||||||
|
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral State and Error functions ***************************************/
|
||||||
|
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
||||||
|
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup SPI_Private_Constants SPI Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
|
||||||
|
#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SPI_Private_Macros SPI Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Set the SPI transmit-only mode.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
|
||||||
|
|
||||||
|
/** @brief Set the SPI receive-only mode.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
|
||||||
|
|
||||||
|
/** @brief Reset the CRC calculation of the SPI.
|
||||||
|
* @param __HANDLE__: specifies the SPI Handle.
|
||||||
|
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
|
||||||
|
(__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
|
||||||
|
|
||||||
|
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
|
||||||
|
((MODE) == SPI_MODE_MASTER))
|
||||||
|
|
||||||
|
#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
|
||||||
|
((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
|
||||||
|
((MODE) == SPI_DIRECTION_1LINE))
|
||||||
|
|
||||||
|
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
|
||||||
|
|
||||||
|
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
|
||||||
|
((MODE) == SPI_DIRECTION_1LINE))
|
||||||
|
|
||||||
|
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
|
||||||
|
((DATASIZE) == SPI_DATASIZE_8BIT))
|
||||||
|
|
||||||
|
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
|
||||||
|
((CPOL) == SPI_POLARITY_HIGH))
|
||||||
|
|
||||||
|
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
|
||||||
|
((CPHA) == SPI_PHASE_2EDGE))
|
||||||
|
|
||||||
|
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
|
||||||
|
((NSS) == SPI_NSS_HARD_INPUT) || \
|
||||||
|
((NSS) == SPI_NSS_HARD_OUTPUT))
|
||||||
|
|
||||||
|
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
|
||||||
|
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
|
||||||
|
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
|
||||||
|
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
|
||||||
|
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
|
||||||
|
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
|
||||||
|
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
|
||||||
|
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
|
||||||
|
|
||||||
|
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
|
||||||
|
((BIT) == SPI_FIRSTBIT_LSB))
|
||||||
|
|
||||||
|
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
|
||||||
|
((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
|
||||||
|
|
||||||
|
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/** @defgroup SPI_Private_Functions SPI Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_SPI_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,201 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_sram.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of SRAM HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_SRAM_H
|
||||||
|
#define __STM32F1xx_HAL_SRAM_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_fsmc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
|
||||||
|
|
||||||
|
/** @addtogroup SRAM
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported typedef ----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Types SRAM Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief HAL SRAM State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
|
||||||
|
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
|
||||||
|
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
|
||||||
|
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
|
||||||
|
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
|
||||||
|
|
||||||
|
}HAL_SRAM_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
|
||||||
|
|
||||||
|
FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< SRAM locking object */
|
||||||
|
|
||||||
|
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
|
||||||
|
|
||||||
|
}SRAM_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset SRAM handle state
|
||||||
|
* @param __HANDLE__: SRAM handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
|
||||||
|
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
|
||||||
|
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
|
||||||
|
|
||||||
|
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
|
||||||
|
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* I/O operation functions *****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* SRAM Control functions ******************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SRAM_Exported_Functions_Group4
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* SRAM State functions *********************************************************/
|
||||||
|
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_SRAM_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,595 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_usart.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of USART HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_USART_H
|
||||||
|
#define __STM32F1xx_HAL_USART_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USART
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup USART_Exported_Types USART Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief USART Init Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
|
||||||
|
The baud rate is computed using the following formula:
|
||||||
|
- IntegerDivider = ((PCLKx) / (16 * (husart->Init.BaudRate)))
|
||||||
|
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||||
|
|
||||||
|
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||||
|
This parameter can be a value of @ref USART_Word_Length */
|
||||||
|
|
||||||
|
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||||
|
This parameter can be a value of @ref USART_Stop_Bits */
|
||||||
|
|
||||||
|
uint32_t Parity; /*!< Specifies the parity mode.
|
||||||
|
This parameter can be a value of @ref USART_Parity
|
||||||
|
@note When parity is enabled, the computed parity is inserted
|
||||||
|
at the MSB position of the transmitted data (9th bit when
|
||||||
|
the word length is set to 9 data bits; 8th bit when the
|
||||||
|
word length is set to 8 data bits). */
|
||||||
|
|
||||||
|
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Mode */
|
||||||
|
|
||||||
|
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
|
||||||
|
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||||
|
|
||||||
|
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||||
|
This parameter can be a value of @ref USART_Clock_Phase */
|
||||||
|
|
||||||
|
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||||
|
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||||
|
This parameter can be a value of @ref USART_Last_Bit */
|
||||||
|
}USART_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet initialized */
|
||||||
|
HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||||
|
HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
||||||
|
HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
|
||||||
|
HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||||
|
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
|
||||||
|
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||||
|
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
|
||||||
|
}HAL_USART_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief USART handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||||
|
|
||||||
|
USART_InitTypeDef Init; /*!< Usart communication parameters */
|
||||||
|
|
||||||
|
uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
|
||||||
|
|
||||||
|
uint16_t TxXferSize; /*!< Usart Tx Transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
|
||||||
|
|
||||||
|
uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
|
||||||
|
|
||||||
|
uint16_t RxXferSize; /*!< Usart Rx Transfer size */
|
||||||
|
|
||||||
|
__IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
|
||||||
|
|
||||||
|
DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||||
|
|
||||||
|
__IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< USART Error code */
|
||||||
|
}USART_HandleTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup USART_Exported_Constants USART Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Error_Code USART Error Code
|
||||||
|
* @brief USART Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
|
||||||
|
#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
|
||||||
|
#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
|
||||||
|
#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
|
||||||
|
#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
|
||||||
|
#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Word_Length USART Word Length
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_WORDLENGTH_8B 0x00000000U
|
||||||
|
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_STOPBITS_1 0x00000000U
|
||||||
|
#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
|
||||||
|
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
|
||||||
|
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Parity USART Parity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_PARITY_NONE 0x00000000U
|
||||||
|
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||||
|
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Mode USART Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
|
||||||
|
#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
|
||||||
|
#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Clock USART Clock
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_CLOCK_DISABLE 0x00000000U
|
||||||
|
#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Clock_Polarity USART Clock Polarity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_POLARITY_LOW 0x00000000U
|
||||||
|
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Clock_Phase USART Clock Phase
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_PHASE_1EDGE 0x00000000U
|
||||||
|
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Last_Bit USART Last Bit
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_LASTBIT_DISABLE 0x00000000U
|
||||||
|
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_NACK_State USART NACK State
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
|
||||||
|
#define USART_NACK_DISABLE 0x00000000U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Flags USART Flags
|
||||||
|
* Elements values convention: 0xXXXX
|
||||||
|
* - 0xXXXX : Flag mask in the SR register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
|
||||||
|
#define USART_FLAG_TC ((uint32_t)USART_SR_TC)
|
||||||
|
#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
|
||||||
|
#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
|
||||||
|
#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
|
||||||
|
#define USART_FLAG_NE ((uint32_t)USART_SR_NE)
|
||||||
|
#define USART_FLAG_FE ((uint32_t)USART_SR_FE)
|
||||||
|
#define USART_FLAG_PE ((uint32_t)USART_SR_PE)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
|
||||||
|
* Elements values convention: 0xY000XXXX
|
||||||
|
* - XXXX : Interrupt mask in the XX register
|
||||||
|
* - Y : Interrupt source register (2bits)
|
||||||
|
* - 01: CR1 register
|
||||||
|
* - 10: CR2 register
|
||||||
|
* - 11: CR3 register
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
|
||||||
|
#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
|
||||||
|
#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
|
||||||
|
#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
|
||||||
|
#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
|
||||||
|
|
||||||
|
#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
|
||||||
|
|
||||||
|
#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
|
||||||
|
#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup USART_Exported_Macros USART Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset USART handle state
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
|
||||||
|
|
||||||
|
/** @brief Checks whether the specified USART flag is set or not.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg USART_FLAG_TXE: Transmit data register empty flag
|
||||||
|
* @arg USART_FLAG_TC: Transmission Complete flag
|
||||||
|
* @arg USART_FLAG_RXNE: Receive data register not empty flag
|
||||||
|
* @arg USART_FLAG_IDLE: Idle Line detection flag
|
||||||
|
* @arg USART_FLAG_ORE: OverRun Error flag
|
||||||
|
* @arg USART_FLAG_NE: Noise Error flag
|
||||||
|
* @arg USART_FLAG_FE: Framing Error flag
|
||||||
|
* @arg USART_FLAG_PE: Parity Error flag
|
||||||
|
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clears the specified USART pending flags.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
* @param __FLAG__: specifies the flag to check.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg USART_FLAG_TC: Transmission Complete flag.
|
||||||
|
* @arg USART_FLAG_RXNE: Receive data register not empty flag.
|
||||||
|
*
|
||||||
|
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||||
|
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||||
|
* sequence: a read operation to USART_SR register followed by a read
|
||||||
|
* operation to USART_DR register.
|
||||||
|
* @note RXNE flag can be also cleared by a read to the USART_DR register.
|
||||||
|
* @note TC flag can be also cleared by software sequence: a read operation to
|
||||||
|
* USART_SR register followed by a write operation to USART_DR register
|
||||||
|
* @note TXE flag is cleared only by a write to the USART_DR register
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Clear the USART PE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
__IO uint32_t tmpreg = 0x00U; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->SR; \
|
||||||
|
tmpreg = (__HANDLE__)->Instance->DR; \
|
||||||
|
UNUSED(tmpreg); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Clear the USART FE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Clear the USART NE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Clear the USART ORE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Clear the USART IDLE pending flag.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
|
||||||
|
|
||||||
|
/** @brief Enable the specified USART interrupts.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
* @param __INTERRUPT__: specifies the USART interrupt source to enable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
|
||||||
|
* @arg USART_IT_TC: Transmission complete interrupt
|
||||||
|
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
|
||||||
|
* @arg USART_IT_IDLE: Idle line detection interrupt
|
||||||
|
* @arg USART_IT_PE: Parity Error interrupt
|
||||||
|
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
|
||||||
|
(((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
|
||||||
|
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
|
||||||
|
|
||||||
|
/** @brief Disable the specified USART interrupts.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
* @param __INTERRUPT__: specifies the USART interrupt source to disable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
|
||||||
|
* @arg USART_IT_TC: Transmission complete interrupt
|
||||||
|
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
|
||||||
|
* @arg USART_IT_IDLE: Idle line detection interrupt
|
||||||
|
* @arg USART_IT_PE: Parity Error interrupt
|
||||||
|
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
|
||||||
|
(((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
|
||||||
|
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
|
||||||
|
|
||||||
|
/** @brief Checks whether the specified USART interrupt has occurred or not.
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
* @param __IT__: specifies the USART interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
|
||||||
|
* @arg USART_IT_TC: Transmission complete interrupt
|
||||||
|
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
|
||||||
|
* @arg USART_IT_IDLE: Idle line detection interrupt
|
||||||
|
* @arg USART_IT_ERR: Error interrupt
|
||||||
|
* @arg USART_IT_PE: Parity Error interrupt
|
||||||
|
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
|
||||||
|
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
|
||||||
|
|
||||||
|
/** @brief Enable USART
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
|
||||||
|
|
||||||
|
/** @brief Disable USART
|
||||||
|
* @param __HANDLE__: specifies the USART Handle.
|
||||||
|
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
|
||||||
|
*/
|
||||||
|
#define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup USART_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USART_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
|
||||||
|
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
|
||||||
|
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
|
||||||
|
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USART_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* IO operation functions *******************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
|
||||||
|
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
|
||||||
|
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
|
||||||
|
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
|
||||||
|
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
|
||||||
|
/* Transfer Abort functions */
|
||||||
|
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
|
||||||
|
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
|
||||||
|
|
||||||
|
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
|
||||||
|
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
|
||||||
|
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
|
||||||
|
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
|
||||||
|
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
|
||||||
|
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
|
||||||
|
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
|
||||||
|
void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USART_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral State functions ************************************************/
|
||||||
|
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
|
||||||
|
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup USART_Private_Constants USART Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @brief USART interruptions flag mask
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USART_IT_MASK 0x0000FFFFU
|
||||||
|
|
||||||
|
#define USART_CR1_REG_INDEX 1U
|
||||||
|
#define USART_CR2_REG_INDEX 2U
|
||||||
|
#define USART_CR3_REG_INDEX 3U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup USART_Private_Macros USART Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
|
||||||
|
((NACK) == USART_NACK_DISABLE))
|
||||||
|
|
||||||
|
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
|
||||||
|
((LASTBIT) == USART_LASTBIT_ENABLE))
|
||||||
|
|
||||||
|
#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
|
||||||
|
|
||||||
|
#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
|
||||||
|
|
||||||
|
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
|
||||||
|
((CLOCK) == USART_CLOCK_ENABLE))
|
||||||
|
|
||||||
|
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
|
||||||
|
((LENGTH) == USART_WORDLENGTH_9B))
|
||||||
|
|
||||||
|
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
|
||||||
|
((STOPBITS) == USART_STOPBITS_0_5) || \
|
||||||
|
((STOPBITS) == USART_STOPBITS_1_5) || \
|
||||||
|
((STOPBITS) == USART_STOPBITS_2))
|
||||||
|
|
||||||
|
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
|
||||||
|
((PARITY) == USART_PARITY_EVEN) || \
|
||||||
|
((PARITY) == USART_PARITY_ODD))
|
||||||
|
|
||||||
|
#define IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))
|
||||||
|
|
||||||
|
#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
|
||||||
|
|
||||||
|
#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
|
||||||
|
|
||||||
|
#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
|
||||||
|
|
||||||
|
#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
|
||||||
|
|
||||||
|
#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/** @defgroup USART_Private_Functions USART Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_USART_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,283 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_wwdg.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of WWDG HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_HAL_WWDG_H
|
||||||
|
#define __STM32F1xx_HAL_WWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WWDG
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup WWDG_Exported_Types WWDG Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief WWDG Init structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
|
||||||
|
This parameter can be a value of @ref WWDG_Prescaler */
|
||||||
|
|
||||||
|
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
|
||||||
|
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
|
||||||
|
|
||||||
|
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
|
||||||
|
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
|
||||||
|
|
||||||
|
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
|
||||||
|
This parameter can be a value of @ref WWDG_EWI_Mode */
|
||||||
|
|
||||||
|
}WWDG_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief WWDG handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
WWDG_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
|
||||||
|
|
||||||
|
}WWDG_HandleTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Flag_definition WWDG Flag definition
|
||||||
|
* @brief WWDG Flag definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Prescaler WWDG Prescaler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||||
|
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||||
|
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||||
|
#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */
|
||||||
|
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Private_Macros WWDG Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
|
||||||
|
((__PRESCALER__) == WWDG_PRESCALER_2) || \
|
||||||
|
((__PRESCALER__) == WWDG_PRESCALER_4) || \
|
||||||
|
((__PRESCALER__) == WWDG_PRESCALER_8))
|
||||||
|
|
||||||
|
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
|
||||||
|
|
||||||
|
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
|
||||||
|
|
||||||
|
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
|
||||||
|
((__MODE__) == WWDG_EWI_DISABLE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported macros ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the WWDG peripheral.
|
||||||
|
* @param __HANDLE__: WWDG handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the WWDG early wakeup interrupt.
|
||||||
|
* @param __HANDLE__: WWDG handle
|
||||||
|
* @param __INTERRUPT__ specifies the interrupt to enable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg WWDG_IT_EWI: Early wakeup interrupt
|
||||||
|
* @note Once enabled this interrupt cannot be disabled except by a system reset.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the selected WWDG interrupt has occurred or not.
|
||||||
|
* @param __HANDLE__ WWDG handle
|
||||||
|
* @param __INTERRUPT__ specifies the it to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
|
||||||
|
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
|
||||||
|
|
||||||
|
/** @brief Clear the WWDG's interrupt pending bits
|
||||||
|
* bits to clear the selected interrupt pending bits.
|
||||||
|
* @param __HANDLE__: WWDG handle
|
||||||
|
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||||
|
*/
|
||||||
|
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified WWDG flag is set or not.
|
||||||
|
* @param __HANDLE__ WWDG handle
|
||||||
|
* @param __FLAG__ specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||||
|
* @retval The new state of WWDG_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the WWDG's pending flags.
|
||||||
|
* @param __HANDLE__: WWDG handle
|
||||||
|
* @param __FLAG__: specifies the flag to clear.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
|
||||||
|
|
||||||
|
/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
|
||||||
|
* @param __HANDLE__: WWDG Handle.
|
||||||
|
* @param __INTERRUPT__: specifies the WWDG interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
|
||||||
|
* @retval state of __INTERRUPT__ (TRUE or FALSE).
|
||||||
|
*/
|
||||||
|
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup WWDG_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WWDG_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization/de-initialization functions **********************************/
|
||||||
|
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
|
||||||
|
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WWDG_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* I/O operation functions ******************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
|
||||||
|
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
|
||||||
|
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_HAL_WWDG_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
3950
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h
Normal file
3950
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h
Normal file
File diff suppressed because it is too large
Load Diff
1033
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h
Normal file
1033
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,658 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_cortex.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of CORTEX LL module.
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
The LL CORTEX driver contains a set of generic APIs that can be
|
||||||
|
used by user:
|
||||||
|
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
|
||||||
|
functions
|
||||||
|
(+) Low power mode configuration (SCB register of Cortex-MCU)
|
||||||
|
(+) MPU API to configure and enable regions
|
||||||
|
(MPU services provided only on some devices)
|
||||||
|
(+) API to access to MCU info (CPUID register)
|
||||||
|
(+) API to enable fault handler (SHCSR accesses)
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_LL_CORTEX_H
|
||||||
|
#define __STM32F1xx_LL_CORTEX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL CORTEX
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
|
||||||
|
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
|
||||||
|
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
|
||||||
|
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if __MPU_PRESENT
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
|
||||||
|
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
|
||||||
|
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
|
||||||
|
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
|
||||||
|
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
|
||||||
|
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
|
||||||
|
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
|
||||||
|
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
|
||||||
|
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
|
||||||
|
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
|
||||||
|
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
|
||||||
|
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
|
||||||
|
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
|
||||||
|
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
|
||||||
|
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
|
||||||
|
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
|
||||||
|
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
|
||||||
|
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
|
||||||
|
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
|
||||||
|
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
|
||||||
|
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
|
||||||
|
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
|
||||||
|
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
|
||||||
|
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* __MPU_PRESENT */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function checks if the Systick counter flag is active or not.
|
||||||
|
* @note It can be used in timeout function on application side.
|
||||||
|
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
|
||||||
|
{
|
||||||
|
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the SysTick clock source
|
||||||
|
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
|
||||||
|
* @param Source This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||||
|
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
|
||||||
|
{
|
||||||
|
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
|
||||||
|
{
|
||||||
|
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the SysTick clock source
|
||||||
|
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
|
||||||
|
* @retval Returned value can be one of the following values:
|
||||||
|
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
|
||||||
|
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
|
||||||
|
{
|
||||||
|
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable SysTick exception request
|
||||||
|
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
|
||||||
|
{
|
||||||
|
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable SysTick exception request
|
||||||
|
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
|
||||||
|
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
|
||||||
|
{
|
||||||
|
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Processor uses sleep as its low power mode
|
||||||
|
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_LPM_EnableSleep(void)
|
||||||
|
{
|
||||||
|
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||||
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Processor uses deep sleep as its low power mode
|
||||||
|
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
|
||||||
|
{
|
||||||
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||||
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
|
||||||
|
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
|
||||||
|
* empty main application.
|
||||||
|
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
|
||||||
|
{
|
||||||
|
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||||
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Do not sleep when returning to Thread mode.
|
||||||
|
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
|
||||||
|
{
|
||||||
|
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||||
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
|
||||||
|
* processor.
|
||||||
|
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
|
||||||
|
{
|
||||||
|
/* Set SEVEONPEND bit of Cortex System Control Register */
|
||||||
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
|
||||||
|
* excluded
|
||||||
|
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
|
||||||
|
{
|
||||||
|
/* Clear SEVEONPEND bit of Cortex System Control Register */
|
||||||
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable a fault in System handler control register (SHCSR)
|
||||||
|
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
|
||||||
|
* @param Fault This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_HANDLER_FAULT_USG
|
||||||
|
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||||
|
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
|
||||||
|
{
|
||||||
|
/* Enable the system handler fault */
|
||||||
|
SET_BIT(SCB->SHCSR, Fault);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable a fault in System handler control register (SHCSR)
|
||||||
|
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
|
||||||
|
* @param Fault This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_HANDLER_FAULT_USG
|
||||||
|
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||||
|
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
|
||||||
|
{
|
||||||
|
/* Disable the system handler fault */
|
||||||
|
CLEAR_BIT(SCB->SHCSR, Fault);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Implementer code
|
||||||
|
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
|
||||||
|
* @retval Value should be equal to 0x41 for ARM
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Variant number (The r value in the rnpn product revision identifier)
|
||||||
|
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
|
||||||
|
* @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Constant number
|
||||||
|
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
|
||||||
|
* @retval Value should be equal to 0xF for Cortex-M3 devices
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Part number
|
||||||
|
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
|
||||||
|
* @retval Value should be equal to 0xC23 for Cortex-M3
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
|
||||||
|
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
|
||||||
|
* @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if __MPU_PRESENT
|
||||||
|
/** @defgroup CORTEX_LL_EF_MPU MPU
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable MPU with input options
|
||||||
|
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
|
||||||
|
* @param Options This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
|
||||||
|
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
|
||||||
|
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
|
||||||
|
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
|
||||||
|
{
|
||||||
|
/* Enable the MPU*/
|
||||||
|
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
|
||||||
|
/* Ensure MPU settings take effects */
|
||||||
|
__DSB();
|
||||||
|
/* Sequence instruction fetches using update settings */
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable MPU
|
||||||
|
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
/* Make sure outstanding transfers are done */
|
||||||
|
__DMB();
|
||||||
|
/* Disable MPU*/
|
||||||
|
WRITE_REG(MPU->CTRL, 0U);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if MPU is enabled or not
|
||||||
|
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
|
||||||
|
{
|
||||||
|
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable a MPU region
|
||||||
|
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
|
||||||
|
* @param Region This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
|
||||||
|
{
|
||||||
|
/* Set Region number */
|
||||||
|
WRITE_REG(MPU->RNR, Region);
|
||||||
|
/* Enable the MPU region */
|
||||||
|
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure and enable a region
|
||||||
|
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
|
||||||
|
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
|
||||||
|
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
|
||||||
|
* MPU_RASR XN LL_MPU_ConfigRegion\n
|
||||||
|
* MPU_RASR AP LL_MPU_ConfigRegion\n
|
||||||
|
* MPU_RASR S LL_MPU_ConfigRegion\n
|
||||||
|
* MPU_RASR C LL_MPU_ConfigRegion\n
|
||||||
|
* MPU_RASR B LL_MPU_ConfigRegion\n
|
||||||
|
* MPU_RASR SIZE LL_MPU_ConfigRegion
|
||||||
|
* @param Region This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||||
|
* @param Address Value of region base address
|
||||||
|
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
|
||||||
|
* @param Attributes This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
|
||||||
|
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
|
||||||
|
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
|
||||||
|
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
|
||||||
|
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
|
||||||
|
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
|
||||||
|
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
|
||||||
|
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
|
||||||
|
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
|
||||||
|
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
|
||||||
|
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
|
||||||
|
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
|
||||||
|
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
|
||||||
|
{
|
||||||
|
/* Set Region number */
|
||||||
|
WRITE_REG(MPU->RNR, Region);
|
||||||
|
/* Set base address */
|
||||||
|
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
|
||||||
|
/* Configure MPU */
|
||||||
|
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable a region
|
||||||
|
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
|
||||||
|
* MPU_RASR ENABLE LL_MPU_DisableRegion
|
||||||
|
* @param Region This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||||
|
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
|
||||||
|
{
|
||||||
|
/* Set Region number */
|
||||||
|
WRITE_REG(MPU->RNR, Region);
|
||||||
|
/* Disable the MPU region */
|
||||||
|
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* __MPU_PRESENT */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_LL_CORTEX_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,212 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_crc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of CRC LL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_LL_CRC_H
|
||||||
|
#define __STM32F1xx_LL_CRC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(CRC)
|
||||||
|
|
||||||
|
/** @defgroup CRC_LL CRC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write a value in CRC register
|
||||||
|
* @param __INSTANCE__ CRC Instance
|
||||||
|
* @param __REG__ Register to be written
|
||||||
|
* @param __VALUE__ Value to be written in the register
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read a value in CRC register
|
||||||
|
* @param __INSTANCE__ CRC Instance
|
||||||
|
* @param __REG__ Register to be read
|
||||||
|
* @retval Register value
|
||||||
|
*/
|
||||||
|
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset the CRC calculation unit.
|
||||||
|
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
|
||||||
|
* @param CRCx CRC Instance
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
|
||||||
|
{
|
||||||
|
WRITE_REG(CRCx->CR, CRC_CR_RESET);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_LL_EF_Data_Management Data_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write given 32-bit data to the CRC calculator
|
||||||
|
* @rmtoll DR DR LL_CRC_FeedData32
|
||||||
|
* @param CRCx CRC Instance
|
||||||
|
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
|
||||||
|
{
|
||||||
|
WRITE_REG(CRCx->DR, InData);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return current CRC calculation result. 32 bits value is returned.
|
||||||
|
* @rmtoll DR DR LL_CRC_ReadData32
|
||||||
|
* @param CRCx CRC Instance
|
||||||
|
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_REG(CRCx->DR));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return data stored in the Independent Data(IDR) register.
|
||||||
|
* @note This register can be used as a temporary storage location for one byte.
|
||||||
|
* @rmtoll IDR IDR LL_CRC_Read_IDR
|
||||||
|
* @param CRCx CRC Instance
|
||||||
|
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_REG(CRCx->IDR));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Store data in the Independent Data(IDR) register.
|
||||||
|
* @note This register can be used as a temporary storage location for one byte.
|
||||||
|
* @rmtoll IDR IDR LL_CRC_Write_IDR
|
||||||
|
* @param CRCx CRC Instance
|
||||||
|
* @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
|
||||||
|
{
|
||||||
|
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* defined(CRC) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_LL_CRC_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
1349
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dac.h
Normal file
1349
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dac.h
Normal file
File diff suppressed because it is too large
Load Diff
1978
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h
Normal file
1978
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,906 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_exti.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of EXTI LL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_LL_EXTI_H
|
||||||
|
#define __STM32F1xx_LL_EXTI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (EXTI)
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL EXTI
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private Macros ------------------------------------------------------------*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /*USE_FULL_LL_DRIVER*/
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
|
||||||
|
uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
|
||||||
|
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
|
||||||
|
|
||||||
|
FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
|
||||||
|
This parameter can be set either to ENABLE or DISABLE */
|
||||||
|
|
||||||
|
uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
|
||||||
|
This parameter can be a value of @ref EXTI_LL_EC_MODE. */
|
||||||
|
|
||||||
|
uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||||
|
This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
|
||||||
|
} LL_EXTI_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /*USE_FULL_LL_DRIVER*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL_EC_LINE LINE
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
|
||||||
|
#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
|
||||||
|
#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
|
||||||
|
#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
|
||||||
|
#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
|
||||||
|
#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
|
||||||
|
#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
|
||||||
|
#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
|
||||||
|
#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
|
||||||
|
#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
|
||||||
|
#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
|
||||||
|
#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
|
||||||
|
#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
|
||||||
|
#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
|
||||||
|
#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
|
||||||
|
#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
|
||||||
|
#if defined(EXTI_IMR_IM16)
|
||||||
|
#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
|
||||||
|
#endif
|
||||||
|
#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
|
||||||
|
#if defined(EXTI_IMR_IM18)
|
||||||
|
#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM19)
|
||||||
|
#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM20)
|
||||||
|
#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM21)
|
||||||
|
#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM22)
|
||||||
|
#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM23)
|
||||||
|
#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM24)
|
||||||
|
#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM25)
|
||||||
|
#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM26)
|
||||||
|
#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM27)
|
||||||
|
#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM28)
|
||||||
|
#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM29)
|
||||||
|
#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM30)
|
||||||
|
#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
|
||||||
|
#endif
|
||||||
|
#if defined(EXTI_IMR_IM31)
|
||||||
|
#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
|
||||||
|
#endif
|
||||||
|
#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
|
||||||
|
|
||||||
|
|
||||||
|
#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
|
||||||
|
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
|
||||||
|
#endif /*USE_FULL_LL_DRIVER*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL_EC_MODE Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */
|
||||||
|
#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */
|
||||||
|
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */
|
||||||
|
#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */
|
||||||
|
#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */
|
||||||
|
#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#endif /*USE_FULL_LL_DRIVER*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write a value in EXTI register
|
||||||
|
* @param __REG__ Register to be written
|
||||||
|
* @param __VALUE__ Value to be written in the register
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read a value in EXTI register
|
||||||
|
* @param __REG__ Register to be read
|
||||||
|
* @retval Register value
|
||||||
|
*/
|
||||||
|
#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
|
||||||
|
* @note The reset value for the direct or internal lines (see RM)
|
||||||
|
* is set to 1 in order to enable the interrupt by default.
|
||||||
|
* Bits are set automatically at Power on.
|
||||||
|
* @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
|
||||||
|
* @param ExtiLine This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_17
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
SET_BIT(EXTI->IMR, ExtiLine);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
|
||||||
|
* @note The reset value for the direct or internal lines (see RM)
|
||||||
|
* is set to 1 in order to enable the interrupt by default.
|
||||||
|
* Bits are set automatically at Power on.
|
||||||
|
* @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
|
||||||
|
* @param ExtiLine This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_17
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(EXTI->IMR, ExtiLine);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
|
||||||
|
* @note The reset value for the direct or internal lines (see RM)
|
||||||
|
* is set to 1 in order to enable the interrupt by default.
|
||||||
|
* Bits are set automatically at Power on.
|
||||||
|
* @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
|
||||||
|
* @param ExtiLine This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_17
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
|
||||||
|
* @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
|
||||||
|
* @param ExtiLine This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_17
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
SET_BIT(EXTI->EMR, ExtiLine);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
|
||||||
|
* @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
|
||||||
|
* @param ExtiLine This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_17
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(EXTI->EMR, ExtiLine);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
|
||||||
|
* @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
|
||||||
|
* @param ExtiLine This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_17
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
||||||
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||||
|
* generated on these lines. If a rising edge on a configurable interrupt
|
||||||
|
* line occurs during a write operation in the EXTI_RTSR register, the
|
||||||
|
* pending bit is not set.
|
||||||
|
* Rising and falling edge triggers can be set for
|
||||||
|
* the same interrupt line. In this case, both generate a trigger
|
||||||
|
* condition.
|
||||||
|
* @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
SET_BIT(EXTI->RTSR, ExtiLine);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
||||||
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||||
|
* generated on these lines. If a rising edge on a configurable interrupt
|
||||||
|
* line occurs during a write operation in the EXTI_RTSR register, the
|
||||||
|
* pending bit is not set.
|
||||||
|
* Rising and falling edge triggers can be set for
|
||||||
|
* the same interrupt line. In this case, both generate a trigger
|
||||||
|
* condition.
|
||||||
|
* @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(EXTI->RTSR, ExtiLine);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
|
||||||
|
* @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
||||||
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||||
|
* generated on these lines. If a falling edge on a configurable interrupt
|
||||||
|
* line occurs during a write operation in the EXTI_FTSR register, the
|
||||||
|
* pending bit is not set.
|
||||||
|
* Rising and falling edge triggers can be set for
|
||||||
|
* the same interrupt line. In this case, both generate a trigger
|
||||||
|
* condition.
|
||||||
|
* @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
SET_BIT(EXTI->FTSR, ExtiLine);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
||||||
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
||||||
|
* generated on these lines. If a Falling edge on a configurable interrupt
|
||||||
|
* line occurs during a write operation in the EXTI_FTSR register, the
|
||||||
|
* pending bit is not set.
|
||||||
|
* Rising and falling edge triggers can be set for the same interrupt line.
|
||||||
|
* In this case, both generate a trigger condition.
|
||||||
|
* @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(EXTI->FTSR, ExtiLine);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
|
||||||
|
* @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
|
||||||
|
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
|
||||||
|
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
|
||||||
|
* resulting in an interrupt request generation.
|
||||||
|
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
|
||||||
|
* register (by writing a 1 into the bit)
|
||||||
|
* @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
SET_BIT(EXTI->SWIER, ExtiLine);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
|
||||||
|
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||||
|
* line. This bit is cleared by writing a 1 to the bit.
|
||||||
|
* @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read ExtLine Combination Flag for Lines in range 0 to 31
|
||||||
|
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||||
|
* line. This bit is cleared by writing a 1 to the bit.
|
||||||
|
* @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval @note This bit is set when the selected edge event arrives on the interrupt
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear ExtLine Flags for Lines in range 0 to 31
|
||||||
|
* @note This bit is set when the selected edge event arrives on the interrupt
|
||||||
|
* line. This bit is cleared by writing a 1 to the bit.
|
||||||
|
* @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
|
||||||
|
* @param ExtiLine This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_EXTI_LINE_0
|
||||||
|
* @arg @ref LL_EXTI_LINE_1
|
||||||
|
* @arg @ref LL_EXTI_LINE_2
|
||||||
|
* @arg @ref LL_EXTI_LINE_3
|
||||||
|
* @arg @ref LL_EXTI_LINE_4
|
||||||
|
* @arg @ref LL_EXTI_LINE_5
|
||||||
|
* @arg @ref LL_EXTI_LINE_6
|
||||||
|
* @arg @ref LL_EXTI_LINE_7
|
||||||
|
* @arg @ref LL_EXTI_LINE_8
|
||||||
|
* @arg @ref LL_EXTI_LINE_9
|
||||||
|
* @arg @ref LL_EXTI_LINE_10
|
||||||
|
* @arg @ref LL_EXTI_LINE_11
|
||||||
|
* @arg @ref LL_EXTI_LINE_12
|
||||||
|
* @arg @ref LL_EXTI_LINE_13
|
||||||
|
* @arg @ref LL_EXTI_LINE_14
|
||||||
|
* @arg @ref LL_EXTI_LINE_15
|
||||||
|
* @arg @ref LL_EXTI_LINE_16
|
||||||
|
* @arg @ref LL_EXTI_LINE_18
|
||||||
|
* @arg @ref LL_EXTI_LINE_19
|
||||||
|
* @note Please check each device line mapping for EXTI Line availability
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
WRITE_REG(EXTI->PR, ExtiLine);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
||||||
|
uint32_t LL_EXTI_DeInit(void);
|
||||||
|
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* EXTI */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_LL_EXTI_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
1081
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h
Normal file
1081
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_fsmc.h
Normal file
File diff suppressed because it is too large
Load Diff
2381
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h
Normal file
2381
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h
Normal file
File diff suppressed because it is too large
Load Diff
1802
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_i2c.h
Normal file
1802
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_i2c.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,329 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_iwdg.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of IWDG LL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_LL_IWDG_H
|
||||||
|
#define __STM32F1xx_LL_IWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(IWDG)
|
||||||
|
|
||||||
|
/** @defgroup IWDG_LL IWDG
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
|
||||||
|
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
|
||||||
|
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
|
||||||
|
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
|
||||||
|
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
|
||||||
|
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
|
||||||
|
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
|
||||||
|
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
|
||||||
|
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
|
||||||
|
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
|
||||||
|
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
|
||||||
|
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write a value in IWDG register
|
||||||
|
* @param __INSTANCE__ IWDG Instance
|
||||||
|
* @param __REG__ Register to be written
|
||||||
|
* @param __VALUE__ Value to be written in the register
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read a value in IWDG register
|
||||||
|
* @param __INSTANCE__ IWDG Instance
|
||||||
|
* @param __REG__ Register to be read
|
||||||
|
* @retval Register value
|
||||||
|
*/
|
||||||
|
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup IWDG_LL_EF_Configuration Configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start the Independent Watchdog
|
||||||
|
* @note Except if the hardware watchdog option is selected
|
||||||
|
* @rmtoll KR KEY LL_IWDG_Enable
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
|
||||||
|
{
|
||||||
|
WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reloads IWDG counter with value defined in the reload register
|
||||||
|
* @rmtoll KR KEY LL_IWDG_ReloadCounter
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
|
||||||
|
{
|
||||||
|
WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||||
|
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||||
|
{
|
||||||
|
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
|
||||||
|
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
|
||||||
|
{
|
||||||
|
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Select the prescaler of the IWDG
|
||||||
|
* @rmtoll PR PR LL_IWDG_SetPrescaler
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @param Prescaler This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_4
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_8
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_16
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_32
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_64
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_128
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_256
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
|
||||||
|
{
|
||||||
|
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the selected prescaler of the IWDG
|
||||||
|
* @rmtoll PR PR LL_IWDG_GetPrescaler
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @retval Returned value can be one of the following values:
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_4
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_8
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_16
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_32
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_64
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_128
|
||||||
|
* @arg @ref LL_IWDG_PRESCALER_256
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_REG(IWDGx->PR));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Specify the IWDG down-counter reload value
|
||||||
|
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
|
||||||
|
{
|
||||||
|
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the specified IWDG down-counter reload value
|
||||||
|
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_REG(IWDGx->RLR));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if flag Prescaler Value Update is set or not
|
||||||
|
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
|
||||||
|
{
|
||||||
|
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if flag Reload Value Update is set or not
|
||||||
|
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
|
||||||
|
{
|
||||||
|
return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
|
||||||
|
* @rmtoll SR PVU LL_IWDG_IsReady\n
|
||||||
|
* SR RVU LL_IWDG_IsReady
|
||||||
|
* @param IWDGx IWDG Instance
|
||||||
|
* @retval State of bits (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
|
||||||
|
{
|
||||||
|
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* IWDG) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_LL_IWDG_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,458 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_pwr.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of PWR LL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_LL_PWR_H
|
||||||
|
#define __STM32F1xx_LL_PWR_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(PWR)
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL PWR
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
|
||||||
|
* @brief Flags defines which can be used with LL_PWR_WriteReg function
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
|
||||||
|
#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
|
||||||
|
* @brief Flags defines which can be used with LL_PWR_ReadReg function
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
|
||||||
|
#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
|
||||||
|
#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
|
||||||
|
#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
|
||||||
|
#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
|
||||||
|
#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
|
||||||
|
#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
|
||||||
|
#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
|
||||||
|
#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
|
||||||
|
#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
|
||||||
|
#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
|
||||||
|
#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
|
||||||
|
#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
|
||||||
|
#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write a value in PWR register
|
||||||
|
* @param __REG__ Register to be written
|
||||||
|
* @param __VALUE__ Value to be written in the register
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read a value in PWR register
|
||||||
|
* @param __REG__ Register to be read
|
||||||
|
* @retval Register value
|
||||||
|
*/
|
||||||
|
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL_EF_Configuration Configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable access to the backup domain
|
||||||
|
* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
|
||||||
|
{
|
||||||
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable access to the backup domain
|
||||||
|
* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if the backup domain is enabled
|
||||||
|
* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
|
||||||
|
{
|
||||||
|
return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set voltage Regulator mode during deep sleep mode
|
||||||
|
* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
|
||||||
|
* @param RegulMode This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
||||||
|
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
|
||||||
|
{
|
||||||
|
MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get voltage Regulator mode during deep sleep mode
|
||||||
|
* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
|
||||||
|
* @retval Returned value can be one of the following values:
|
||||||
|
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
||||||
|
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Power Down mode when CPU enters deepsleep
|
||||||
|
* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
|
||||||
|
* @rmtoll CR LPDS LL_PWR_SetPowerMode
|
||||||
|
* @param PDMode This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
||||||
|
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
||||||
|
* @arg @ref LL_PWR_MODE_STANDBY
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
|
||||||
|
{
|
||||||
|
MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Power Down mode when CPU enters deepsleep
|
||||||
|
* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
|
||||||
|
* @rmtoll CR LPDS LL_PWR_GetPowerMode
|
||||||
|
* @retval Returned value can be one of the following values:
|
||||||
|
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
||||||
|
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
||||||
|
* @arg @ref LL_PWR_MODE_STANDBY
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure the voltage threshold detected by the Power Voltage Detector
|
||||||
|
* @rmtoll CR PLS LL_PWR_SetPVDLevel
|
||||||
|
* @param PVDLevel This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_0
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_1
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_2
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_3
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_4
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_5
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_6
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_7
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
|
||||||
|
{
|
||||||
|
MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the voltage threshold detection
|
||||||
|
* @rmtoll CR PLS LL_PWR_GetPVDLevel
|
||||||
|
* @retval Returned value can be one of the following values:
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_0
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_1
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_2
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_3
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_4
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_5
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_6
|
||||||
|
* @arg @ref LL_PWR_PVDLEVEL_7
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Power Voltage Detector
|
||||||
|
* @rmtoll CR PVDE LL_PWR_EnablePVD
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_EnablePVD(void)
|
||||||
|
{
|
||||||
|
SET_BIT(PWR->CR, PWR_CR_PVDE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Power Voltage Detector
|
||||||
|
* @rmtoll CR PVDE LL_PWR_DisablePVD
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_DisablePVD(void)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if Power Voltage Detector is enabled
|
||||||
|
* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
|
||||||
|
{
|
||||||
|
return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the WakeUp PINx functionality
|
||||||
|
* @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
|
||||||
|
* @param WakeUpPin This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
|
||||||
|
{
|
||||||
|
SET_BIT(PWR->CSR, WakeUpPin);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the WakeUp PINx functionality
|
||||||
|
* @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
|
||||||
|
* @param WakeUpPin This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(PWR->CSR, WakeUpPin);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if the WakeUp PINx functionality is enabled
|
||||||
|
* @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
|
||||||
|
* @param WakeUpPin This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_PWR_WAKEUP_PIN1
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
|
||||||
|
{
|
||||||
|
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Wake-up Flag
|
||||||
|
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
|
||||||
|
{
|
||||||
|
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Standby Flag
|
||||||
|
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
|
||||||
|
{
|
||||||
|
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Indicate whether VDD voltage is below the selected PVD threshold
|
||||||
|
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
|
||||||
|
{
|
||||||
|
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Standby Flag
|
||||||
|
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
|
||||||
|
{
|
||||||
|
SET_BIT(PWR->CR, PWR_CR_CSBF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Wake-up Flags
|
||||||
|
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
|
||||||
|
{
|
||||||
|
SET_BIT(PWR->CR, PWR_CR_CWUF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
/** @defgroup PWR_LL_EF_Init De-initialization function
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_PWR_DeInit(void);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* defined(PWR) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_LL_PWR_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
2309
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h
Normal file
2309
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h
Normal file
File diff suppressed because it is too large
Load Diff
1021
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h
Normal file
1021
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
1922
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h
Normal file
1922
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,592 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_system.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of SYSTEM LL module.
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
The LL SYSTEM driver contains a set of generic APIs that can be
|
||||||
|
used by user:
|
||||||
|
(+) Some of the FLASH features need to be handled in the SYSTEM file.
|
||||||
|
(+) Access to DBGCMU registers
|
||||||
|
(+) Access to SYSCFG registers
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_LL_SYSTEM_H
|
||||||
|
#define __STM32F1xx_LL_SYSTEM_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (FLASH) || defined (DBGMCU)
|
||||||
|
|
||||||
|
/** @defgroup SYSTEM_LL SYSTEM
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
|
||||||
|
#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
|
||||||
|
#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
|
||||||
|
#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
|
||||||
|
#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM5_STOP)
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM5_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM6_STOP)
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM6_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM7_STOP)
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM7_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM12_STOP)
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM12_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM13_STOP)
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM13_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM14_STOP)
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM14_STOP */
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
|
||||||
|
#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
|
||||||
|
#if defined(DBGMCU_CR_DBG_CAN1_STOP)
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_CAN2_STOP)
|
||||||
|
#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_CAN2_STOP */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM8_STOP)
|
||||||
|
#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM9_STOP)
|
||||||
|
#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM9_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM10_STOP)
|
||||||
|
#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM10_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM11_STOP)
|
||||||
|
#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM11_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM15_STOP)
|
||||||
|
#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM15_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM16_STOP)
|
||||||
|
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM16_STOP */
|
||||||
|
#if defined(DBGMCU_CR_DBG_TIM17_STOP)
|
||||||
|
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
|
||||||
|
#endif /* DBGMCU_CR_DBG_TIM17_STOP */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined(FLASH_ACR_LATENCY)
|
||||||
|
#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
|
||||||
|
#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
|
||||||
|
#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
|
||||||
|
#else
|
||||||
|
#endif /* FLASH_ACR_LATENCY */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the device identifier
|
||||||
|
* @note For Low Density devices, the device ID is 0x412
|
||||||
|
* @note For Medium Density devices, the device ID is 0x410
|
||||||
|
* @note For High Density devices, the device ID is 0x414
|
||||||
|
* @note For XL Density devices, the device ID is 0x430
|
||||||
|
* @note For Connectivity Line devices, the device ID is 0x418
|
||||||
|
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
|
||||||
|
* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the device revision identifier
|
||||||
|
* @note This field indicates the revision of the device.
|
||||||
|
For example, it is read as revA -> 0x1000,for Low Density devices
|
||||||
|
For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
|
||||||
|
For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
|
||||||
|
For example, it is read as revA or 1 -> 0x1003,for XL Density devices
|
||||||
|
For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
|
||||||
|
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
|
||||||
|
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the Debug Module during SLEEP mode
|
||||||
|
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
|
||||||
|
{
|
||||||
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the Debug Module during SLEEP mode
|
||||||
|
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the Debug Module during STOP mode
|
||||||
|
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
|
||||||
|
{
|
||||||
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the Debug Module during STOP mode
|
||||||
|
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the Debug Module during STANDBY mode
|
||||||
|
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
|
||||||
|
{
|
||||||
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the Debug Module during STANDBY mode
|
||||||
|
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Trace pin assignment control
|
||||||
|
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
|
||||||
|
* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
|
||||||
|
* @param PinAssignment This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_NONE
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
|
||||||
|
{
|
||||||
|
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Trace pin assignment control
|
||||||
|
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
|
||||||
|
* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
|
||||||
|
* @retval Returned value can be one of the following values:
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_NONE
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
|
||||||
|
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Freeze APB1 peripherals (group1 peripherals)
|
||||||
|
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
|
||||||
|
* @param Periphs This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
|
||||||
|
*
|
||||||
|
* (*) value not defined in all devices.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
|
||||||
|
{
|
||||||
|
SET_BIT(DBGMCU->CR, Periphs);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Unfreeze APB1 peripherals (group1 peripherals)
|
||||||
|
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
|
||||||
|
* @param Periphs This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
|
||||||
|
*
|
||||||
|
* (*) value not defined in all devices.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(DBGMCU->CR, Periphs);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Freeze APB2 peripherals
|
||||||
|
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
|
||||||
|
* @param Periphs This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
|
||||||
|
*
|
||||||
|
* (*) value not defined in all devices.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
|
||||||
|
{
|
||||||
|
SET_BIT(DBGMCU->CR, Periphs);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Unfreeze APB2 peripherals
|
||||||
|
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
|
||||||
|
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
|
||||||
|
* @param Periphs This parameter can be a combination of the following values:
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
|
||||||
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
|
||||||
|
*
|
||||||
|
* (*) value not defined in all devices.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(DBGMCU->CR, Periphs);
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(FLASH_ACR_LATENCY)
|
||||||
|
/** @defgroup SYSTEM_LL_EF_FLASH FLASH
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set FLASH Latency
|
||||||
|
* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
|
||||||
|
* @param Latency This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_FLASH_LATENCY_0
|
||||||
|
* @arg @ref LL_FLASH_LATENCY_1
|
||||||
|
* @arg @ref LL_FLASH_LATENCY_2
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
|
||||||
|
{
|
||||||
|
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get FLASH Latency
|
||||||
|
* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
|
||||||
|
* @retval Returned value can be one of the following values:
|
||||||
|
* @arg @ref LL_FLASH_LATENCY_0
|
||||||
|
* @arg @ref LL_FLASH_LATENCY_1
|
||||||
|
* @arg @ref LL_FLASH_LATENCY_2
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Prefetch
|
||||||
|
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
|
||||||
|
{
|
||||||
|
SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Prefetch
|
||||||
|
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if Prefetch buffer is enabled
|
||||||
|
* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
|
||||||
|
{
|
||||||
|
return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* FLASH_ACR_LATENCY */
|
||||||
|
/**
|
||||||
|
* @brief Enable Flash Half Cycle Access
|
||||||
|
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
|
||||||
|
{
|
||||||
|
SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Flash Half Cycle Access
|
||||||
|
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if Flash Half Cycle Access is enabled or not
|
||||||
|
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
|
||||||
|
{
|
||||||
|
return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* defined (FLASH) || defined (DBGMCU) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_LL_SYSTEM_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
3837
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
Normal file
3837
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,616 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_usb.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of USB Low Layer HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_LL_USB_H
|
||||||
|
#define __STM32F1xx_LL_USB_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F102x6) || defined(STM32F102xB) || \
|
||||||
|
defined(STM32F103x6) || defined(STM32F103xB) || \
|
||||||
|
defined(STM32F103xE) || defined(STM32F103xG) || \
|
||||||
|
defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USB_LL
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup USB_LL_Exported_Types USB Low Layer Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief USB Mode definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
USB_DEVICE_MODE = 0,
|
||||||
|
USB_HOST_MODE = 1,
|
||||||
|
USB_DRD_MODE = 2
|
||||||
|
}USB_ModeTypeDef;
|
||||||
|
|
||||||
|
#if defined (USB_OTG_FS)
|
||||||
|
/**
|
||||||
|
* @brief URB States definition
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
URB_IDLE = 0,
|
||||||
|
URB_DONE,
|
||||||
|
URB_NOTREADY,
|
||||||
|
URB_NYET,
|
||||||
|
URB_ERROR,
|
||||||
|
URB_STALL
|
||||||
|
}USB_OTG_URBStateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Host channel States definition
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
HC_IDLE = 0,
|
||||||
|
HC_XFRC,
|
||||||
|
HC_HALTED,
|
||||||
|
HC_NAK,
|
||||||
|
HC_NYET,
|
||||||
|
HC_STALL,
|
||||||
|
HC_XACTERR,
|
||||||
|
HC_BBLERR,
|
||||||
|
HC_DATATGLERR
|
||||||
|
}USB_OTG_HCStateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief USB OTG Initialization Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t dev_endpoints; /*!< Device Endpoints number.
|
||||||
|
This parameter depends on the used USB core.
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
|
uint32_t Host_channels; /*!< Host Channels number.
|
||||||
|
This parameter Depends on the used USB core.
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
|
uint32_t speed; /*!< USB Core speed.
|
||||||
|
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||||
|
|
||||||
|
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
|
||||||
|
This parameter can be any value of @ref USB_EP0_MPS_ */
|
||||||
|
|
||||||
|
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||||
|
|
||||||
|
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
|
||||||
|
|
||||||
|
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
|
||||||
|
|
||||||
|
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
|
||||||
|
}USB_OTG_CfgTypeDef;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t num; /*!< Endpoint number
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
|
uint8_t is_in; /*!< Endpoint direction
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint8_t is_stall; /*!< Endpoint stall condition
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint8_t type; /*!< Endpoint type
|
||||||
|
This parameter can be any value of @ref USB_EP_Type_ */
|
||||||
|
|
||||||
|
uint8_t data_pid_start; /*!< Initial data PID
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint8_t even_odd_frame; /*!< IFrame parity
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint16_t tx_fifo_num; /*!< Transmission FIFO number
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
|
uint32_t maxpacket; /*!< Endpoint Max packet size
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||||
|
|
||||||
|
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
|
||||||
|
|
||||||
|
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
|
||||||
|
|
||||||
|
uint32_t xfer_len; /*!< Current transfer length */
|
||||||
|
|
||||||
|
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
||||||
|
}USB_OTG_EPTypeDef;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t dev_addr ; /*!< USB device address.
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
|
||||||
|
|
||||||
|
uint8_t ch_num; /*!< Host channel number.
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
|
uint8_t ep_num; /*!< Endpoint number.
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
|
uint8_t ep_is_in; /*!< Endpoint direction
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint8_t speed; /*!< USB Host speed.
|
||||||
|
This parameter can be any value of @ref USB_Core_Speed_ */
|
||||||
|
|
||||||
|
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
|
||||||
|
|
||||||
|
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
|
||||||
|
|
||||||
|
uint8_t ep_type; /*!< Endpoint Type.
|
||||||
|
This parameter can be any value of @ref USB_EP_Type_ */
|
||||||
|
|
||||||
|
uint16_t max_packet; /*!< Endpoint Max packet size.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||||
|
|
||||||
|
uint8_t data_pid; /*!< Initial data PID.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
|
||||||
|
|
||||||
|
uint32_t xfer_len; /*!< Current transfer length. */
|
||||||
|
|
||||||
|
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
|
||||||
|
|
||||||
|
uint8_t toggle_in; /*!< IN transfer current toggle flag.
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint8_t toggle_out; /*!< OUT transfer current toggle flag
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
|
||||||
|
|
||||||
|
uint32_t ErrCnt; /*!< Host channel error count.*/
|
||||||
|
|
||||||
|
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
|
||||||
|
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
|
||||||
|
|
||||||
|
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
|
||||||
|
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
|
||||||
|
}USB_OTG_HCTypeDef;
|
||||||
|
#endif /* USB_OTG_FS */
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
/**
|
||||||
|
* @brief USB Initialization Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t dev_endpoints; /*!< Device Endpoints number.
|
||||||
|
This parameter depends on the used USB core.
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
|
uint32_t speed; /*!< USB Core speed.
|
||||||
|
This parameter can be any value of @ref USB_Core_Speed */
|
||||||
|
|
||||||
|
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
|
||||||
|
This parameter can be any value of @ref USB_EP0_MPS */
|
||||||
|
|
||||||
|
uint32_t phy_itface; /*!< Select the used PHY interface.
|
||||||
|
This parameter can be any value of @ref USB_Core_PHY */
|
||||||
|
|
||||||
|
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
|
||||||
|
|
||||||
|
uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
|
||||||
|
|
||||||
|
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
|
||||||
|
|
||||||
|
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
|
||||||
|
} USB_CfgTypeDef;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t num; /*!< Endpoint number
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
|
||||||
|
|
||||||
|
uint8_t is_in; /*!< Endpoint direction
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint8_t is_stall; /*!< Endpoint stall condition
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
|
||||||
|
|
||||||
|
uint8_t type; /*!< Endpoint type
|
||||||
|
This parameter can be any value of @ref USB_EP_Type */
|
||||||
|
|
||||||
|
uint16_t pmaadress; /*!< PMA Address
|
||||||
|
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||||
|
|
||||||
|
uint16_t pmaaddr0; /*!< PMA Address0
|
||||||
|
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||||
|
|
||||||
|
uint16_t pmaaddr1; /*!< PMA Address1
|
||||||
|
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
|
||||||
|
|
||||||
|
uint8_t doublebuffer; /*!< Double buffer enable
|
||||||
|
This parameter can be 0 or 1 */
|
||||||
|
|
||||||
|
uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
|
||||||
|
only by USB OTG FS peripheral
|
||||||
|
This parameter is added to ensure compatibility across USB peripherals */
|
||||||
|
|
||||||
|
uint32_t maxpacket; /*!< Endpoint Max packet size
|
||||||
|
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
|
||||||
|
|
||||||
|
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
|
||||||
|
|
||||||
|
uint32_t xfer_len; /*!< Current transfer length */
|
||||||
|
|
||||||
|
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
|
||||||
|
|
||||||
|
} USB_EPTypeDef;
|
||||||
|
#endif /* USB */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup USB_LL_Exported_Constants USB Low Layer Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB_OTG_FS)
|
||||||
|
/** @defgroup USB_LL_Core_Mode USB Low Layer Core Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USB_OTG_MODE_DEVICE 0
|
||||||
|
#define USB_OTG_MODE_HOST 1
|
||||||
|
#define USB_OTG_MODE_DRD 2
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USB_OTG_SPEED_LOW 2
|
||||||
|
#define USB_OTG_SPEED_FULL 3
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USB_OTG_ULPI_PHY 1
|
||||||
|
#define USB_OTG_EMBEDDED_PHY 2
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USB_OTG_FS_MAX_PACKET_SIZE 64
|
||||||
|
#define USB_OTG_MAX_EP0_SIZE 64
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1)
|
||||||
|
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1)
|
||||||
|
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DCFG_FRAME_INTERVAL_80 0
|
||||||
|
#define DCFG_FRAME_INTERVAL_85 1
|
||||||
|
#define DCFG_FRAME_INTERVAL_90 2
|
||||||
|
#define DCFG_FRAME_INTERVAL_95 3
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DEP0CTL_MPS_64 0
|
||||||
|
#define DEP0CTL_MPS_32 1
|
||||||
|
#define DEP0CTL_MPS_16 2
|
||||||
|
#define DEP0CTL_MPS_8 3
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EP_SPEED_LOW 0
|
||||||
|
#define EP_SPEED_FULL 1
|
||||||
|
#define EP_SPEED_HIGH 2
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EP_TYPE_CTRL 0
|
||||||
|
#define EP_TYPE_ISOC 1
|
||||||
|
#define EP_TYPE_BULK 2
|
||||||
|
#define EP_TYPE_INTR 3
|
||||||
|
#define EP_TYPE_MSK 3
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define STS_GOUT_NAK 1
|
||||||
|
#define STS_DATA_UPDT 2
|
||||||
|
#define STS_XFER_COMP 3
|
||||||
|
#define STS_SETUP_COMP 4
|
||||||
|
#define STS_SETUP_UPDT 6
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HCFG_30_60_MHZ 0
|
||||||
|
#define HCFG_48_MHZ 1
|
||||||
|
#define HCFG_6_MHZ 2
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HPRT0_PRTSPD_HIGH_SPEED 0
|
||||||
|
#define HPRT0_PRTSPD_FULL_SPEED 1
|
||||||
|
#define HPRT0_PRTSPD_LOW_SPEED 2
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define HCCHAR_CTRL 0
|
||||||
|
#define HCCHAR_ISOC 1
|
||||||
|
#define HCCHAR_BULK 2
|
||||||
|
#define HCCHAR_INTR 3
|
||||||
|
|
||||||
|
#define HC_PID_DATA0 0
|
||||||
|
#define HC_PID_DATA2 1
|
||||||
|
#define HC_PID_DATA1 2
|
||||||
|
#define HC_PID_SETUP 3
|
||||||
|
|
||||||
|
#define GRXSTS_PKTSTS_IN 2
|
||||||
|
#define GRXSTS_PKTSTS_IN_XFER_COMP 3
|
||||||
|
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
|
||||||
|
#define GRXSTS_PKTSTS_CH_HALTED 7
|
||||||
|
|
||||||
|
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
|
||||||
|
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
|
||||||
|
|
||||||
|
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
|
||||||
|
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
|
||||||
|
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
|
||||||
|
#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
|
||||||
|
|
||||||
|
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
|
||||||
|
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
|
||||||
|
#endif /* USB_OTG_FS */
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DEP0CTL_MPS_64 0
|
||||||
|
#define DEP0CTL_MPS_32 1
|
||||||
|
#define DEP0CTL_MPS_16 2
|
||||||
|
#define DEP0CTL_MPS_8 3
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EP_TYPE_CTRL 0
|
||||||
|
#define EP_TYPE_ISOC 1
|
||||||
|
#define EP_TYPE_BULK 2
|
||||||
|
#define EP_TYPE_INTR 3
|
||||||
|
#define EP_TYPE_MSK 3
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define BTABLE_ADDRESS (0x000)
|
||||||
|
#endif /* USB */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB_OTG_FS)
|
||||||
|
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
|
||||||
|
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
|
||||||
|
|
||||||
|
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
|
||||||
|
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
|
||||||
|
#endif /* USB_OTG_FS */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @addtogroup USB_LL_Exported_Functions_Group1 Peripheral Control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (USB_OTG_FS)
|
||||||
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
|
||||||
|
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
|
||||||
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode);
|
||||||
|
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
|
||||||
|
HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
|
||||||
|
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
|
||||||
|
void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||||
|
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
|
||||||
|
HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);
|
||||||
|
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
|
||||||
|
uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
|
||||||
|
void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
|
||||||
|
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
|
||||||
|
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
|
||||||
|
uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
|
||||||
|
uint8_t ch_num,
|
||||||
|
uint8_t epnum,
|
||||||
|
uint8_t dev_address,
|
||||||
|
uint8_t speed,
|
||||||
|
uint8_t ep_type,
|
||||||
|
uint16_t mps);
|
||||||
|
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);
|
||||||
|
uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
|
||||||
|
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
|
||||||
|
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
|
||||||
|
#endif /* USB_OTG_FS */
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init);
|
||||||
|
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef Init);
|
||||||
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode);
|
||||||
|
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx , uint8_t speed);
|
||||||
|
HAL_StatusTypeDef USB_FlushRxFifo (USB_TypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num );
|
||||||
|
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
|
||||||
|
void * USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
|
||||||
|
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx , USB_EPTypeDef *ep);
|
||||||
|
HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address);
|
||||||
|
HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
|
||||||
|
uint32_t USB_ReadInterrupts (USB_TypeDef *USBx);
|
||||||
|
uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx);
|
||||||
|
uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum);
|
||||||
|
uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx);
|
||||||
|
uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum);
|
||||||
|
void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt);
|
||||||
|
|
||||||
|
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
|
||||||
|
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
|
||||||
|
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||||
|
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||||
|
#endif /* USB */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F102x6 || STM32F102xB || */
|
||||||
|
/* STM32F103x6 || STM32F103xB || */
|
||||||
|
/* STM32F103xE || STM32F103xG || */
|
||||||
|
/* STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_LL_USB_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,284 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_utils.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of UTILS LL module.
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
The LL UTILS driver contains a set of generic APIs that can be
|
||||||
|
used by user:
|
||||||
|
(+) Device electronic signature
|
||||||
|
(+) Timing functions
|
||||||
|
(+) PLL configuration functions
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_LL_UTILS_H
|
||||||
|
#define __STM32F1xx_LL_UTILS_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup UTILS_LL UTILS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Max delay can be used in LL_mDelay */
|
||||||
|
#define LL_MAX_DELAY 0xFFFFFFFFU
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Unique device ID register base address
|
||||||
|
*/
|
||||||
|
#define UID_BASE_ADDRESS UID_BASE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Flash size data register base address
|
||||||
|
*/
|
||||||
|
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief UTILS PLL structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
|
||||||
|
This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
|
||||||
|
|
||||||
|
This feature can be modified afterwards using unitary function
|
||||||
|
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||||
|
|
||||||
|
uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
|
||||||
|
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
|
||||||
|
|
||||||
|
This feature can be modified afterwards using unitary function
|
||||||
|
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
|
||||||
|
} LL_UTILS_PLLInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief UTILS System, AHB and APB buses clock configuration structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||||
|
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
|
||||||
|
|
||||||
|
This feature can be modified afterwards using unitary function
|
||||||
|
@ref LL_RCC_SetAHBPrescaler(). */
|
||||||
|
|
||||||
|
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||||
|
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
|
||||||
|
|
||||||
|
This feature can be modified afterwards using unitary function
|
||||||
|
@ref LL_RCC_SetAPB1Prescaler(). */
|
||||||
|
|
||||||
|
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
|
||||||
|
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
|
||||||
|
|
||||||
|
This feature can be modified afterwards using unitary function
|
||||||
|
@ref LL_RCC_SetAPB2Prescaler(). */
|
||||||
|
|
||||||
|
} LL_UTILS_ClkInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
|
||||||
|
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
|
||||||
|
* @retval UID[31:0]
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
|
||||||
|
* @retval UID[63:32]
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
|
||||||
|
* @retval UID[95:64]
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Flash memory size
|
||||||
|
* @note This bitfield indicates the size of the device Flash memory expressed in
|
||||||
|
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
|
||||||
|
* @retval FLASH_SIZE[15:0]: Flash memory size
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||||
|
{
|
||||||
|
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup UTILS_LL_EF_DELAY DELAY
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function configures the Cortex-M SysTick source of the time base.
|
||||||
|
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||||
|
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||||
|
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||||
|
* @param Ticks Number of ticks
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||||
|
{
|
||||||
|
/* Configure the SysTick to have interrupt in 1ms time base */
|
||||||
|
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
||||||
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
||||||
|
}
|
||||||
|
|
||||||
|
void LL_Init1msTick(uint32_t HCLKFrequency);
|
||||||
|
void LL_mDelay(uint32_t Delay);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup UTILS_EF_SYSTEM SYSTEM
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
|
||||||
|
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||||
|
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||||
|
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
|
||||||
|
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_LL_UTILS_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,342 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_wwdg.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Header file of WWDG LL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F1xx_LL_WWDG_H
|
||||||
|
#define __STM32F1xx_LL_WWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (WWDG)
|
||||||
|
|
||||||
|
/** @defgroup WWDG_LL WWDG
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup WWDG_LL_EC_IT IT Defines
|
||||||
|
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
|
||||||
|
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
|
||||||
|
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
|
||||||
|
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief Write a value in WWDG register
|
||||||
|
* @param __INSTANCE__ WWDG Instance
|
||||||
|
* @param __REG__ Register to be written
|
||||||
|
* @param __VALUE__ Value to be written in the register
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read a value in WWDG register
|
||||||
|
* @param __INSTANCE__ WWDG Instance
|
||||||
|
* @param __REG__ Register to be read
|
||||||
|
* @retval Register value
|
||||||
|
*/
|
||||||
|
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_LL_EF_Configuration Configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
|
||||||
|
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
|
||||||
|
* then it cannot be disabled again except by a reset.
|
||||||
|
* This bit is set by software and only cleared by hardware after a reset.
|
||||||
|
* When WDGA = 1, the watchdog can generate a reset.
|
||||||
|
* @rmtoll CR WDGA LL_WWDG_Enable
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
|
||||||
|
{
|
||||||
|
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks if Window Watchdog is enabled
|
||||||
|
* @rmtoll CR WDGA LL_WWDG_IsEnabled
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
|
||||||
|
{
|
||||||
|
return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
|
||||||
|
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
|
||||||
|
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||||
|
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
|
||||||
|
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
|
||||||
|
* @rmtoll CR T LL_WWDG_SetCounter
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @param Counter 0..0x7F (7 bit counter value)
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
|
||||||
|
{
|
||||||
|
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return current Watchdog Counter Value (7 bits counter value)
|
||||||
|
* @rmtoll CR T LL_WWDG_GetCounter
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @retval 7 bit Watchdog Counter value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the time base of the prescaler (WDGTB).
|
||||||
|
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
|
||||||
|
* is decremented every (4096 x 2expWDGTB) PCLK cycles
|
||||||
|
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @param Prescaler This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_WWDG_PRESCALER_1
|
||||||
|
* @arg @ref LL_WWDG_PRESCALER_2
|
||||||
|
* @arg @ref LL_WWDG_PRESCALER_4
|
||||||
|
* @arg @ref LL_WWDG_PRESCALER_8
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
|
||||||
|
{
|
||||||
|
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return current Watchdog Prescaler Value
|
||||||
|
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @retval Returned value can be one of the following values:
|
||||||
|
* @arg @ref LL_WWDG_PRESCALER_1
|
||||||
|
* @arg @ref LL_WWDG_PRESCALER_2
|
||||||
|
* @arg @ref LL_WWDG_PRESCALER_4
|
||||||
|
* @arg @ref LL_WWDG_PRESCALER_8
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
|
||||||
|
* @note This window value defines when write in the WWDG_CR register
|
||||||
|
* to program Watchdog counter is allowed.
|
||||||
|
* Watchdog counter value update must occur only when the counter value
|
||||||
|
* is lower than the Watchdog window register value.
|
||||||
|
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
|
||||||
|
* (in the control register) is refreshed before the downcounter has reached
|
||||||
|
* the watchdog window register value.
|
||||||
|
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
|
||||||
|
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
|
||||||
|
* @rmtoll CFR W LL_WWDG_SetWindow
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @param Window 0x00..0x7F (7 bit Window value)
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
|
||||||
|
{
|
||||||
|
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return current Watchdog Window Value (7 bits value)
|
||||||
|
* @rmtoll CFR W LL_WWDG_GetWindow
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @retval 7 bit Watchdog Window value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
|
||||||
|
{
|
||||||
|
return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
|
||||||
|
* @note This bit is set by hardware when the counter has reached the value 0x40.
|
||||||
|
* It must be cleared by software by writing 0.
|
||||||
|
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
|
||||||
|
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||||
|
{
|
||||||
|
return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
|
||||||
|
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
|
||||||
|
{
|
||||||
|
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief Enable the Early Wakeup Interrupt.
|
||||||
|
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
|
||||||
|
* This interrupt is only cleared by hardware after a reset
|
||||||
|
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||||
|
{
|
||||||
|
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if Early Wakeup Interrupt is enabled
|
||||||
|
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
|
||||||
|
* @param WWDGx WWDG Instance
|
||||||
|
* @retval State of bit (1 or 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
|
||||||
|
{
|
||||||
|
return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* WWDG */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F1xx_LL_WWDG_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
2112
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c
Normal file
2112
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
1702
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c
Normal file
1702
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,694 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_cec.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief CEC HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the High Definition Multimedia Interface
|
||||||
|
* Consumer Electronics Control Peripheral (CEC).
|
||||||
|
* + Initialization and de-initialization function
|
||||||
|
* + IO operation function
|
||||||
|
* + Peripheral Control function
|
||||||
|
*
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
===============================================================================
|
||||||
|
[..]
|
||||||
|
The CEC HAL driver can be used as follow:
|
||||||
|
|
||||||
|
(#) Declare a CEC_HandleTypeDef handle structure.
|
||||||
|
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
|
||||||
|
(##) Enable the CEC interface clock.
|
||||||
|
(##) CEC pins configuration:
|
||||||
|
(+++) Enable the clock for the CEC GPIOs.
|
||||||
|
(+++) Configure these CEC pins as alternate function pull-up.
|
||||||
|
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
|
||||||
|
and HAL_CEC_Receive_IT() APIs):
|
||||||
|
(+++) Configure the CEC interrupt priority.
|
||||||
|
(+++) Enable the NVIC CEC IRQ handle.
|
||||||
|
(+++) The specific CEC interrupts (Transmission complete interrupt,
|
||||||
|
RXNE interrupt and Error Interrupts) will be managed using the macros
|
||||||
|
__HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
|
||||||
|
and receive process.
|
||||||
|
|
||||||
|
(#) Program the Bit Timing Error Mode and the Bit Period Error Mode in the hcec Init structure.
|
||||||
|
|
||||||
|
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
|
||||||
|
|
||||||
|
[..]
|
||||||
|
(@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
|
||||||
|
by calling the customed HAL_CEC_MspInit() API.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
#ifdef HAL_CEC_MODULE_ENABLED
|
||||||
|
|
||||||
|
#if defined(STM32F100xB) || defined(STM32F100xE)
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC CEC
|
||||||
|
* @brief HAL CEC module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_CFGR_FIELDS (CEC_CFGR_BTEM | CEC_CFGR_BPEM )
|
||||||
|
#define CEC_FLAG_TRANSMIT_MASK (CEC_FLAG_TSOM|CEC_FLAG_TEOM|CEC_FLAG_TBTRF)
|
||||||
|
#define CEC_FLAG_RECEIVE_MASK (CEC_FLAG_RSOM|CEC_FLAG_REOM|CEC_FLAG_RBTF)
|
||||||
|
#define CEC_ESR_ALL_ERROR (CEC_ESR_BTE|CEC_ESR_BPE|CEC_ESR_RBTFE|CEC_ESR_SBE|CEC_ESR_ACKE|CEC_ESR_LINE|CEC_ESR_TBTFE)
|
||||||
|
#define CEC_RXXFERSIZE_INITIALIZE 0xFFFF /*!< Value used to initialise the RxXferSize of the handle */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
|
||||||
|
static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Exported_Functions CEC Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### Initialization and Configuration functions #####
|
||||||
|
===============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection provides a set of functions allowing to initialize the CEC
|
||||||
|
(+) The following parameters need to be configured:
|
||||||
|
(++) TimingErrorFree
|
||||||
|
(++) PeriodErrorFree
|
||||||
|
(++) InitiatorAddress
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the CEC mode according to the specified
|
||||||
|
* parameters in the CEC_InitTypeDef and creates the associated handle .
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
/* Check the CEC handle allocation */
|
||||||
|
if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
|
||||||
|
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(hcec->Init.TimingErrorFree));
|
||||||
|
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(hcec->Init.PeriodErrorFree));
|
||||||
|
assert_param(IS_CEC_ADDRESS(hcec->Init.OwnAddress));
|
||||||
|
|
||||||
|
if(hcec->gState == HAL_CEC_STATE_RESET)
|
||||||
|
{
|
||||||
|
/* Allocate lock resource and initialize it */
|
||||||
|
hcec->Lock = HAL_UNLOCKED;
|
||||||
|
/* Init the low level hardware : GPIO, CLOCK */
|
||||||
|
HAL_CEC_MspInit(hcec);
|
||||||
|
}
|
||||||
|
hcec->gState = HAL_CEC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Disable the Peripheral */
|
||||||
|
__HAL_CEC_DISABLE(hcec);
|
||||||
|
|
||||||
|
/* Write to CEC Control Register */
|
||||||
|
MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree | hcec->Init.PeriodErrorFree);
|
||||||
|
|
||||||
|
/* Write to CEC Own Address Register */
|
||||||
|
MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
|
||||||
|
|
||||||
|
/* Configure the prescaler to generate the required 50 microseconds time base.*/
|
||||||
|
MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50U * (HAL_RCC_GetPCLK1Freq()/1000000U) - 1U);
|
||||||
|
|
||||||
|
/* Enable the following CEC Interrupt */
|
||||||
|
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
|
||||||
|
|
||||||
|
/* Enable the CEC Peripheral */
|
||||||
|
__HAL_CEC_ENABLE(hcec);
|
||||||
|
|
||||||
|
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||||
|
hcec->gState = HAL_CEC_STATE_READY;
|
||||||
|
hcec->RxState = HAL_CEC_STATE_READY;
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DeInitializes the CEC peripheral
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
/* Check the CEC handle allocation */
|
||||||
|
if(hcec == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
|
||||||
|
|
||||||
|
hcec->gState = HAL_CEC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* DeInit the low level hardware */
|
||||||
|
HAL_CEC_MspDeInit(hcec);
|
||||||
|
|
||||||
|
__HAL_RCC_CEC_FORCE_RESET();
|
||||||
|
__HAL_RCC_CEC_RELEASE_RESET();
|
||||||
|
|
||||||
|
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||||
|
hcec->gState = HAL_CEC_STATE_RESET;
|
||||||
|
hcec->RxState = HAL_CEC_STATE_RESET;
|
||||||
|
|
||||||
|
/* Process Unlock */
|
||||||
|
__HAL_UNLOCK(hcec);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the Own Address of the CEC device
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @param CEC_OwnAddress: The CEC own address.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
|
||||||
|
|
||||||
|
if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hcec);
|
||||||
|
|
||||||
|
hcec->gState = HAL_CEC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Disable the Peripheral */
|
||||||
|
__HAL_CEC_DISABLE(hcec);
|
||||||
|
|
||||||
|
if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
|
||||||
|
{
|
||||||
|
MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
CLEAR_BIT(hcec->Instance->OAR, CEC_OAR_OA);
|
||||||
|
}
|
||||||
|
|
||||||
|
hcec->gState = HAL_CEC_STATE_READY;
|
||||||
|
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hcec);
|
||||||
|
|
||||||
|
/* Enable the Peripheral */
|
||||||
|
__HAL_CEC_ENABLE(hcec);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CEC MSP Init
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hcec);
|
||||||
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||||||
|
the HAL_CEC_MspInit can be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CEC MSP DeInit
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hcec);
|
||||||
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||||||
|
the HAL_CEC_MspDeInit can be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
|
||||||
|
* @brief CEC Transmit/Receive functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### IO operation functions #####
|
||||||
|
===============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection provides a set of functions allowing to manage the CEC data transfers.
|
||||||
|
|
||||||
|
(#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
|
||||||
|
logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
|
||||||
|
|
||||||
|
(#) The communication is performed using Interrupts.
|
||||||
|
These API's return the HAL status.
|
||||||
|
The end of the data processing will be indicated through the
|
||||||
|
dedicated CEC IRQ when using Interrupt mode.
|
||||||
|
The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
|
||||||
|
will be executed respectively at the end of the transmit or Receive process
|
||||||
|
The HAL_CEC_ErrorCallback() user callback will be executed when a communication
|
||||||
|
error is detected
|
||||||
|
|
||||||
|
(#) API's with Interrupt are :
|
||||||
|
(+) HAL_CEC_Transmit_IT()
|
||||||
|
(+) HAL_CEC_IRQHandler()
|
||||||
|
|
||||||
|
(#) A set of User Callbacks are provided:
|
||||||
|
(+) HAL_CEC_TxCpltCallback()
|
||||||
|
(+) HAL_CEC_RxCpltCallback()
|
||||||
|
(+) HAL_CEC_ErrorCallback()
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Send data in interrupt mode
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @param InitiatorAddress: Initiator address
|
||||||
|
* @param DestinationAddress: destination logical address
|
||||||
|
* @param pData: pointer to input byte data buffer
|
||||||
|
* @param Size: amount of data to be sent in bytes (without counting the header).
|
||||||
|
* 0 means only the header is sent (ping operation).
|
||||||
|
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
|
||||||
|
{
|
||||||
|
/* if the IP isn't already busy and if there is no previous transmission
|
||||||
|
already pending due to arbitration lost */
|
||||||
|
if(hcec->gState == HAL_CEC_STATE_READY)
|
||||||
|
{
|
||||||
|
if((pData == NULL ) && (Size > 0U))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
assert_param(IS_CEC_ADDRESS(DestinationAddress));
|
||||||
|
assert_param(IS_CEC_ADDRESS(InitiatorAddress));
|
||||||
|
assert_param(IS_CEC_MSGSIZE(Size));
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hcec);
|
||||||
|
hcec->pTxBuffPtr = pData;
|
||||||
|
hcec->gState = HAL_CEC_STATE_BUSY_TX;
|
||||||
|
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
|
||||||
|
|
||||||
|
/* initialize the number of bytes to send,
|
||||||
|
* 0 means only one header is sent (ping operation) */
|
||||||
|
hcec->TxXferCount = Size;
|
||||||
|
|
||||||
|
/* send header block */
|
||||||
|
hcec->Instance->TXD = (uint8_t)((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hcec);
|
||||||
|
|
||||||
|
/* case no data to be sent, sender is only pinging the system */
|
||||||
|
if (Size != 0)
|
||||||
|
{
|
||||||
|
/* Set TX Start of Message (TXSOM) bit */
|
||||||
|
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TSOM);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Send a ping command */
|
||||||
|
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM|CEC_FLAG_TSOM);
|
||||||
|
}
|
||||||
|
return HAL_OK;
|
||||||
|
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get size of the received frame.
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @retval Frame size
|
||||||
|
*/
|
||||||
|
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
return hcec->RxXferSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Change Rx Buffer.
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @param Rxbuffer: Rx Buffer
|
||||||
|
* @note This function can be called only inside the HAL_CEC_RxCpltCallback()
|
||||||
|
* @retval Frame size
|
||||||
|
*/
|
||||||
|
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
|
||||||
|
{
|
||||||
|
hcec->Init.RxBuffer = Rxbuffer;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles CEC interrupt requests.
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
/* Save error status register for further error handling purposes */
|
||||||
|
hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
|
||||||
|
|
||||||
|
/* Transmit error */
|
||||||
|
if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TERR) != RESET)
|
||||||
|
{
|
||||||
|
/* Acknowledgement of the error */
|
||||||
|
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
|
||||||
|
|
||||||
|
hcec->gState = HAL_CEC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Receive error */
|
||||||
|
if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RERR) != RESET)
|
||||||
|
{
|
||||||
|
/* Acknowledgement of the error */
|
||||||
|
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
|
||||||
|
hcec->Init.RxBuffer-=hcec->RxXferSize;
|
||||||
|
hcec->RxXferSize = 0U;
|
||||||
|
hcec->RxState = HAL_CEC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
if((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0U)
|
||||||
|
{
|
||||||
|
/* Error Call Back */
|
||||||
|
HAL_CEC_ErrorCallback(hcec);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Transmit byte request or block transfer finished */
|
||||||
|
if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TBTRF) != RESET)
|
||||||
|
{
|
||||||
|
CEC_Transmit_IT(hcec);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Receive byte or block transfer finished */
|
||||||
|
if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RBTF) != RESET)
|
||||||
|
{
|
||||||
|
if(hcec->RxXferSize == 0U)
|
||||||
|
{
|
||||||
|
/* reception is starting */
|
||||||
|
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
|
||||||
|
}
|
||||||
|
CEC_Receive_IT(hcec);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Tx Transfer completed callback
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hcec);
|
||||||
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||||||
|
the HAL_CEC_TxCpltCallback can be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Rx Transfer completed callback
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @param RxFrameSize: Size of frame
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hcec);
|
||||||
|
UNUSED(RxFrameSize);
|
||||||
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||||||
|
the HAL_CEC_RxCpltCallback can be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CEC error callbacks
|
||||||
|
* @param hcec: CEC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hcec);
|
||||||
|
/* NOTE : This function should not be modified, when the callback is needed,
|
||||||
|
the HAL_CEC_ErrorCallback can be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
|
||||||
|
* @brief CEC control functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### Peripheral Control function #####
|
||||||
|
===============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection provides a set of functions allowing to control the CEC.
|
||||||
|
(+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
|
||||||
|
(+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief return the CEC state
|
||||||
|
* @param hcec: pointer to a CEC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified CEC module.
|
||||||
|
* @retval HAL state
|
||||||
|
*/
|
||||||
|
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
uint32_t temp1= 0x00U, temp2 = 0x00U;
|
||||||
|
temp1 = hcec->gState;
|
||||||
|
temp2 = hcec->RxState;
|
||||||
|
|
||||||
|
return (HAL_CEC_StateTypeDef)(temp1 | temp2);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the CEC error code
|
||||||
|
* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified CEC.
|
||||||
|
* @retval CEC Error Code
|
||||||
|
*/
|
||||||
|
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
return hcec->ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CEC_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Send data in interrupt mode
|
||||||
|
* @param hcec: CEC handle.
|
||||||
|
* Function called under interruption only, once
|
||||||
|
* interruptions have been enabled by HAL_CEC_Transmit_IT()
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
/* if the IP is already busy or if there is a previous transmission
|
||||||
|
already pending due to arbitration loss */
|
||||||
|
if((hcec->gState == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
|
||||||
|
{
|
||||||
|
/* if all data have been sent */
|
||||||
|
if(hcec->TxXferCount == 0U)
|
||||||
|
{
|
||||||
|
/* Acknowledge successful completion by writing 0x00 */
|
||||||
|
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
|
||||||
|
|
||||||
|
hcec->gState = HAL_CEC_STATE_READY;
|
||||||
|
|
||||||
|
HAL_CEC_TxCpltCallback(hcec);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Reduce the number of bytes to transfer by one */
|
||||||
|
hcec->TxXferCount--;
|
||||||
|
|
||||||
|
/* Write data to TX buffer*/
|
||||||
|
hcec->Instance->TXD = *hcec->pTxBuffPtr++;
|
||||||
|
|
||||||
|
/* If this is the last byte of the ongoing transmission */
|
||||||
|
if(hcec->TxXferCount == 0U)
|
||||||
|
{
|
||||||
|
/* Acknowledge byte request and signal end of message */
|
||||||
|
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Acknowledge byte request by writing 0x00 */
|
||||||
|
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Receive data in interrupt mode.
|
||||||
|
* @param hcec: CEC handle.
|
||||||
|
* Function called under interruption only, once
|
||||||
|
* interruptions have been enabled by HAL_CEC_Receive_IT()
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
|
||||||
|
{
|
||||||
|
static uint32_t temp;
|
||||||
|
|
||||||
|
if(hcec->RxState == HAL_CEC_STATE_BUSY_RX)
|
||||||
|
{
|
||||||
|
temp = hcec->Instance->CSR;
|
||||||
|
|
||||||
|
/* Store received data */
|
||||||
|
hcec->RxXferSize++;
|
||||||
|
*hcec->Init.RxBuffer++ = hcec->Instance->RXD;
|
||||||
|
|
||||||
|
/* Acknowledge received byte by writing 0x00 */
|
||||||
|
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00U);
|
||||||
|
|
||||||
|
/* If the End Of Message is reached */
|
||||||
|
if(HAL_IS_BIT_SET(temp, CEC_FLAG_REOM))
|
||||||
|
{
|
||||||
|
/* Interrupts are not disabled due to transmission still ongoing */
|
||||||
|
hcec->RxState = HAL_CEC_STATE_READY;
|
||||||
|
|
||||||
|
HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* defined(STM32F100xB) || defined(STM32F100xE) */
|
||||||
|
|
||||||
|
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,348 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_crc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief CRC HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
|
||||||
|
* + Initialization and de-initialization functions
|
||||||
|
* + Peripheral Control functions
|
||||||
|
* + Peripheral State functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
The CRC HAL driver can be used as follows:
|
||||||
|
|
||||||
|
(#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
|
||||||
|
|
||||||
|
(#) Use HAL_CRC_Accumulate() function to compute the CRC value of
|
||||||
|
a 32-bit data buffer using combination of the previous CRC value
|
||||||
|
and the new one.
|
||||||
|
|
||||||
|
(#) Use HAL_CRC_Calculate() function to compute the CRC Value of
|
||||||
|
a new 32-bit data buffer. This function resets the CRC computation
|
||||||
|
unit before starting the computation to avoid getting wrong CRC values.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC CRC
|
||||||
|
* @brief CRC HAL module driver.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_CRC_MODULE_ENABLED
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @brief Initialization and Configuration functions.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Initialization and de-initialization functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..] This section provides functions allowing to:
|
||||||
|
(+) Initialize the CRC according to the specified parameters
|
||||||
|
in the CRC_InitTypeDef and create the associated handle
|
||||||
|
(+) DeInitialize the CRC peripheral
|
||||||
|
(+) Initialize the CRC MSP
|
||||||
|
(+) DeInitialize CRC MSP
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the CRC according to the specified
|
||||||
|
* parameters in the CRC_InitTypeDef and creates the associated handle.
|
||||||
|
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for CRC
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||||
|
{
|
||||||
|
/* Check the CRC handle allocation */
|
||||||
|
if(hcrc == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||||
|
|
||||||
|
if(hcrc->State == HAL_CRC_STATE_RESET)
|
||||||
|
{
|
||||||
|
/* Allocate lock resource and initialize it */
|
||||||
|
hcrc->Lock = HAL_UNLOCKED;
|
||||||
|
|
||||||
|
/* Init the low level hardware */
|
||||||
|
HAL_CRC_MspInit(hcrc);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Change CRC peripheral state */
|
||||||
|
hcrc->State = HAL_CRC_STATE_READY;
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DeInitializes the CRC peripheral.
|
||||||
|
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for CRC
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||||
|
{
|
||||||
|
/* Check the CRC handle allocation */
|
||||||
|
if(hcrc == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||||
|
|
||||||
|
/* Change CRC peripheral state */
|
||||||
|
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* DeInit the low level hardware */
|
||||||
|
HAL_CRC_MspDeInit(hcrc);
|
||||||
|
|
||||||
|
/* Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF */
|
||||||
|
__HAL_CRC_DR_RESET(hcrc);
|
||||||
|
|
||||||
|
/* Reset IDR register content */
|
||||||
|
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
|
||||||
|
|
||||||
|
/* Change CRC peripheral state */
|
||||||
|
hcrc->State = HAL_CRC_STATE_RESET;
|
||||||
|
|
||||||
|
/* Release Lock */
|
||||||
|
__HAL_UNLOCK(hcrc);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the CRC MSP.
|
||||||
|
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for CRC
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hcrc);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_CRC_MspInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DeInitializes the CRC MSP.
|
||||||
|
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for CRC
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hcrc);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_CRC_MspDeInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||||
|
* @brief management functions.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Peripheral Control functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..] This section provides functions allowing to:
|
||||||
|
(+) Compute the 32-bit CRC value of 32-bit data buffer,
|
||||||
|
using combination of the previous CRC value and the new one.
|
||||||
|
(+) Compute the 32-bit CRC value of 32-bit data buffer,
|
||||||
|
independently of the previous CRC value.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Computes the 32-bit CRC of 32-bit data buffer using combination
|
||||||
|
* of the previous CRC value and the new one.
|
||||||
|
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for CRC
|
||||||
|
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||||
|
* @param BufferLength: length of the buffer to be computed (defined in word, 4 bytes)
|
||||||
|
* @retval 32-bit CRC
|
||||||
|
*/
|
||||||
|
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||||
|
{
|
||||||
|
uint32_t index = 0U;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hcrc);
|
||||||
|
|
||||||
|
/* Change CRC peripheral state */
|
||||||
|
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Enter Data to the CRC calculator */
|
||||||
|
for(index = 0U; index < BufferLength; index++)
|
||||||
|
{
|
||||||
|
hcrc->Instance->DR = pBuffer[index];
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Change CRC peripheral state */
|
||||||
|
hcrc->State = HAL_CRC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hcrc);
|
||||||
|
|
||||||
|
/* Return the CRC computed value */
|
||||||
|
return hcrc->Instance->DR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Computes the 32-bit CRC of 32-bit data buffer independently
|
||||||
|
* of the previous CRC value.
|
||||||
|
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for CRC
|
||||||
|
* @param pBuffer: Pointer to the buffer containing the data to be computed
|
||||||
|
* @param BufferLength: Length of the buffer to be computed (defined in word, 4 bytes)
|
||||||
|
* @retval 32-bit CRC
|
||||||
|
*/
|
||||||
|
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||||
|
{
|
||||||
|
uint32_t index = 0U;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hcrc);
|
||||||
|
|
||||||
|
/* Change CRC peripheral state */
|
||||||
|
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Reset CRC Calculation Unit */
|
||||||
|
__HAL_CRC_DR_RESET(hcrc);
|
||||||
|
|
||||||
|
/* Enter Data to the CRC calculator */
|
||||||
|
for(index = 0U; index < BufferLength; index++)
|
||||||
|
{
|
||||||
|
hcrc->Instance->DR = pBuffer[index];
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Change CRC peripheral state */
|
||||||
|
hcrc->State = HAL_CRC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hcrc);
|
||||||
|
|
||||||
|
/* Return the CRC computed value */
|
||||||
|
return hcrc->Instance->DR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||||
|
* @brief Peripheral State functions.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Peripheral State functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection permits to get in run-time the status of the peripheral.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the CRC state.
|
||||||
|
* @param hcrc: pointer to a CRC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for CRC
|
||||||
|
* @retval HAL state
|
||||||
|
*/
|
||||||
|
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
||||||
|
{
|
||||||
|
return hcrc->State;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,939 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_dac.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief DAC HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the Digital to Analog Converter (DAC) peripheral:
|
||||||
|
* + Initialization and de-initialization functions
|
||||||
|
* + IO operation functions
|
||||||
|
* + Peripheral Control functions
|
||||||
|
* + Peripheral State and Errors functions
|
||||||
|
*
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### DAC Peripheral features #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
*** DAC Channels ***
|
||||||
|
====================
|
||||||
|
[..]
|
||||||
|
The device integrates two 12-bit Digital Analog Converters that can
|
||||||
|
be used independently or simultaneously (dual mode):
|
||||||
|
(#) DAC channel1 with DAC_OUT1 (PA4) as output
|
||||||
|
(#) DAC channel2 with DAC_OUT2 (PA5) as output
|
||||||
|
|
||||||
|
*** DAC Triggers ***
|
||||||
|
====================
|
||||||
|
[..]
|
||||||
|
Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
|
||||||
|
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
|
||||||
|
[..]
|
||||||
|
Digital to Analog conversion can be triggered by:
|
||||||
|
(#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
|
||||||
|
The used pin (GPIOx_PIN_9) must be configured in input mode.
|
||||||
|
|
||||||
|
(#) Timers TRGO: TIM2, TIM4, TIM6, TIM7
|
||||||
|
For STM32F10x connectivity line devices and STM32F100x devices: TIM3
|
||||||
|
For STM32F10x high-density and XL-density devices: TIM8
|
||||||
|
For STM32F100x high-density value line devices: TIM15 as
|
||||||
|
replacement of TIM5.
|
||||||
|
(DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
|
||||||
|
|
||||||
|
(#) Software using DAC_TRIGGER_SOFTWARE
|
||||||
|
|
||||||
|
*** DAC Buffer mode feature ***
|
||||||
|
===============================
|
||||||
|
[..]
|
||||||
|
Each DAC channel integrates an output buffer that can be used to
|
||||||
|
reduce the output impedance, and to drive external loads directly
|
||||||
|
without having to add an external operational amplifier.
|
||||||
|
To enable, the output buffer use
|
||||||
|
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
|
||||||
|
[..]
|
||||||
|
(@) Refer to the device datasheet for more details about output
|
||||||
|
impedance value with and without output buffer.
|
||||||
|
|
||||||
|
*** DAC connect feature ***
|
||||||
|
===============================
|
||||||
|
[..]
|
||||||
|
Each DAC channel can be connected internally.
|
||||||
|
To connect, use
|
||||||
|
sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
|
||||||
|
|
||||||
|
*** GPIO configurations guidelines ***
|
||||||
|
=====================
|
||||||
|
[..]
|
||||||
|
When a DAC channel is used (ex channel1 on PA4) and the other is not
|
||||||
|
(ex channel1 on PA5 is configured in Analog and disabled).
|
||||||
|
Channel1 may disturb channel2 as coupling effect.
|
||||||
|
Note that there is no coupling on channel2 as soon as channel2 is turned on.
|
||||||
|
Coupling on adjacent channel could be avoided as follows:
|
||||||
|
when unused PA5 is configured as INPUT PULL-UP or DOWN.
|
||||||
|
PA5 is configured in ANALOG just before it is turned on.
|
||||||
|
|
||||||
|
*** DAC wave generation feature ***
|
||||||
|
===================================
|
||||||
|
[..]
|
||||||
|
Both DAC channels can be used to generate
|
||||||
|
(#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
|
||||||
|
(#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
|
||||||
|
|
||||||
|
*** DAC data format ***
|
||||||
|
=======================
|
||||||
|
[..]
|
||||||
|
The DAC data format can be:
|
||||||
|
(#) 8-bit right alignment using DAC_ALIGN_8B_R
|
||||||
|
(#) 12-bit left alignment using DAC_ALIGN_12B_L
|
||||||
|
(#) 12-bit right alignment using DAC_ALIGN_12B_R
|
||||||
|
|
||||||
|
*** DAC data value to voltage correspondance ***
|
||||||
|
================================================
|
||||||
|
[..]
|
||||||
|
The analog output voltage on each DAC channel pin is determined
|
||||||
|
by the following equation:
|
||||||
|
[..]
|
||||||
|
DAC_OUTx = VREF+ * DOR / 4095
|
||||||
|
(+) with DOR is the Data Output Register
|
||||||
|
[..]
|
||||||
|
VEF+ is the input voltage reference (refer to the device datasheet)
|
||||||
|
[..]
|
||||||
|
e.g. To set DAC_OUT1 to 0.7V, use
|
||||||
|
(+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
|
||||||
|
|
||||||
|
*** DMA requests ***
|
||||||
|
=====================
|
||||||
|
[..]
|
||||||
|
A DMA1 request can be generated when an external trigger (but not
|
||||||
|
a software trigger) occurs if DMA1 requests are enabled using
|
||||||
|
HAL_DAC_Start_DMA()
|
||||||
|
[..]
|
||||||
|
DMA requests are mapped as following:
|
||||||
|
(#) DAC channel1 :
|
||||||
|
For STM32F100x low-density, medium-density, high-density with DAC
|
||||||
|
DMA remap:
|
||||||
|
mapped on DMA1 channel3 which must be
|
||||||
|
already configured
|
||||||
|
For STM32F100x high-density without DAC DMA remap and other
|
||||||
|
STM32F1 devices:
|
||||||
|
mapped on DMA2 channel3 which must be
|
||||||
|
already configured
|
||||||
|
(#) DAC channel2 :
|
||||||
|
For STM32F100x low-density, medium-density, high-density with DAC
|
||||||
|
DMA remap:
|
||||||
|
mapped on DMA1 channel4 which must be
|
||||||
|
already configured
|
||||||
|
For STM32F100x high-density without DAC DMA remap and other
|
||||||
|
STM32F1 devices:
|
||||||
|
mapped on DMA2 channel4 which must be
|
||||||
|
already configured
|
||||||
|
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
(+) DAC APB clock must be enabled to get write access to DAC
|
||||||
|
registers using HAL_DAC_Init()
|
||||||
|
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
|
||||||
|
(+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
|
||||||
|
(+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
|
||||||
|
|
||||||
|
*** Polling mode IO operation ***
|
||||||
|
=================================
|
||||||
|
[..]
|
||||||
|
(+) Start the DAC peripheral using HAL_DAC_Start()
|
||||||
|
(+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
|
||||||
|
(+) Stop the DAC peripheral using HAL_DAC_Stop()
|
||||||
|
|
||||||
|
*** DMA mode IO operation ***
|
||||||
|
==============================
|
||||||
|
[..]
|
||||||
|
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
|
||||||
|
of data to be transferred at each end of conversion
|
||||||
|
(+) At the middle of data transfer HAL_DACEx_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
|
||||||
|
function is executed and user can add his own code by customization of function pointer
|
||||||
|
HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
|
||||||
|
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
|
||||||
|
function is executed and user can add his own code by customization of function pointer
|
||||||
|
HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
|
||||||
|
(+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() or HAL_DACEx_ErrorCallbackCh2() function is executed and user can
|
||||||
|
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 or HAL_DACEx_ErrorCallbackCh2
|
||||||
|
(+) For STM32F100x devices with specific feature: DMA underrun.
|
||||||
|
In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
|
||||||
|
HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
|
||||||
|
function is executed and user can add his own code by customization of function pointer
|
||||||
|
HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DACEx_DMAUnderrunCallbackCh2
|
||||||
|
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
|
||||||
|
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
|
||||||
|
|
||||||
|
*** DAC HAL driver macros list ***
|
||||||
|
=============================================
|
||||||
|
[..]
|
||||||
|
Below the list of most used macros in DAC HAL driver.
|
||||||
|
|
||||||
|
(+) __HAL_DAC_ENABLE : Enable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
|
||||||
|
(+) __HAL_DAC_DISABLE : Disable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
|
||||||
|
(+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (For STM32F100x devices with specific feature: DMA underrun)
|
||||||
|
(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status (For STM32F100x devices with specific feature: DMA underrun)
|
||||||
|
|
||||||
|
[..]
|
||||||
|
(@) You can refer to the DAC HAL driver header file for more useful macros
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC DAC
|
||||||
|
* @brief DAC driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_DAC_MODULE_ENABLED
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions -------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Functions DAC Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Initialization and de-initialization functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..] This section provides functions allowing to:
|
||||||
|
(+) Initialize and configure the DAC.
|
||||||
|
(+) De-initialize the DAC.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the DAC peripheral according to the specified parameters
|
||||||
|
* in the DAC_InitStruct.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
/* Check DAC handle */
|
||||||
|
if(hdac == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||||
|
|
||||||
|
if(hdac->State == HAL_DAC_STATE_RESET)
|
||||||
|
{
|
||||||
|
/* Allocate lock resource and initialize it */
|
||||||
|
hdac->Lock = HAL_UNLOCKED;
|
||||||
|
|
||||||
|
/* Init the low level hardware */
|
||||||
|
HAL_DAC_MspInit(hdac);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Initialize the DAC state*/
|
||||||
|
hdac->State = HAL_DAC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Set DAC error code to none */
|
||||||
|
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||||
|
|
||||||
|
/* Initialize the DAC state*/
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
/* Check DAC handle */
|
||||||
|
if(hdac == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* DeInit the low level hardware */
|
||||||
|
HAL_DAC_MspDeInit(hdac);
|
||||||
|
|
||||||
|
/* Set DAC error code to none */
|
||||||
|
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_RESET;
|
||||||
|
|
||||||
|
/* Release Lock */
|
||||||
|
__HAL_UNLOCK(hdac);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the DAC MSP.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DAC_MspInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DeInitializes the DAC MSP.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DAC_MspDeInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
|
||||||
|
* @brief IO operation functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### IO operation functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..] This section provides functions allowing to:
|
||||||
|
(+) Start conversion.
|
||||||
|
(+) Stop conversion.
|
||||||
|
(+) Start conversion and enable DMA transfer.
|
||||||
|
(+) Stop conversion and disable DMA transfer.
|
||||||
|
(+) Get result of conversion.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables DAC and starts conversion of channel.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
|
||||||
|
/* Process locked */
|
||||||
|
__HAL_LOCK(hdac);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Enable the Peripharal */
|
||||||
|
__HAL_DAC_ENABLE(hdac, Channel);
|
||||||
|
|
||||||
|
if(Channel == DAC_CHANNEL_1)
|
||||||
|
{
|
||||||
|
/* Check if software trigger enabled */
|
||||||
|
if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
|
||||||
|
{
|
||||||
|
/* Enable the selected DAC software conversion */
|
||||||
|
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Check if software trigger enabled */
|
||||||
|
if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
|
||||||
|
{
|
||||||
|
/* Enable the selected DAC software conversion*/
|
||||||
|
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hdac);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables DAC and stop conversion of channel.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
|
||||||
|
/* Disable the Peripheral */
|
||||||
|
__HAL_DAC_DISABLE(hdac, Channel);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables DAC and starts conversion of channel.
|
||||||
|
* Note: For STM32F100x devices with specific feature: DMA underrun.
|
||||||
|
* On these devices, this function enables the interruption of DMA
|
||||||
|
* underrun.
|
||||||
|
* (refer to redefinition of this function in DAC extended file)
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||||
|
* @param pData: The Source memory Buffer address.
|
||||||
|
* @param Length: The length of data to be transferred from memory to DAC peripheral
|
||||||
|
* @param Alignment: Specifies the data alignment for DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||||
|
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||||
|
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0U;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
assert_param(IS_DAC_ALIGN(Alignment));
|
||||||
|
|
||||||
|
/* Process locked */
|
||||||
|
__HAL_LOCK(hdac);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_BUSY;
|
||||||
|
|
||||||
|
if(Channel == DAC_CHANNEL_1)
|
||||||
|
{
|
||||||
|
/* Set the DMA transfer complete callback for channel1 */
|
||||||
|
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
|
||||||
|
|
||||||
|
/* Set the DMA half transfer complete callback for channel1 */
|
||||||
|
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
|
||||||
|
|
||||||
|
/* Set the DMA error callback for channel1 */
|
||||||
|
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
|
||||||
|
|
||||||
|
/* Enable the selected DAC channel1 DMA request */
|
||||||
|
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
|
||||||
|
|
||||||
|
/* Case of use of channel 1 */
|
||||||
|
switch(Alignment)
|
||||||
|
{
|
||||||
|
case DAC_ALIGN_12B_R:
|
||||||
|
/* Get DHR12R1 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
|
||||||
|
break;
|
||||||
|
case DAC_ALIGN_12B_L:
|
||||||
|
/* Get DHR12L1 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
|
||||||
|
break;
|
||||||
|
case DAC_ALIGN_8B_R:
|
||||||
|
/* Get DHR8R1 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Set the DMA transfer complete callback for channel2 */
|
||||||
|
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
|
||||||
|
|
||||||
|
/* Set the DMA half transfer complete callback for channel2 */
|
||||||
|
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
|
||||||
|
|
||||||
|
/* Set the DMA error callback for channel2 */
|
||||||
|
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
|
||||||
|
|
||||||
|
/* Enable the selected DAC channel2 DMA request */
|
||||||
|
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
|
||||||
|
|
||||||
|
/* Case of use of channel 2 */
|
||||||
|
switch(Alignment)
|
||||||
|
{
|
||||||
|
case DAC_ALIGN_12B_R:
|
||||||
|
/* Get DHR12R2 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
|
||||||
|
break;
|
||||||
|
case DAC_ALIGN_12B_L:
|
||||||
|
/* Get DHR12L2 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
|
||||||
|
break;
|
||||||
|
case DAC_ALIGN_8B_R:
|
||||||
|
/* Get DHR8R2 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable the DMA channel */
|
||||||
|
if(Channel == DAC_CHANNEL_1)
|
||||||
|
{
|
||||||
|
/* Enable the DMA channel */
|
||||||
|
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Enable the DMA channel */
|
||||||
|
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hdac);
|
||||||
|
|
||||||
|
/* Enable the Peripharal */
|
||||||
|
__HAL_DAC_ENABLE(hdac, Channel);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables DAC and stop conversion of channel.
|
||||||
|
* Note: For STM32F100x devices with specific feature: DMA underrun.
|
||||||
|
* On these devices, this function disables the interruption of DMA
|
||||||
|
* underrun.
|
||||||
|
* (refer to redefinition of this function in DAC extended file)
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
__weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||||
|
{
|
||||||
|
HAL_StatusTypeDef status = HAL_OK;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
|
||||||
|
/* Disable the selected DAC channel DMA request */
|
||||||
|
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1 << Channel);
|
||||||
|
|
||||||
|
/* Disable the Peripharal */
|
||||||
|
__HAL_DAC_DISABLE(hdac, Channel);
|
||||||
|
|
||||||
|
/* Disable the DMA Channel */
|
||||||
|
/* Channel1 is used */
|
||||||
|
if (Channel == DAC_CHANNEL_1)
|
||||||
|
{
|
||||||
|
status = HAL_DMA_Abort(hdac->DMA_Handle1);
|
||||||
|
}
|
||||||
|
else /* Channel2 is used for */
|
||||||
|
{
|
||||||
|
status = HAL_DMA_Abort(hdac->DMA_Handle2);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check if DMA Channel effectively disabled */
|
||||||
|
if (status != HAL_OK)
|
||||||
|
{
|
||||||
|
/* Update ADC state machine to error */
|
||||||
|
hdac->State = HAL_DAC_STATE_ERROR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the last data output value of the selected DAC channel.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||||
|
* @retval The selected DAC channel data output value.
|
||||||
|
*/
|
||||||
|
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
|
||||||
|
/* Returns the DAC channel data output register value */
|
||||||
|
if(Channel == DAC_CHANNEL_1)
|
||||||
|
{
|
||||||
|
return hdac->Instance->DOR1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return hdac->Instance->DOR2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Conversion complete callback in non blocking mode for Channel1
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Conversion half DMA transfer callback in non blocking mode for Channel1
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Error DAC callback for Channel1.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
|
||||||
|
* @brief Peripheral Control functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Peripheral Control functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..] This section provides functions allowing to:
|
||||||
|
(+) Configure channels.
|
||||||
|
(+) Set the specified data holding register value for DAC channel.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the selected DAC channel.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param sConfig: DAC configuration structure.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg1 = 0U;
|
||||||
|
|
||||||
|
/* Check the DAC parameters */
|
||||||
|
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
|
||||||
|
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
|
||||||
|
/* Process locked */
|
||||||
|
__HAL_LOCK(hdac);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Configure for the selected DAC channel: buffer output, trigger */
|
||||||
|
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||||
|
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||||
|
SET_BIT(tmpreg1, (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer));
|
||||||
|
|
||||||
|
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||||
|
/* Calculate CR register value depending on DAC_Channel */
|
||||||
|
MODIFY_REG(hdac->Instance->CR,
|
||||||
|
((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel,
|
||||||
|
tmpreg1 << Channel);
|
||||||
|
|
||||||
|
/* Disable wave generation */
|
||||||
|
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hdac);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the specified data holding register value for DAC channel.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||||
|
* @param Alignment: Specifies the data alignment.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||||
|
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||||
|
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||||
|
* @param Data: Data to be loaded in the selected data holding register.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0U;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
assert_param(IS_DAC_ALIGN(Alignment));
|
||||||
|
assert_param(IS_DAC_DATA(Data));
|
||||||
|
|
||||||
|
tmp = (uint32_t)hdac->Instance;
|
||||||
|
if(Channel == DAC_CHANNEL_1)
|
||||||
|
{
|
||||||
|
tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set the DAC channel selected data holding register */
|
||||||
|
*(__IO uint32_t *) tmp = Data;
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
|
||||||
|
* @brief Peripheral State and Errors functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Peripheral State and Errors functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection provides functions allowing to
|
||||||
|
(+) Check the DAC state.
|
||||||
|
(+) Check the DAC Errors.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief return the DAC state
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval HAL state
|
||||||
|
*/
|
||||||
|
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
/* Return DAC state */
|
||||||
|
return hdac->State;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the DAC error code
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval DAC Error Code
|
||||||
|
*/
|
||||||
|
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
|
||||||
|
{
|
||||||
|
return hdac->ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA conversion complete callback.
|
||||||
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DMA module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||||
|
|
||||||
|
HAL_DAC_ConvCpltCallbackCh1(hdac);
|
||||||
|
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA half transfer complete callback.
|
||||||
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DMA module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||||
|
/* Conversion complete callback */
|
||||||
|
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA error callback
|
||||||
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DMA module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||||
|
|
||||||
|
/* Set DAC error code to DMA error */
|
||||||
|
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||||
|
|
||||||
|
HAL_DAC_ErrorCallbackCh1(hdac);
|
||||||
|
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||||
|
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,669 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_dac_ex.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief DAC HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of DAC extension peripheral:
|
||||||
|
* + Extended features functions
|
||||||
|
*
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
(+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
|
||||||
|
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
|
||||||
|
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
|
||||||
|
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
|
||||||
|
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DACEx DACEx
|
||||||
|
* @brief DACEx driver module
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_DAC_MODULE_ENABLED
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
|
||||||
|
* @brief Extended features functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Extended features functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..] This section provides functions allowing to:
|
||||||
|
(+) Start conversion.
|
||||||
|
(+) Stop conversion.
|
||||||
|
(+) Start conversion and enable DMA transfer.
|
||||||
|
(+) Stop conversion and disable DMA transfer.
|
||||||
|
(+) Get result of conversion.
|
||||||
|
(+) Get result of dual mode conversion.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the last data output value of the selected DAC channel.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval The selected DAC channel data output value.
|
||||||
|
*/
|
||||||
|
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0U;
|
||||||
|
|
||||||
|
tmp |= hdac->Instance->DOR1;
|
||||||
|
|
||||||
|
tmp |= hdac->Instance->DOR2 << 16U;
|
||||||
|
|
||||||
|
/* Returns the DAC channel data output register value */
|
||||||
|
return tmp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the selected DAC channel wave generation.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* DAC_CHANNEL_1 / DAC_CHANNEL_2
|
||||||
|
* @param Amplitude: Select max triangle amplitude.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
|
||||||
|
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||||
|
|
||||||
|
/* Process locked */
|
||||||
|
__HAL_LOCK(hdac);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Enable the selected wave generation for the selected DAC channel */
|
||||||
|
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hdac);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the selected DAC channel wave generation.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* DAC_CHANNEL_1 / DAC_CHANNEL_2
|
||||||
|
* @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
|
||||||
|
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
|
||||||
|
|
||||||
|
/* Process locked */
|
||||||
|
__HAL_LOCK(hdac);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Enable the selected wave generation for the selected DAC channel */
|
||||||
|
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hdac);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the specified data holding register value for dual DAC channel.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Alignment: Specifies the data alignment for dual channel DAC.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||||
|
* DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||||
|
* DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||||
|
* @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
|
||||||
|
* @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
|
||||||
|
* @note In dual mode, a unique register access is required to write in both
|
||||||
|
* DAC channels at the same time.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
|
||||||
|
{
|
||||||
|
uint32_t data = 0U, tmp = 0U;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_ALIGN(Alignment));
|
||||||
|
assert_param(IS_DAC_DATA(Data1));
|
||||||
|
assert_param(IS_DAC_DATA(Data2));
|
||||||
|
|
||||||
|
/* Calculate and set dual DAC data holding register value */
|
||||||
|
if (Alignment == DAC_ALIGN_8B_R)
|
||||||
|
{
|
||||||
|
data = ((uint32_t)Data2 << 8U) | Data1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
data = ((uint32_t)Data2 << 16U) | Data1;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp = (uint32_t)hdac->Instance;
|
||||||
|
tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
|
||||||
|
|
||||||
|
/* Set the dual DAC selected data holding register */
|
||||||
|
*(__IO uint32_t *)tmp = data;
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Conversion complete callback in non blocking mode for Channel2
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Error DAC callback for Channel2.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE)
|
||||||
|
/**
|
||||||
|
* @brief DMA underrun DAC callback for channel1.
|
||||||
|
* Note: For STM32F100x devices with specific feature: DMA underrun.
|
||||||
|
* On these devices, this function uses the interruption of DMA
|
||||||
|
* underrun.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA underrun DAC callback for channel2.
|
||||||
|
* Note: For STM32F100x devices with specific feature: DMA underrun.
|
||||||
|
* On these devices, this function uses the interruption of DMA
|
||||||
|
* underrun.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdac);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
#endif /* STM32F100xB) || defined (STM32F100xE) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE)
|
||||||
|
/**
|
||||||
|
* @brief Enables DAC and starts conversion of channel.
|
||||||
|
* Note: For STM32F100x devices with specific feature: DMA underrun.
|
||||||
|
* On these devices, this function enables the interruption of DMA
|
||||||
|
* underrun.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||||
|
* @param pData: The destination peripheral Buffer address.
|
||||||
|
* @param Length: The length of data to be transferred from memory to DAC peripheral
|
||||||
|
* @param Alignment: Specifies the data alignment for DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
|
||||||
|
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
|
||||||
|
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0U;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
assert_param(IS_DAC_ALIGN(Alignment));
|
||||||
|
|
||||||
|
/* Process locked */
|
||||||
|
__HAL_LOCK(hdac);
|
||||||
|
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_BUSY;
|
||||||
|
|
||||||
|
if(Channel == DAC_CHANNEL_1)
|
||||||
|
{
|
||||||
|
/* Set the DMA transfer complete callback for channel1 */
|
||||||
|
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
|
||||||
|
|
||||||
|
/* Set the DMA half transfer complete callback for channel1 */
|
||||||
|
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
|
||||||
|
|
||||||
|
/* Set the DMA error callback for channel1 */
|
||||||
|
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
|
||||||
|
|
||||||
|
/* Enable the selected DAC channel1 DMA request */
|
||||||
|
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
|
||||||
|
|
||||||
|
/* Case of use of channel 1 */
|
||||||
|
switch(Alignment)
|
||||||
|
{
|
||||||
|
case DAC_ALIGN_12B_R:
|
||||||
|
/* Get DHR12R1 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
|
||||||
|
break;
|
||||||
|
case DAC_ALIGN_12B_L:
|
||||||
|
/* Get DHR12L1 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
|
||||||
|
break;
|
||||||
|
case DAC_ALIGN_8B_R:
|
||||||
|
/* Get DHR8R1 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Set the DMA transfer complete callback for channel2 */
|
||||||
|
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
|
||||||
|
|
||||||
|
/* Set the DMA half transfer complete callback for channel2 */
|
||||||
|
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
|
||||||
|
|
||||||
|
/* Set the DMA error callback for channel2 */
|
||||||
|
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
|
||||||
|
|
||||||
|
/* Enable the selected DAC channel2 DMA request */
|
||||||
|
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
|
||||||
|
|
||||||
|
/* Case of use of channel 2 */
|
||||||
|
switch(Alignment)
|
||||||
|
{
|
||||||
|
case DAC_ALIGN_12B_R:
|
||||||
|
/* Get DHR12R2 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
|
||||||
|
break;
|
||||||
|
case DAC_ALIGN_12B_L:
|
||||||
|
/* Get DHR12L2 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
|
||||||
|
break;
|
||||||
|
case DAC_ALIGN_8B_R:
|
||||||
|
/* Get DHR8R2 address */
|
||||||
|
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable the DMA channel */
|
||||||
|
if(Channel == DAC_CHANNEL_1)
|
||||||
|
{
|
||||||
|
/* Enable the DAC DMA underrun interrupt */
|
||||||
|
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
|
||||||
|
|
||||||
|
/* Enable the DMA channel */
|
||||||
|
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Enable the DAC DMA underrun interrupt */
|
||||||
|
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
|
||||||
|
|
||||||
|
/* Enable the DMA channel */
|
||||||
|
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable the Peripharal */
|
||||||
|
__HAL_DAC_ENABLE(hdac, Channel);
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hdac);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
#endif /* STM32F100xB) || defined (STM32F100xE) */
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE)
|
||||||
|
/**
|
||||||
|
* @brief Disables DAC and stop conversion of channel.
|
||||||
|
* Note: For STM32F100x devices with specific feature: DMA underrun.
|
||||||
|
* On these devices, this function disables the interruption of DMA
|
||||||
|
* underrun.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @param Channel: The selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
|
||||||
|
{
|
||||||
|
HAL_StatusTypeDef status = HAL_OK;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(Channel));
|
||||||
|
|
||||||
|
/* Disable the selected DAC channel DMA request */
|
||||||
|
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
|
||||||
|
|
||||||
|
/* Disable the Peripharal */
|
||||||
|
__HAL_DAC_DISABLE(hdac, Channel);
|
||||||
|
|
||||||
|
/* Disable the DMA Channel */
|
||||||
|
/* Channel1 is used */
|
||||||
|
if(Channel == DAC_CHANNEL_1)
|
||||||
|
{
|
||||||
|
/* Disable the DMA channel */
|
||||||
|
status = HAL_DMA_Abort(hdac->DMA_Handle1);
|
||||||
|
|
||||||
|
/* Disable the DAC DMA underrun interrupt */
|
||||||
|
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
|
||||||
|
}
|
||||||
|
else /* Channel2 is used for */
|
||||||
|
{
|
||||||
|
/* Disable the DMA channel */
|
||||||
|
status = HAL_DMA_Abort(hdac->DMA_Handle2);
|
||||||
|
|
||||||
|
/* Disable the DAC DMA underrun interrupt */
|
||||||
|
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check if DMA Channel effectively disabled */
|
||||||
|
if(status != HAL_OK)
|
||||||
|
{
|
||||||
|
/* Update ADC state machine to error */
|
||||||
|
hdac->State = HAL_DAC_STATE_ERROR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Change DAC state */
|
||||||
|
hdac->State = HAL_DAC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
#endif /* STM32F100xB) || defined (STM32F100xE) */
|
||||||
|
|
||||||
|
#if defined (STM32F100xB) || defined (STM32F100xE)
|
||||||
|
/**
|
||||||
|
* @brief Handles DAC interrupt request
|
||||||
|
* Note: For STM32F100x devices with specific feature: DMA underrun.
|
||||||
|
* On these devices, this function uses the interruption of DMA
|
||||||
|
* underrun.
|
||||||
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DAC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
|
||||||
|
{
|
||||||
|
|
||||||
|
if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
|
||||||
|
{
|
||||||
|
/* Check underrun flag of DAC channel 1 */
|
||||||
|
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
|
||||||
|
{
|
||||||
|
/* Change DAC state to error state */
|
||||||
|
hdac->State = HAL_DAC_STATE_ERROR;
|
||||||
|
|
||||||
|
/* Set DAC error code to chanel1 DMA underrun error */
|
||||||
|
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
|
||||||
|
|
||||||
|
/* Clear the underrun flag */
|
||||||
|
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
|
||||||
|
|
||||||
|
/* Disable the selected DAC channel1 DMA request */
|
||||||
|
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
|
||||||
|
|
||||||
|
/* Error callback */
|
||||||
|
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
|
||||||
|
{
|
||||||
|
/* Check underrun flag of DAC channel 2 */
|
||||||
|
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
|
||||||
|
{
|
||||||
|
/* Change DAC state to error state */
|
||||||
|
hdac->State = HAL_DAC_STATE_ERROR;
|
||||||
|
|
||||||
|
/* Set DAC error code to channel2 DMA underrun error */
|
||||||
|
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
|
||||||
|
|
||||||
|
/* Clear the underrun flag */
|
||||||
|
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
|
||||||
|
|
||||||
|
/* Disable the selected DAC channel1 DMA request */
|
||||||
|
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
|
||||||
|
|
||||||
|
/* Error callback */
|
||||||
|
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* STM32F100xB || STM32F100xE */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DACEx_Private_Functions DACEx Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA conversion complete callback.
|
||||||
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DMA module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||||
|
|
||||||
|
HAL_DACEx_ConvCpltCallbackCh2(hdac);
|
||||||
|
|
||||||
|
hdac->State= HAL_DAC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA half transfer complete callback.
|
||||||
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DMA module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||||
|
/* Conversion complete callback */
|
||||||
|
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA error callback
|
||||||
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified DMA module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
||||||
|
|
||||||
|
/* Set DAC error code to DMA error */
|
||||||
|
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
|
||||||
|
|
||||||
|
HAL_DACEx_ErrorCallbackCh2(hdac);
|
||||||
|
|
||||||
|
hdac->State= HAL_DAC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
||||||
|
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
2043
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c
Normal file
2043
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c
Normal file
File diff suppressed because it is too large
Load Diff
1196
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c
Normal file
1196
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c
Normal file
File diff suppressed because it is too large
Load Diff
5575
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c
Normal file
5575
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
1460
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c
Normal file
1460
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,258 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_iwdg.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief IWDG HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the Independent Watchdog (IWDG) peripheral:
|
||||||
|
* + Initialization and Start functions
|
||||||
|
* + IO operation functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### IWDG Generic features #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
(+) The IWDG can be started by either software or hardware (configurable
|
||||||
|
through option byte).
|
||||||
|
|
||||||
|
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
|
||||||
|
if the main clock fails.
|
||||||
|
|
||||||
|
(+) Once the IWDG is started, the LSI is forced ON and both can not be
|
||||||
|
disabled. The counter starts counting down from the reset value (0xFFF).
|
||||||
|
When it reaches the end of count value (0x000) a reset signal is
|
||||||
|
generated (IWDG reset).
|
||||||
|
|
||||||
|
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
|
||||||
|
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
|
||||||
|
prevented.
|
||||||
|
|
||||||
|
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||||
|
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||||
|
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||||
|
reset occurs.
|
||||||
|
|
||||||
|
(+) Debug mode : When the microcontroller enters debug mode (core halted),
|
||||||
|
the IWDG counter either continues to work normally or stops, depending
|
||||||
|
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
|
||||||
|
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
|
||||||
|
|
||||||
|
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
|
||||||
|
The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
|
||||||
|
devices provide the capability to measure the LSI frequency (LSI clock
|
||||||
|
connected internally to TIM5 CH4 input capture). The measured value
|
||||||
|
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||||
|
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
(#) Use IWDG using HAL_IWDG_Init() function to :
|
||||||
|
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
|
||||||
|
clock is forced ON and IWDG counter starts downcounting.
|
||||||
|
(++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
|
||||||
|
(++) Configure the IWDG prescaler and counter reload value. This reload
|
||||||
|
value will be loaded in the IWDG counter each time the watchdog is
|
||||||
|
reloaded, then the IWDG will start counting down from this value.
|
||||||
|
(++) wait for status flags to be reset"
|
||||||
|
|
||||||
|
(#) Then the application program must refresh the IWDG counter at regular
|
||||||
|
intervals during normal operation to prevent an MCU reset, using
|
||||||
|
HAL_IWDG_Refresh() function.
|
||||||
|
|
||||||
|
*** IWDG HAL driver macros list ***
|
||||||
|
====================================
|
||||||
|
[..]
|
||||||
|
Below the list of most used macros in IWDG HAL driver:
|
||||||
|
(+) __HAL_IWDG_START: Enable the IWDG peripheral
|
||||||
|
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
|
||||||
|
the reload register
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||||
|
/** @defgroup IWDG IWDG
|
||||||
|
* @brief IWDG HAL module driver.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
|
||||||
|
higher prescaler (256), and according to HSI variation, we need to wait at
|
||||||
|
least 6 cycles so 48 ms. */
|
||||||
|
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup IWDG_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup IWDG_Exported_Functions_Group1
|
||||||
|
* @brief Initialization and Start functions.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### Initialization and Start functions #####
|
||||||
|
===============================================================================
|
||||||
|
[..] This section provides functions allowing to:
|
||||||
|
(+) Initialize the IWDG according to the specified parameters in the
|
||||||
|
IWDG_InitTypeDef of associated handle.
|
||||||
|
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
|
||||||
|
is reloaded in order to exit function with correct time base.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the IWDG according to the specified parameters in the
|
||||||
|
* IWDG_InitTypeDef and start watchdog. Before exiting function,
|
||||||
|
* watchdog is refreshed in order to have correct time base.
|
||||||
|
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified IWDG module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
||||||
|
{
|
||||||
|
uint32_t tickstart;
|
||||||
|
|
||||||
|
/* Check the IWDG handle allocation */
|
||||||
|
if(hiwdg == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
|
||||||
|
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
|
||||||
|
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
|
||||||
|
|
||||||
|
/* Enable IWDG. LSI is turned on automaticaly */
|
||||||
|
__HAL_IWDG_START(hiwdg);
|
||||||
|
|
||||||
|
/* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
|
||||||
|
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
|
||||||
|
|
||||||
|
/* Write to IWDG registers the Prescaler & Reload values to work with */
|
||||||
|
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
|
||||||
|
hiwdg->Instance->RLR = hiwdg->Init.Reload;
|
||||||
|
|
||||||
|
/* Check pending flag, if previous update not done, return timeout */
|
||||||
|
tickstart = HAL_GetTick();
|
||||||
|
|
||||||
|
/* Wait for register to be updated */
|
||||||
|
while(hiwdg->Instance->SR != RESET)
|
||||||
|
{
|
||||||
|
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||||
|
{
|
||||||
|
return HAL_TIMEOUT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Reload IWDG counter with value defined in the reload register */
|
||||||
|
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||||
|
* @brief IO operation functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### IO operation functions #####
|
||||||
|
===============================================================================
|
||||||
|
[..] This section provides functions allowing to:
|
||||||
|
(+) Refresh the IWDG.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Refresh the IWDG.
|
||||||
|
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified IWDG module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
||||||
|
{
|
||||||
|
/* Reload IWDG counter with value defined in the reload register */
|
||||||
|
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
2598
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_mmc.c
Normal file
2598
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_mmc.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,111 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_msp_template.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief HAL BSP module.
|
||||||
|
* This file template is located in the HAL folder and should be copied
|
||||||
|
* to the user folder.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_MSP HAL_MSP
|
||||||
|
* @brief HAL MSP module.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_MSP_Exported_Functions HAL MSP Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the Global MSP.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_MspInit(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DeInitializes the Global MSP.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_MspDeInit(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the PPP MSP.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_PPP_MspInit(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DeInitializes the PPP MSP.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_PPP_MspDeInit(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
1060
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c
Normal file
1060
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,748 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_pccard.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief PCCARD HAL module driver.
|
||||||
|
* This file provides a generic firmware to drive PCCARD memories mounted
|
||||||
|
* as external device.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
===============================================================================
|
||||||
|
[..]
|
||||||
|
This driver is a generic layered driver which contains a set of APIs used to
|
||||||
|
control PCCARD/compact flash memories. It uses the FSMC/FSMC layer functions
|
||||||
|
to interface with PCCARD devices. This driver is used for:
|
||||||
|
|
||||||
|
(+) PCCARD/compact flash memory configuration sequence using the function
|
||||||
|
HAL_PCCARD_Init() with control and timing parameters for both common and
|
||||||
|
attribute spaces.
|
||||||
|
|
||||||
|
(+) Read PCCARD/compact flash memory maker and device IDs using the function
|
||||||
|
HAL_PCCARD_Read_ID(). The read information is stored in the CompactFlash_ID
|
||||||
|
structure declared by the function caller.
|
||||||
|
|
||||||
|
(+) Access PCCARD/compact flash memory by read/write operations using the functions
|
||||||
|
HAL_PCCARD_Read_Sector()/HAL_PCCARD_Write_Sector(), to read/write sector.
|
||||||
|
|
||||||
|
(+) Perform PCCARD/compact flash Reset chip operation using the function HAL_PCCARD_Reset().
|
||||||
|
|
||||||
|
(+) Perform PCCARD/compact flash erase sector operation using the function
|
||||||
|
HAL_PCCARD_Erase_Sector().
|
||||||
|
|
||||||
|
(+) Read the PCCARD/compact flash status operation using the function HAL_PCCARD_ReadStatus().
|
||||||
|
|
||||||
|
(+) You can monitor the PCCARD/compact flash device HAL state by calling the function
|
||||||
|
HAL_PCCARD_GetState()
|
||||||
|
|
||||||
|
[..]
|
||||||
|
(@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
|
||||||
|
operations. If a PCCARD/compact flash device contains different operations
|
||||||
|
and/or implementations, it should be implemented separately.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||||
|
#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
|
||||||
|
|
||||||
|
/** @defgroup PCCARD PCCARD
|
||||||
|
* @brief PCCARD HAL module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PCCARD_TIMEOUT_READ_ID 0x0000FFFFU
|
||||||
|
#define PCCARD_TIMEOUT_SECTOR 0x0000FFFFU
|
||||||
|
#define PCCARD_TIMEOUT_STATUS 0x01000000U
|
||||||
|
|
||||||
|
#define PCCARD_STATUS_OK (uint8_t)0x58
|
||||||
|
#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### PCCARD Initialization and de-initialization functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This section provides functions allowing to initialize/de-initialize
|
||||||
|
the PCCARD memory
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Perform the PCCARD memory Initialization sequence
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @param ComSpaceTiming: Common space timing structure
|
||||||
|
* @param AttSpaceTiming: Attribute space timing structure
|
||||||
|
* @param IOSpaceTiming: IO space timing structure
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
|
||||||
|
{
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
if(hpccard == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(hpccard->State == HAL_PCCARD_STATE_RESET)
|
||||||
|
{
|
||||||
|
/* Allocate lock resource and initialize it */
|
||||||
|
hpccard->Lock = HAL_UNLOCKED;
|
||||||
|
|
||||||
|
/* Initialize the low level hardware (MSP) */
|
||||||
|
HAL_PCCARD_MspInit(hpccard);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Initialize the PCCARD state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Initialize PCCARD control Interface */
|
||||||
|
FSMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
|
||||||
|
|
||||||
|
/* Init PCCARD common space timing Interface */
|
||||||
|
FSMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
|
||||||
|
|
||||||
|
/* Init PCCARD attribute space timing Interface */
|
||||||
|
FSMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
|
||||||
|
|
||||||
|
/* Init PCCARD IO space timing Interface */
|
||||||
|
FSMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
|
||||||
|
|
||||||
|
/* Enable the PCCARD device */
|
||||||
|
__FSMC_PCCARD_ENABLE(hpccard->Instance);
|
||||||
|
|
||||||
|
/* Update the PCCARD state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Perform the PCCARD memory De-initialization sequence
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
|
||||||
|
{
|
||||||
|
/* De-Initialize the low level hardware (MSP) */
|
||||||
|
HAL_PCCARD_MspDeInit(hpccard);
|
||||||
|
|
||||||
|
/* Configure the PCCARD registers with their reset values */
|
||||||
|
FSMC_PCCARD_DeInit(hpccard->Instance);
|
||||||
|
|
||||||
|
/* Update the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_RESET;
|
||||||
|
|
||||||
|
/* Release Lock */
|
||||||
|
__HAL_UNLOCK(hpccard);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PCCARD MSP Init
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hpccard);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_PCCARD_MspInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PCCARD MSP DeInit
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hpccard);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_PCCARD_MspDeInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
|
||||||
|
* @brief Input Output and memory control functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### PCCARD Input Output and memory functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This section provides functions allowing to use and control the PCCARD memory
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read Compact Flash's ID.
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @param CompactFlash_ID: Compact flash ID structure.
|
||||||
|
* @param pStatus: pointer to compact flash status
|
||||||
|
* @retval HAL status
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
|
||||||
|
{
|
||||||
|
uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
|
||||||
|
uint8_t status = 0U;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hpccard);
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Initialize the CF status */
|
||||||
|
*pStatus = PCCARD_READY;
|
||||||
|
|
||||||
|
/* Send the Identify Command */
|
||||||
|
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECECU;
|
||||||
|
|
||||||
|
/* Read CF IDs and timeout treatment */
|
||||||
|
do
|
||||||
|
{
|
||||||
|
/* Read the CF status */
|
||||||
|
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
|
||||||
|
timeout--;
|
||||||
|
}while((status != PCCARD_STATUS_OK) && timeout);
|
||||||
|
|
||||||
|
if(timeout == 0U)
|
||||||
|
{
|
||||||
|
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Read CF ID bytes */
|
||||||
|
for(index = 0U; index < 16U; index++)
|
||||||
|
{
|
||||||
|
CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hpccard);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read sector from PCCARD memory
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @param pBuffer: pointer to destination read buffer
|
||||||
|
* @param SectorAddress: Sector address to read
|
||||||
|
* @param pStatus: pointer to CF status
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
|
||||||
|
{
|
||||||
|
uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
|
||||||
|
uint8_t status = 0U;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hpccard);
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Initialize CF status */
|
||||||
|
*pStatus = PCCARD_READY;
|
||||||
|
|
||||||
|
/* Set the parameters to write a sector */
|
||||||
|
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
|
||||||
|
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
|
||||||
|
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
/* wait till the Status = 0x80 */
|
||||||
|
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
timeout--;
|
||||||
|
}while((status == 0x80U) && timeout);
|
||||||
|
|
||||||
|
if(timeout == 0U)
|
||||||
|
{
|
||||||
|
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
timeout = 0xFFFFU;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
/* wait till the Status = PCCARD_STATUS_OK */
|
||||||
|
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
timeout--;
|
||||||
|
}while((status != PCCARD_STATUS_OK) && timeout);
|
||||||
|
|
||||||
|
if(timeout == 0U)
|
||||||
|
{
|
||||||
|
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Read bytes */
|
||||||
|
for(; index < PCCARD_SECTOR_SIZE; index++)
|
||||||
|
{
|
||||||
|
*(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hpccard);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write sector to PCCARD memory
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @param pBuffer: pointer to source write buffer
|
||||||
|
* @param SectorAddress: Sector address to write
|
||||||
|
* @param pStatus: pointer to CF status
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
|
||||||
|
{
|
||||||
|
uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
|
||||||
|
uint8_t status = 0U;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hpccard);
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Initialize CF status */
|
||||||
|
*pStatus = PCCARD_READY;
|
||||||
|
|
||||||
|
/* Set the parameters to write a sector */
|
||||||
|
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
|
||||||
|
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
|
||||||
|
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
/* Wait till the Status = PCCARD_STATUS_OK */
|
||||||
|
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
timeout--;
|
||||||
|
}while((status != PCCARD_STATUS_OK) && timeout);
|
||||||
|
|
||||||
|
if(timeout == 0U)
|
||||||
|
{
|
||||||
|
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Write bytes */
|
||||||
|
for(; index < PCCARD_SECTOR_SIZE; index++)
|
||||||
|
{
|
||||||
|
*(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
|
||||||
|
}
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
/* Wait till the Status = PCCARD_STATUS_WRITE_OK */
|
||||||
|
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
timeout--;
|
||||||
|
}while((status != PCCARD_STATUS_WRITE_OK) && timeout);
|
||||||
|
|
||||||
|
if(timeout == 0U)
|
||||||
|
{
|
||||||
|
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hpccard);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Erase sector from PCCARD memory
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @param SectorAddress: Sector address to erase
|
||||||
|
* @param pStatus: pointer to CF status
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
|
||||||
|
{
|
||||||
|
uint32_t timeout = 0x400U;
|
||||||
|
uint8_t status = 0;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hpccard);
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Initialize CF status */
|
||||||
|
*pStatus = PCCARD_READY;
|
||||||
|
|
||||||
|
/* Set the parameters to write a sector */
|
||||||
|
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00;
|
||||||
|
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
|
||||||
|
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
|
||||||
|
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01;
|
||||||
|
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0;
|
||||||
|
*(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD;
|
||||||
|
|
||||||
|
/* wait till the CF is ready */
|
||||||
|
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
|
||||||
|
while((status != PCCARD_STATUS_WRITE_OK) && timeout)
|
||||||
|
{
|
||||||
|
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
timeout--;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(timeout == 0U)
|
||||||
|
{
|
||||||
|
*pStatus = PCCARD_TIMEOUT_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hpccard);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset the PCCARD memory
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hpccard);
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||||
|
{
|
||||||
|
return HAL_BUSY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Provide an SW reset and Read and verify the:
|
||||||
|
- CF Configuration Option Register at address 0x98000200 --> 0x80
|
||||||
|
- Card Configuration and Status Register at address 0x98000202 --> 0x00
|
||||||
|
- Pin Replacement Register at address 0x98000204 --> 0x0C
|
||||||
|
- Socket and Copy Register at address 0x98000206 --> 0x00
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_BUSY;
|
||||||
|
|
||||||
|
*(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
hpccard->State = HAL_PCCARD_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hpccard);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles PCCARD device interrupt request.
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
|
||||||
|
{
|
||||||
|
/* Check PCCARD interrupt Rising edge flag */
|
||||||
|
if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE))
|
||||||
|
{
|
||||||
|
/* PCCARD interrupt callback*/
|
||||||
|
HAL_PCCARD_ITCallback(hpccard);
|
||||||
|
|
||||||
|
/* Clear PCCARD interrupt Rising edge pending bit */
|
||||||
|
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check PCCARD interrupt Level flag */
|
||||||
|
if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL))
|
||||||
|
{
|
||||||
|
/* PCCARD interrupt callback*/
|
||||||
|
HAL_PCCARD_ITCallback(hpccard);
|
||||||
|
|
||||||
|
/* Clear PCCARD interrupt Level pending bit */
|
||||||
|
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check PCCARD interrupt Falling edge flag */
|
||||||
|
if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE))
|
||||||
|
{
|
||||||
|
/* PCCARD interrupt callback*/
|
||||||
|
HAL_PCCARD_ITCallback(hpccard);
|
||||||
|
|
||||||
|
/* Clear PCCARD interrupt Falling edge pending bit */
|
||||||
|
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check PCCARD interrupt FIFO empty flag */
|
||||||
|
if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT))
|
||||||
|
{
|
||||||
|
/* PCCARD interrupt callback*/
|
||||||
|
HAL_PCCARD_ITCallback(hpccard);
|
||||||
|
|
||||||
|
/* Clear PCCARD interrupt FIFO empty pending bit */
|
||||||
|
__FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PCCARD interrupt feature callback
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hpccard);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_PCCARD_ITCallback could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
|
||||||
|
* @brief Peripheral State functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### PCCARD Peripheral State functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection permits to get in run-time the status of the PCCARD controller
|
||||||
|
and the data flow.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief return the PCCARD controller state
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @retval HAL state
|
||||||
|
*/
|
||||||
|
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
|
||||||
|
{
|
||||||
|
return hpccard->State;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the compact flash memory status
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @retval New status of the CF operation. This parameter can be:
|
||||||
|
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
|
||||||
|
* a Timeout error
|
||||||
|
* - CompactFlash_READY: when memory is ready for the next operation
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
|
||||||
|
{
|
||||||
|
uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0;
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||||
|
{
|
||||||
|
return HAL_PCCARD_STATUS_ONGOING;
|
||||||
|
}
|
||||||
|
|
||||||
|
status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
|
||||||
|
while((status_cf == PCCARD_BUSY) && timeout)
|
||||||
|
{
|
||||||
|
status_cf = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
timeout--;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(timeout == 0U)
|
||||||
|
{
|
||||||
|
status_cf = PCCARD_TIMEOUT_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return the operation status */
|
||||||
|
return (HAL_PCCARD_StatusTypeDef) status_cf;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads the Compact Flash memory status using the Read status command
|
||||||
|
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for PCCARD module.
|
||||||
|
* @retval The status of the Compact Flash memory. This parameter can be:
|
||||||
|
* - CompactFlash_BUSY: when memory is busy
|
||||||
|
* - CompactFlash_READY: when memory is ready for the next operation
|
||||||
|
* - CompactFlash_ERROR: when the previous operation gererates error
|
||||||
|
*/
|
||||||
|
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
|
||||||
|
{
|
||||||
|
uint8_t data = 0U, status_cf = PCCARD_BUSY;
|
||||||
|
|
||||||
|
/* Check the PCCARD controller state */
|
||||||
|
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
|
||||||
|
{
|
||||||
|
return HAL_PCCARD_STATUS_ONGOING;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Read status operation */
|
||||||
|
data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
|
||||||
|
|
||||||
|
if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
|
||||||
|
{
|
||||||
|
status_cf = PCCARD_TIMEOUT_ERROR;
|
||||||
|
}
|
||||||
|
else if((data & PCCARD_READY) == PCCARD_READY)
|
||||||
|
{
|
||||||
|
status_cf = PCCARD_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (HAL_PCCARD_StatusTypeDef) status_cf;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
||||||
|
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
1426
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c
Normal file
1426
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,252 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_pcd_ex.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Extended PCD HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the USB Peripheral Controller:
|
||||||
|
* + Extended features functions: Update FIFO configuration,
|
||||||
|
* PMA configuration for EPs
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_PCD_MODULE_ENABLED
|
||||||
|
|
||||||
|
#if defined(STM32F102x6) || defined(STM32F102xB) || \
|
||||||
|
defined(STM32F103x6) || defined(STM32F103xB) || \
|
||||||
|
defined(STM32F103xE) || defined(STM32F103xG) || \
|
||||||
|
defined(STM32F105xC) || defined(STM32F107xC)
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup PCDEx PCDEx
|
||||||
|
* @brief PCD Extended HAL module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||||
|
* @brief PCDEx control functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### Extended Peripheral Control functions #####
|
||||||
|
===============================================================================
|
||||||
|
[..] This section provides functions allowing to:
|
||||||
|
(+) Update FIFO (USB_OTG_FS)
|
||||||
|
(+) Update PMA configuration (USB)
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (USB_OTG_FS)
|
||||||
|
/**
|
||||||
|
* @brief Set Tx FIFO
|
||||||
|
* @param hpcd: PCD handle
|
||||||
|
* @param fifo: The number of Tx fifo
|
||||||
|
* @param size: Fifo size
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
|
||||||
|
{
|
||||||
|
uint8_t index = 0;
|
||||||
|
uint32_t Tx_Offset = 0U;
|
||||||
|
|
||||||
|
/* TXn min size = 16 words. (n : Transmit FIFO index)
|
||||||
|
When a TxFIFO is not used, the Configuration should be as follows:
|
||||||
|
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||||
|
--> Txm can use the space allocated for Txn.
|
||||||
|
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||||
|
--> Txn should be configured with the minimum space of 16 words
|
||||||
|
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
||||||
|
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
||||||
|
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
||||||
|
|
||||||
|
Tx_Offset = hpcd->Instance->GRXFSIZ;
|
||||||
|
|
||||||
|
if(fifo == 0U)
|
||||||
|
{
|
||||||
|
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16U) | Tx_Offset;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
|
||||||
|
for(index = 0; index < (fifo - 1); index++)
|
||||||
|
{
|
||||||
|
Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16U);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Multiply Tx_Size by 2 to get higher performance */
|
||||||
|
hpcd->Instance->DIEPTXF[fifo - 1U] = (size << 16U) | Tx_Offset;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Rx FIFO
|
||||||
|
* @param hpcd: PCD handle
|
||||||
|
* @param size: Size of Rx fifo
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
|
||||||
|
{
|
||||||
|
hpcd->Instance->GRXFSIZ = size;
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
#endif /* USB_OTG_FS */
|
||||||
|
|
||||||
|
#if defined (USB)
|
||||||
|
/**
|
||||||
|
* @brief Configure PMA for EP
|
||||||
|
* @param hpcd : Device instance
|
||||||
|
* @param ep_addr: endpoint address
|
||||||
|
* @param ep_kind: endpoint Kind
|
||||||
|
* USB_SNG_BUF: Single Buffer used
|
||||||
|
* USB_DBL_BUF: Double Buffer used
|
||||||
|
* @param pmaadress: EP address in The PMA: In case of single buffer endpoint
|
||||||
|
* this parameter is 16-bit value providing the address
|
||||||
|
* in PMA allocated to endpoint.
|
||||||
|
* In case of double buffer endpoint this parameter
|
||||||
|
* is a 32-bit value providing the endpoint buffer 0 address
|
||||||
|
* in the LSB part of 32-bit value and endpoint buffer 1 address
|
||||||
|
* in the MSB part of 32-bit value.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
|
||||||
|
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
|
||||||
|
uint16_t ep_addr,
|
||||||
|
uint16_t ep_kind,
|
||||||
|
uint32_t pmaadress)
|
||||||
|
|
||||||
|
{
|
||||||
|
PCD_EPTypeDef *ep = NULL;
|
||||||
|
|
||||||
|
/* initialize ep structure*/
|
||||||
|
if ((ep_addr & 0x80U) == 0x80U)
|
||||||
|
{
|
||||||
|
ep = &hpcd->IN_ep[ep_addr & 0x7FU];
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ep = &hpcd->OUT_ep[ep_addr];
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Here we check if the endpoint is single or double Buffer*/
|
||||||
|
if (ep_kind == PCD_SNG_BUF)
|
||||||
|
{
|
||||||
|
/*Single Buffer*/
|
||||||
|
ep->doublebuffer = 0U;
|
||||||
|
/*Configure te PMA*/
|
||||||
|
ep->pmaadress = (uint16_t)pmaadress;
|
||||||
|
}
|
||||||
|
else /*USB_DBL_BUF*/
|
||||||
|
{
|
||||||
|
/*Double Buffer Endpoint*/
|
||||||
|
ep->doublebuffer = 1U;
|
||||||
|
/*Configure the PMA*/
|
||||||
|
ep->pmaaddr0 = pmaadress & 0x0000FFFFU;
|
||||||
|
ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U;
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
#endif /* USB */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PCDEx_Exported_Functions_Group2 Peripheral State functions
|
||||||
|
* @brief Manage device connection state
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief Software Device Connection,
|
||||||
|
* this function is not required by USB OTG FS peripheral, it is used
|
||||||
|
* only by USB Device FS peripheral.
|
||||||
|
* @param hpcd: PCD handle
|
||||||
|
* @param state: connection state (0 : disconnected / 1: connected)
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hpcd);
|
||||||
|
UNUSED(state);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_PCDEx_SetConnectionState could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F102x6 || STM32F102xB || */
|
||||||
|
/* STM32F103x6 || STM32F103xB || */
|
||||||
|
/* STM32F103xE || STM32F103xG || */
|
||||||
|
/* STM32F105xC || STM32F107xC */
|
||||||
|
|
||||||
|
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
1720
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c
Normal file
1720
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,593 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_rtc_ex.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Extended RTC HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the Real Time Clock (RTC) Extension peripheral:
|
||||||
|
* + RTC Tamper functions
|
||||||
|
* + Extension Control functions
|
||||||
|
* + Extension RTC features functions
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_RTC_MODULE_ENABLED
|
||||||
|
|
||||||
|
/** @defgroup RTCEx RTCEx
|
||||||
|
* @brief RTC Extended HAL module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTCEx_Exported_Functions_Group1 RTC Tamper functions
|
||||||
|
* @brief RTC Tamper functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### RTC Tamper functions #####
|
||||||
|
===============================================================================
|
||||||
|
|
||||||
|
[..] This section provides functions allowing to configure Tamper feature
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets Tamper
|
||||||
|
* @note By calling this API we disable the tamper interrupt for all tampers.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @param sTamper: Pointer to Tamper Structure.
|
||||||
|
* @note Tamper can be enabled only if ASOE and CCO bit are reset
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
|
||||||
|
{
|
||||||
|
/* Check input parameters */
|
||||||
|
if((hrtc == NULL) || (sTamper == NULL))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
|
||||||
|
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hrtc);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||||
|
|
||||||
|
if (HAL_IS_BIT_SET(BKP->RTCCR,(BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
|
||||||
|
{
|
||||||
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hrtc);
|
||||||
|
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hrtc);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets Tamper with interrupt.
|
||||||
|
* @note By calling this API we force the tamper interrupt for all tampers.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @param sTamper: Pointer to RTC Tamper.
|
||||||
|
* @note Tamper can be enabled only if ASOE and CCO bit are reset
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
|
||||||
|
{
|
||||||
|
/* Check input parameters */
|
||||||
|
if((hrtc == NULL) || (sTamper == NULL))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
|
||||||
|
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hrtc);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||||
|
|
||||||
|
if (HAL_IS_BIT_SET(BKP->RTCCR,(BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
|
||||||
|
{
|
||||||
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hrtc);
|
||||||
|
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
|
||||||
|
|
||||||
|
/* Configure the Tamper Interrupt in the BKP->CSR */
|
||||||
|
__HAL_RTC_TAMPER_ENABLE_IT(hrtc, RTC_IT_TAMP1);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hrtc);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deactivates Tamper.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @param Tamper: Selected tamper pin.
|
||||||
|
* This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
|
||||||
|
{
|
||||||
|
/* Check input parameters */
|
||||||
|
if(hrtc == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(Tamper);
|
||||||
|
|
||||||
|
assert_param(IS_RTC_TAMPER(Tamper));
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hrtc);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Disable the selected Tamper pin */
|
||||||
|
CLEAR_BIT(BKP->CR, BKP_CR_TPE);
|
||||||
|
|
||||||
|
/* Disable the Tamper Interrupt in the BKP->CSR */
|
||||||
|
/* Configure the Tamper Interrupt in the BKP->CSR */
|
||||||
|
__HAL_RTC_TAMPER_DISABLE_IT(hrtc, RTC_IT_TAMP1);
|
||||||
|
|
||||||
|
/* Clear the Tamper interrupt pending bit */
|
||||||
|
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
|
||||||
|
SET_BIT(BKP->CSR, BKP_CSR_CTE);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hrtc);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles Tamper interrupt request.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
|
||||||
|
{
|
||||||
|
/* Get the status of the Interrupt */
|
||||||
|
if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP1))
|
||||||
|
{
|
||||||
|
/* Get the TAMPER Interrupt enable bit and pending bit */
|
||||||
|
if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* Tamper callback */
|
||||||
|
HAL_RTCEx_Tamper1EventCallback(hrtc);
|
||||||
|
|
||||||
|
/* Clear the Tamper interrupt pending bit */
|
||||||
|
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Change RTC state */
|
||||||
|
hrtc->State = HAL_RTC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Tamper 1 callback.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hrtc);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles Tamper1 Polling.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @param Timeout: Timeout duration
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
|
||||||
|
{
|
||||||
|
uint32_t tickstart = HAL_GetTick();
|
||||||
|
|
||||||
|
/* Check input parameters */
|
||||||
|
if(hrtc == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get the status of the Interrupt */
|
||||||
|
while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
|
||||||
|
{
|
||||||
|
if(Timeout != HAL_MAX_DELAY)
|
||||||
|
{
|
||||||
|
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||||
|
{
|
||||||
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
||||||
|
return HAL_TIMEOUT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear the Tamper Flag */
|
||||||
|
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
|
||||||
|
|
||||||
|
/* Change RTC state */
|
||||||
|
hrtc->State = HAL_RTC_STATE_READY;
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTCEx_Exported_Functions_Group2 RTC Second functions
|
||||||
|
* @brief RTC Second functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### RTC Second functions #####
|
||||||
|
===============================================================================
|
||||||
|
|
||||||
|
[..] This section provides functions implementing second interupt handlers
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets Interrupt for second
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc)
|
||||||
|
{
|
||||||
|
/* Check input parameters */
|
||||||
|
if(hrtc == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hrtc);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Enable Second interuption */
|
||||||
|
__HAL_RTC_SECOND_ENABLE_IT(hrtc, RTC_IT_SEC);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hrtc);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deactivates Second.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc)
|
||||||
|
{
|
||||||
|
/* Check input parameters */
|
||||||
|
if(hrtc == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hrtc);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Deactivate Second interuption*/
|
||||||
|
__HAL_RTC_SECOND_DISABLE_IT(hrtc, RTC_IT_SEC);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hrtc);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles second interrupt request.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef* hrtc)
|
||||||
|
{
|
||||||
|
if(__HAL_RTC_SECOND_GET_IT_SOURCE(hrtc, RTC_IT_SEC))
|
||||||
|
{
|
||||||
|
/* Get the status of the Interrupt */
|
||||||
|
if(__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_SEC))
|
||||||
|
{
|
||||||
|
/* Check if Overrun occurred */
|
||||||
|
if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_OW))
|
||||||
|
{
|
||||||
|
/* Second error callback */
|
||||||
|
HAL_RTCEx_RTCEventErrorCallback(hrtc);
|
||||||
|
|
||||||
|
/* Clear flag Second */
|
||||||
|
__HAL_RTC_OVERFLOW_CLEAR_FLAG(hrtc, RTC_FLAG_OW);
|
||||||
|
|
||||||
|
/* Change RTC state */
|
||||||
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Second callback */
|
||||||
|
HAL_RTCEx_RTCEventCallback(hrtc);
|
||||||
|
|
||||||
|
/* Change RTC state */
|
||||||
|
hrtc->State = HAL_RTC_STATE_READY;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear flag Second */
|
||||||
|
__HAL_RTC_SECOND_CLEAR_FLAG(hrtc, RTC_FLAG_SEC);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Second event callback.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hrtc);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_RTCEx_RTCEventCallback could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Second event error callback.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hrtc);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_RTCEx_RTCEventErrorCallback could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
|
||||||
|
* @brief Extended Peripheral Control functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### Extension Peripheral Control functions #####
|
||||||
|
===============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection provides functions allowing to
|
||||||
|
(+) Writes a data in a specified RTC Backup data register
|
||||||
|
(+) Read a data in a specified RTC Backup data register
|
||||||
|
(+) Sets the Smooth calibration parameters.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes a data in a specified RTC Backup data register.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @param BackupRegister: RTC Backup data Register number.
|
||||||
|
* This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
|
||||||
|
* specify the register (depending devices).
|
||||||
|
* @param Data: Data to be written in the specified RTC Backup data register.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0U;
|
||||||
|
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hrtc);
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_BKP(BackupRegister));
|
||||||
|
|
||||||
|
tmp = (uint32_t)BKP_BASE;
|
||||||
|
tmp += (BackupRegister * 4U);
|
||||||
|
|
||||||
|
*(__IO uint32_t *) tmp = (Data & BKP_DR1_D);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads data from the specified RTC Backup data Register.
|
||||||
|
* @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for RTC.
|
||||||
|
* @param BackupRegister: RTC Backup data Register number.
|
||||||
|
* This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
|
||||||
|
* specify the register (depending devices).
|
||||||
|
* @retval Read value
|
||||||
|
*/
|
||||||
|
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
|
||||||
|
{
|
||||||
|
uint32_t backupregister = 0U;
|
||||||
|
uint32_t pvalue = 0U;
|
||||||
|
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hrtc);
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_BKP(BackupRegister));
|
||||||
|
|
||||||
|
backupregister = (uint32_t)BKP_BASE;
|
||||||
|
backupregister += (BackupRegister * 4U);
|
||||||
|
|
||||||
|
pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D;
|
||||||
|
|
||||||
|
/* Read the specified register */
|
||||||
|
return pvalue;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the Smooth calibration parameters.
|
||||||
|
* @param hrtc: RTC handle
|
||||||
|
* @param SmoothCalibPeriod: Not used (only present for compatibility with another families)
|
||||||
|
* @param SmoothCalibPlusPulses: Not used (only present for compatibility with another families)
|
||||||
|
* @param SmouthCalibMinusPulsesValue: specifies the RTC Clock Calibration value.
|
||||||
|
* This parameter must be a number between 0 and 0x7F.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
|
||||||
|
{
|
||||||
|
/* Check input parameters */
|
||||||
|
if(hrtc == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(SmoothCalibPeriod);
|
||||||
|
UNUSED(SmoothCalibPlusPulses);
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hrtc);
|
||||||
|
|
||||||
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Sets RTC Clock Calibration value.*/
|
||||||
|
MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, SmouthCalibMinusPulsesValue);
|
||||||
|
|
||||||
|
/* Change RTC state */
|
||||||
|
hrtc->State = HAL_RTC_STATE_READY;
|
||||||
|
|
||||||
|
/* Process Unlocked */
|
||||||
|
__HAL_UNLOCK(hrtc);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
2924
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c
Normal file
2924
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
3266
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c
Normal file
3266
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,233 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_spi_ex.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief Extended SPI HAL module driver.
|
||||||
|
*
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities SPI extension peripheral:
|
||||||
|
* + Extended Peripheral Control functions
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
|
|
||||||
|
/** @defgroup SPI_Private_Variables SPI Private Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if (USE_SPI_CRC != 0U)
|
||||||
|
/* Variable used to determine if device is impacted by implementation of workaround
|
||||||
|
related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
|
||||||
|
- STM32F101CDE/STM32F103CDE
|
||||||
|
- Revision ID : Z
|
||||||
|
- SPI2
|
||||||
|
- In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
|
||||||
|
the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
|
||||||
|
+ If the value is 0, the complete data transfer is successful.
|
||||||
|
+ Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
|
||||||
|
If CRCERR is found reset, the complete data transfer is considered successful.
|
||||||
|
*/
|
||||||
|
uint8_t uCRCErrorWorkaroundCheck = 0U;
|
||||||
|
#endif /* USE_SPI_CRC */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI_Exported_Functions_Group1
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the SPI according to the specified parameters
|
||||||
|
* in the SPI_InitTypeDef and create the associated handle.
|
||||||
|
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SPI module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
||||||
|
{
|
||||||
|
/* Check the SPI handle allocation */
|
||||||
|
if(hspi == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
|
||||||
|
assert_param(IS_SPI_MODE(hspi->Init.Mode));
|
||||||
|
assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
|
||||||
|
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
|
||||||
|
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
||||||
|
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
||||||
|
assert_param(IS_SPI_NSS(hspi->Init.NSS));
|
||||||
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
||||||
|
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
|
||||||
|
|
||||||
|
#if (USE_SPI_CRC != 0U)
|
||||||
|
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
|
||||||
|
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
||||||
|
{
|
||||||
|
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||||
|
#endif /* USE_SPI_CRC */
|
||||||
|
|
||||||
|
if(hspi->State == HAL_SPI_STATE_RESET)
|
||||||
|
{
|
||||||
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
||||||
|
HAL_SPI_MspInit(hspi);
|
||||||
|
}
|
||||||
|
|
||||||
|
hspi->State = HAL_SPI_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Disble the selected SPI peripheral */
|
||||||
|
__HAL_SPI_DISABLE(hspi);
|
||||||
|
|
||||||
|
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
||||||
|
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
|
||||||
|
Communication speed, First bit and CRC calculation state */
|
||||||
|
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
|
||||||
|
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
|
||||||
|
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
|
||||||
|
|
||||||
|
/* Configure : NSS management */
|
||||||
|
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
|
||||||
|
|
||||||
|
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
|
||||||
|
/* Configure : CRC Polynomial */
|
||||||
|
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
|
||||||
|
|
||||||
|
#if defined(SPI_I2SCFGR_I2SMOD)
|
||||||
|
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
||||||
|
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
||||||
|
#endif /* SPI_I2SCFGR_I2SMOD */
|
||||||
|
|
||||||
|
#if (USE_SPI_CRC != 0U)
|
||||||
|
#if defined (STM32F101xE) || defined (STM32F103xE)
|
||||||
|
/* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
|
||||||
|
CRC errors wrongly detected */
|
||||||
|
/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
|
||||||
|
Revision ID information is only available in Debug mode, so Workaround could not be implemented
|
||||||
|
to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
|
||||||
|
So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
|
||||||
|
uCRCErrorWorkaroundCheck = 0U;
|
||||||
|
#else
|
||||||
|
uCRCErrorWorkaroundCheck = 0U;
|
||||||
|
#endif /* STM32F101xE || STM32F103xE */
|
||||||
|
#endif /* USE_SPI_CRC */
|
||||||
|
|
||||||
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
||||||
|
hspi->State = HAL_SPI_STATE_READY;
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if (USE_SPI_CRC != 0U)
|
||||||
|
/**
|
||||||
|
* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
|
||||||
|
* according to SPI instance, Device type, and revision ID.
|
||||||
|
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SPI module.
|
||||||
|
* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
|
||||||
|
*/
|
||||||
|
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
|
||||||
|
{
|
||||||
|
#if defined(STM32F101xE) || defined(STM32F103xE)
|
||||||
|
/* Check how to handle this CRC error (workaround to be applied or not) */
|
||||||
|
/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
|
||||||
|
if((uCRCErrorWorkaroundCheck != 0U) && (hspi->Instance == SPI2))
|
||||||
|
{
|
||||||
|
if(hspi->Instance->RXCRCR == 0U)
|
||||||
|
{
|
||||||
|
return (SPI_INVALID_CRC_ERROR);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (SPI_VALID_CRC_ERROR);
|
||||||
|
#else
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hspi);
|
||||||
|
|
||||||
|
return (SPI_VALID_CRC_ERROR);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif /* USE_SPI_CRC */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,692 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_sram.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief SRAM HAL module driver.
|
||||||
|
* This file provides a generic firmware to drive SRAM memories
|
||||||
|
* mounted as external device.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This driver is a generic layered driver which contains a set of APIs used to
|
||||||
|
control SRAM memories. It uses the FSMC layer functions to interface
|
||||||
|
with SRAM devices.
|
||||||
|
The following sequence should be followed to configure the FSMC to interface
|
||||||
|
with SRAM/PSRAM memories:
|
||||||
|
|
||||||
|
(#) Declare a SRAM_HandleTypeDef handle structure, for example:
|
||||||
|
SRAM_HandleTypeDef hsram; and:
|
||||||
|
|
||||||
|
(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
|
||||||
|
values of the structure member.
|
||||||
|
|
||||||
|
(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
|
||||||
|
base register instance for NOR or SRAM device
|
||||||
|
|
||||||
|
(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
|
||||||
|
base register instance for NOR or SRAM extended mode
|
||||||
|
|
||||||
|
(#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
|
||||||
|
mode timings; for example:
|
||||||
|
FSMC_NORSRAM_TimingTypeDef Timing and FSMC_NORSRAM_TimingTypeDef ExTiming;
|
||||||
|
and fill its fields with the allowed values of the structure member.
|
||||||
|
|
||||||
|
(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
|
||||||
|
performs the following sequence:
|
||||||
|
|
||||||
|
(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
|
||||||
|
(##) Control register configuration using the FSMC NORSRAM interface function
|
||||||
|
FSMC_NORSRAM_Init()
|
||||||
|
(##) Timing register configuration using the FSMC NORSRAM interface function
|
||||||
|
FSMC_NORSRAM_Timing_Init()
|
||||||
|
(##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
|
||||||
|
FSMC_NORSRAM_Extended_Timing_Init()
|
||||||
|
(##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
|
||||||
|
|
||||||
|
(#) At this stage you can perform read/write accesses from/to the memory connected
|
||||||
|
to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
|
||||||
|
following APIs:
|
||||||
|
(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
|
||||||
|
(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
|
||||||
|
|
||||||
|
(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
|
||||||
|
HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
|
||||||
|
|
||||||
|
(#) You can continuously monitor the SRAM device HAL state by calling the function
|
||||||
|
HAL_SRAM_GetState()
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||||
|
|
||||||
|
#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
|
||||||
|
|
||||||
|
/** @defgroup SRAM SRAM
|
||||||
|
* @brief SRAM driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @brief Initialization and Configuration functions.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### SRAM Initialization and de_initialization functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..] This section provides functions allowing to initialize/de-initialize
|
||||||
|
the SRAM memory
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Performs the SRAM device initialization sequence
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param Timing: Pointer to SRAM control timing structure
|
||||||
|
* @param ExtTiming: Pointer to SRAM extended mode timing structure
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
|
||||||
|
{
|
||||||
|
/* Check the SRAM handle parameter */
|
||||||
|
if(hsram == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_RESET)
|
||||||
|
{
|
||||||
|
/* Allocate lock resource and initialize it */
|
||||||
|
hsram->Lock = HAL_UNLOCKED;
|
||||||
|
|
||||||
|
/* Initialize the low level hardware (MSP) */
|
||||||
|
HAL_SRAM_MspInit(hsram);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Initialize SRAM control Interface */
|
||||||
|
FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
|
||||||
|
|
||||||
|
/* Initialize SRAM timing Interface */
|
||||||
|
FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
/* Initialize SRAM extended mode timing Interface */
|
||||||
|
FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
|
||||||
|
|
||||||
|
/* Enable the NORSRAM device */
|
||||||
|
__FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Performs the SRAM device De-initialization sequence.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* De-Initialize the low level hardware (MSP) */
|
||||||
|
HAL_SRAM_MspDeInit(hsram);
|
||||||
|
|
||||||
|
/* Configure the SRAM registers with their reset values */
|
||||||
|
FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
hsram->State = HAL_SRAM_STATE_RESET;
|
||||||
|
|
||||||
|
/* Release Lock */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM MSP Init.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hsram);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_SRAM_MspInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SRAM MSP DeInit.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hsram);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_SRAM_MspDeInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA transfer complete callback.
|
||||||
|
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdma);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA transfer complete error callback.
|
||||||
|
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hdma);
|
||||||
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||||
|
the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
|
||||||
|
* @brief Input Output and memory control functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### SRAM Input and Output functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This section provides functions allowing to use and control the SRAM memory
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads 8-bit buffer from SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to read start address
|
||||||
|
* @param pDstBuffer: Pointer to destination buffer
|
||||||
|
* @param BufferSize: Size of the buffer to read from memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
__IO uint8_t * psramaddress = (uint8_t *)pAddress;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Read data from memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*pDstBuffer = *(__IO uint8_t *)psramaddress;
|
||||||
|
pDstBuffer++;
|
||||||
|
psramaddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes 8-bit buffer to SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to write start address
|
||||||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||||||
|
* @param BufferSize: Size of the buffer to write to memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
__IO uint8_t * psramaddress = (uint8_t *)pAddress;
|
||||||
|
|
||||||
|
/* Check the SRAM controller state */
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Write data to memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*(__IO uint8_t *)psramaddress = *pSrcBuffer;
|
||||||
|
pSrcBuffer++;
|
||||||
|
psramaddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads 16-bit buffer from SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to read start address
|
||||||
|
* @param pDstBuffer: Pointer to destination buffer
|
||||||
|
* @param BufferSize: Size of the buffer to read from memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
__IO uint16_t * psramaddress = (uint16_t *)pAddress;
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Read data from memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*pDstBuffer = *(__IO uint16_t *)psramaddress;
|
||||||
|
pDstBuffer++;
|
||||||
|
psramaddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes 16-bit buffer to SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to write start address
|
||||||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||||||
|
* @param BufferSize: Size of the buffer to write to memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
__IO uint16_t * psramaddress = (uint16_t *)pAddress;
|
||||||
|
|
||||||
|
/* Check the SRAM controller state */
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Write data to memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*(__IO uint16_t *)psramaddress = *pSrcBuffer;
|
||||||
|
pSrcBuffer++;
|
||||||
|
psramaddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads 32-bit buffer from SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to read start address
|
||||||
|
* @param pDstBuffer: Pointer to destination buffer
|
||||||
|
* @param BufferSize: Size of the buffer to read from memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Read data from memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*pDstBuffer = *(__IO uint32_t *)pAddress;
|
||||||
|
pDstBuffer++;
|
||||||
|
pAddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes 32-bit buffer to SRAM memory.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to write start address
|
||||||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||||||
|
* @param BufferSize: Size of the buffer to write to memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
/* Check the SRAM controller state */
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Write data to memory */
|
||||||
|
for(; BufferSize != 0U; BufferSize--)
|
||||||
|
{
|
||||||
|
*(__IO uint32_t *)pAddress = *pSrcBuffer;
|
||||||
|
pSrcBuffer++;
|
||||||
|
pAddress++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads a Words data from the SRAM memory using DMA transfer.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to read start address
|
||||||
|
* @param pDstBuffer: Pointer to destination buffer
|
||||||
|
* @param BufferSize: Size of the buffer to read from memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Configure DMA user callbacks */
|
||||||
|
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||||
|
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||||
|
|
||||||
|
/* Enable the DMA Channel */
|
||||||
|
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @param pAddress: Pointer to write start address
|
||||||
|
* @param pSrcBuffer: Pointer to source buffer to write
|
||||||
|
* @param BufferSize: Size of the buffer to write to memory
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
||||||
|
{
|
||||||
|
/* Check the SRAM controller state */
|
||||||
|
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Configure DMA user callbacks */
|
||||||
|
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
|
||||||
|
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
|
||||||
|
|
||||||
|
/* Enable the DMA Channel */
|
||||||
|
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
|
||||||
|
* @brief Control functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### SRAM Control functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection provides a set of functions allowing to control dynamically
|
||||||
|
the SRAM interface.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables dynamically SRAM write operation.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Enable write operation */
|
||||||
|
FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_READY;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables dynamically SRAM write operation.
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
/* Process Locked */
|
||||||
|
__HAL_LOCK(hsram);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_BUSY;
|
||||||
|
|
||||||
|
/* Disable write operation */
|
||||||
|
FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
|
||||||
|
|
||||||
|
/* Update the SRAM controller state */
|
||||||
|
hsram->State = HAL_SRAM_STATE_PROTECTED;
|
||||||
|
|
||||||
|
/* Process unlocked */
|
||||||
|
__HAL_UNLOCK(hsram);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
|
||||||
|
* @brief Peripheral State functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### SRAM State functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection permits to get in run-time the status of the SRAM controller
|
||||||
|
and the data flow.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the SRAM controller state
|
||||||
|
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for SRAM module.
|
||||||
|
* @retval HAL state
|
||||||
|
*/
|
||||||
|
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
|
||||||
|
{
|
||||||
|
return hsram->State;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
|
||||||
|
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,307 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_timebase_rtc_alarm_template.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief HAL time base based on the hardware RTC_ALARM.
|
||||||
|
*
|
||||||
|
* This file override the native HAL time base functions (defined as weak)
|
||||||
|
* to use the RTC ALARM for time base generation:
|
||||||
|
* + Intializes the RTC peripheral to increment the seconds registers each 1ms
|
||||||
|
* + The alarm is configured to assert an interrupt when the RTC reaches 1ms
|
||||||
|
* + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
|
||||||
|
* + HSE (default), LSE or LSI can be selected as RTC clock source
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This file must be copied to the application folder and modified as follows:
|
||||||
|
(#) Rename it to 'stm32f1xx_hal_timebase_rtc_alarm.c'
|
||||||
|
(#) Add this file and the RTC HAL drivers to your project and uncomment
|
||||||
|
HAL_RTC_MODULE_ENABLED define in stm32f1xx_hal_conf.h
|
||||||
|
|
||||||
|
[..]
|
||||||
|
(@) HAL RTC alarm and HAL RTC wakeup drivers can<EFBFBD>t be used with low power modes:
|
||||||
|
The wake up capability of the RTC may be intrusive in case of prior low power mode
|
||||||
|
configuration requiring different wake up sources.
|
||||||
|
Application/Example behavior is no more guaranteed
|
||||||
|
(@) The stm32f1xx_hal_timebase_tim use is recommended for the Applications/Examples
|
||||||
|
requiring low power modes
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Uncomment the line below to select the appropriate RTC Clock source for your application:
|
||||||
|
+ RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
|
||||||
|
+ RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
|
||||||
|
precision.
|
||||||
|
+ RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
|
||||||
|
precision.
|
||||||
|
*/
|
||||||
|
#define RTC_CLOCK_SOURCE_HSE
|
||||||
|
/* #define RTC_CLOCK_SOURCE_LSE */
|
||||||
|
/* #define RTC_CLOCK_SOURCE_LSI */
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
RTC_HandleTypeDef hRTC_Handle;
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
void RTC_Alarm_IRQHandler(void);
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function configures the RTC_ALARMA as a time base source.
|
||||||
|
* The time source is configured to have 1ms time base with a dedicated
|
||||||
|
* Tick interrupt priority.
|
||||||
|
* @note This function is called automatically at the beginning of program after
|
||||||
|
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
||||||
|
* @param TickPriority: Tick interrupt priority.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
|
||||||
|
{
|
||||||
|
__IO uint32_t counter = 0U;
|
||||||
|
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||||
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
||||||
|
|
||||||
|
#ifdef RTC_CLOCK_SOURCE_LSE
|
||||||
|
/* Configue LSE as RTC clock soucre */
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||||
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||||
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
||||||
|
#elif defined (RTC_CLOCK_SOURCE_LSI)
|
||||||
|
/* Configue LSI as RTC clock soucre */
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||||
|
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
||||||
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
||||||
|
#elif defined (RTC_CLOCK_SOURCE_HSE)
|
||||||
|
/* Configue HSE as RTC clock soucre */
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||||
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||||
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV128;
|
||||||
|
#else
|
||||||
|
#error Please select the RTC Clock source
|
||||||
|
#endif /* RTC_CLOCK_SOURCE_LSE */
|
||||||
|
|
||||||
|
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
|
||||||
|
{
|
||||||
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
||||||
|
if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
|
||||||
|
{
|
||||||
|
/* Enable RTC Clock */
|
||||||
|
__HAL_RCC_RTC_ENABLE();
|
||||||
|
|
||||||
|
hRTC_Handle.Instance = RTC;
|
||||||
|
/* Configure RTC time base to 10Khz */
|
||||||
|
hRTC_Handle.Init.AsynchPrediv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC) / 10000) - 1;
|
||||||
|
hRTC_Handle.Init.OutPut = RTC_OUTPUTSOURCE_NONE;
|
||||||
|
HAL_RTC_Init(&hRTC_Handle);
|
||||||
|
|
||||||
|
/* Disable the write protection for RTC registers */
|
||||||
|
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
|
||||||
|
|
||||||
|
/* Clear flag alarm A */
|
||||||
|
__HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
|
||||||
|
|
||||||
|
counter = 0U;
|
||||||
|
/* Wait till RTC ALRAF flag is set and if Time out is reached exit */
|
||||||
|
while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF) != RESET)
|
||||||
|
{
|
||||||
|
if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set RTC COUNTER MSB word */
|
||||||
|
hRTC_Handle.Instance->ALRH = 0x00U;
|
||||||
|
/* Set RTC COUNTER LSB word */
|
||||||
|
hRTC_Handle.Instance->ALRL = 0x09U;
|
||||||
|
|
||||||
|
/* RTC Alarm Interrupt Configuration: EXTI configuration */
|
||||||
|
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
|
||||||
|
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
|
||||||
|
|
||||||
|
/* Clear Second and overflow flags */
|
||||||
|
CLEAR_BIT(hRTC_Handle.Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
|
||||||
|
|
||||||
|
/* Set RTC COUNTER MSB word */
|
||||||
|
hRTC_Handle.Instance->CNTH = 0x00U;
|
||||||
|
/* Set RTC COUNTER LSB word */
|
||||||
|
hRTC_Handle.Instance->CNTL = 0x00U;
|
||||||
|
|
||||||
|
/* Configure the Alarm interrupt */
|
||||||
|
__HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
|
||||||
|
|
||||||
|
/* Enable the write protection for RTC registers */
|
||||||
|
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
|
||||||
|
|
||||||
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
||||||
|
counter = 0U;
|
||||||
|
while((hRTC_Handle.Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
|
||||||
|
HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Suspend Tick increment.
|
||||||
|
* @note Disable the tick increment by disabling RTC ALARM interrupt.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_SuspendTick(void)
|
||||||
|
{
|
||||||
|
/* Disable RTC ALARM update Interrupt */
|
||||||
|
__HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Resume Tick increment.
|
||||||
|
* @note Enable the tick increment by Enabling RTC ALARM interrupt.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_ResumeTick(void)
|
||||||
|
{
|
||||||
|
__IO uint32_t counter = 0U;
|
||||||
|
|
||||||
|
/* Disable the write protection for RTC registers */
|
||||||
|
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
|
||||||
|
|
||||||
|
/* Set RTC COUNTER MSB word */
|
||||||
|
hRTC_Handle.Instance->CNTH = 0x00U;
|
||||||
|
/* Set RTC COUNTER LSB word */
|
||||||
|
hRTC_Handle.Instance->CNTL = 0x00U;
|
||||||
|
|
||||||
|
/* Clear Second and overflow flags */
|
||||||
|
CLEAR_BIT(hRTC_Handle.Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW | RTC_FLAG_ALRAF));
|
||||||
|
|
||||||
|
/* Enable RTC ALARM Update interrupt */
|
||||||
|
__HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
|
||||||
|
|
||||||
|
/* Enable the write protection for RTC registers */
|
||||||
|
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
|
||||||
|
|
||||||
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
||||||
|
while((hRTC_Handle.Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ALARM A Event Callback in non blocking mode
|
||||||
|
* @note This function is called when RTC_ALARM interrupt took place, inside
|
||||||
|
* RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
|
||||||
|
* a global variable "uwTick" used as application time base.
|
||||||
|
* @param hrtc : RTC handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
|
||||||
|
{
|
||||||
|
__IO uint32_t counter = 0U;
|
||||||
|
|
||||||
|
HAL_IncTick();
|
||||||
|
|
||||||
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
||||||
|
|
||||||
|
/* Set RTC COUNTER MSB word */
|
||||||
|
WRITE_REG(hrtc->Instance->CNTH, 0x00U);
|
||||||
|
/* Set RTC COUNTER LSB word */
|
||||||
|
WRITE_REG(hrtc->Instance->CNTL, 0x00U);
|
||||||
|
|
||||||
|
/* Clear Second and overflow flags */
|
||||||
|
CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
|
||||||
|
|
||||||
|
/* Enable the write protection for RTC registers */
|
||||||
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
||||||
|
|
||||||
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
||||||
|
while((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles RTC ALARM interrupt request.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_Alarm_IRQHandler(void)
|
||||||
|
{
|
||||||
|
HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,184 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_timebase_tim_template.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief HAL time base based on the hardware TIM Template.
|
||||||
|
*
|
||||||
|
* This file overrides the native HAL time base functions (defined as weak)
|
||||||
|
* the TIM time base:
|
||||||
|
* + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
|
||||||
|
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup HAL_TimeBase_TIM
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
TIM_HandleTypeDef TimHandle;
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
void TIM2_IRQHandler(void);
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function configures the TIM2 as a time base source.
|
||||||
|
* The time source is configured to have 1ms time base with a dedicated
|
||||||
|
* Tick interrupt priority.
|
||||||
|
* @note This function is called automatically at the beginning of program after
|
||||||
|
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
||||||
|
* @param TickPriority: Tick interrupt priority.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
|
||||||
|
{
|
||||||
|
RCC_ClkInitTypeDef clkconfig;
|
||||||
|
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
|
||||||
|
uint32_t uwPrescalerValue = 0U;
|
||||||
|
uint32_t pFLatency;
|
||||||
|
|
||||||
|
/*Configure the TIM2 IRQ priority */
|
||||||
|
HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0U);
|
||||||
|
|
||||||
|
/* Enable the TIM2 global Interrupt */
|
||||||
|
HAL_NVIC_EnableIRQ(TIM2_IRQn);
|
||||||
|
|
||||||
|
/* Enable TIM2 clock */
|
||||||
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
||||||
|
|
||||||
|
/* Get clock configuration */
|
||||||
|
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
|
||||||
|
|
||||||
|
/* Get APB1 prescaler */
|
||||||
|
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
|
||||||
|
|
||||||
|
/* Compute TIM2 clock */
|
||||||
|
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
|
||||||
|
{
|
||||||
|
uwTimclock = HAL_RCC_GetPCLK1Freq();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */
|
||||||
|
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
|
||||||
|
|
||||||
|
/* Initialize TIM2 */
|
||||||
|
TimHandle.Instance = TIM2;
|
||||||
|
|
||||||
|
/* Initialize TIMx peripheral as follow:
|
||||||
|
+ Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base.
|
||||||
|
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
|
||||||
|
+ ClockDivision = 0
|
||||||
|
+ Counter direction = Up
|
||||||
|
*/
|
||||||
|
TimHandle.Init.Period = (1000000U / 1000U) - 1U;
|
||||||
|
TimHandle.Init.Prescaler = uwPrescalerValue;
|
||||||
|
TimHandle.Init.ClockDivision = 0U;
|
||||||
|
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||||
|
TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||||
|
if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
|
||||||
|
{
|
||||||
|
/* Start the TIM time Base generation in interrupt mode */
|
||||||
|
return HAL_TIM_Base_Start_IT(&TimHandle);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Suspend Tick increment.
|
||||||
|
* @note Disable the tick increment by disabling TIM2 update interrupt.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_SuspendTick(void)
|
||||||
|
{
|
||||||
|
/* Disable TIM2 update Interrupt */
|
||||||
|
__HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Resume Tick increment.
|
||||||
|
* @note Enable the tick increment by Enabling TIM2 update interrupt.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_ResumeTick(void)
|
||||||
|
{
|
||||||
|
/* Enable TIM2 Update interrupt */
|
||||||
|
__HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Period elapsed callback in non blocking mode
|
||||||
|
* @note This function is called when TIM2 interrupt took place, inside
|
||||||
|
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
|
||||||
|
* a global variable "uwTick" used as application time base.
|
||||||
|
* @param htim : TIM handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
||||||
|
{
|
||||||
|
HAL_IncTick();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles TIM interrupt request.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void TIM2_IRQHandler(void)
|
||||||
|
{
|
||||||
|
HAL_TIM_IRQHandler(&TimHandle);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,314 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_hal_wwdg.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief WWDG HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the Window Watchdog (WWDG) peripheral:
|
||||||
|
* + Initialization and de-initialization functions
|
||||||
|
* + IO operation functions
|
||||||
|
* + Peripheral State functions
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### WWDG specific features #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
Once enabled the WWDG generates a system reset on expiry of a programmed
|
||||||
|
time period, unless the program refreshes the counter (downcounter)
|
||||||
|
before reaching 0x3F value (i.e. a reset is generated when the counter
|
||||||
|
value rolls over from 0x40 to 0x3F).
|
||||||
|
|
||||||
|
(+) An MCU reset is also generated if the counter value is refreshed
|
||||||
|
before the counter has reached the refresh window value. This
|
||||||
|
implies that the counter must be refreshed in a limited window.
|
||||||
|
(+) Once enabled the WWDG cannot be disabled except by a system reset.
|
||||||
|
(+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
|
||||||
|
reset occurs.
|
||||||
|
(+) The WWDG counter input clock is derived from the APB clock divided
|
||||||
|
by a programmable prescaler.
|
||||||
|
(+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
|
||||||
|
(+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
|
||||||
|
(+) WWDG Counter refresh is allowed between the following limits :
|
||||||
|
(++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
|
||||||
|
(++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
|
||||||
|
|
||||||
|
(+) Min-max timeout value at 36 MHz(PCLK1): 910 us / 58.25 ms
|
||||||
|
|
||||||
|
(+) The Early Wakeup Interrupt (EWI) can be used if specific safety
|
||||||
|
operations or data logging must be performed before the actual reset is
|
||||||
|
generated. When the downcounter reaches the value 0x40, an EWI interrupt
|
||||||
|
is generated and the corresponding interrupt service routine (ISR) can
|
||||||
|
be used to trigger specific actions (such as communications or data
|
||||||
|
logging), before resetting the device.
|
||||||
|
In some applications, the EWI interrupt can be used to manage a software
|
||||||
|
system check and/or system recovery/graceful degradation, without
|
||||||
|
generating a WWDG reset. In this case, the corresponding interrupt
|
||||||
|
service routine (ISR) should reload the WWDG counter to avoid the WWDG
|
||||||
|
reset, then trigger the required actions.
|
||||||
|
Note:When the EWI interrupt cannot be served, e.g. due to a system lock
|
||||||
|
in a higher priority task, the WWDG reset will eventually be generated.
|
||||||
|
|
||||||
|
(+) Debug mode : When the microcontroller enters debug mode (core halted),
|
||||||
|
the WWDG counter either continues to work normally or stops, depending
|
||||||
|
on DBG_WWDG_STOP configuration bit in DBG module, accessible through
|
||||||
|
__HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
|
||||||
|
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
|
||||||
|
|
||||||
|
(+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
|
||||||
|
Interrupt mode using using HAL_WWDG_Init() function.
|
||||||
|
This enables WWDG peripheral and the downcounter starts downcounting
|
||||||
|
from given counter value.
|
||||||
|
Init function can be called again to modify all watchdog parameters,
|
||||||
|
however if EWI mode has been set once, it can't be clear until next
|
||||||
|
reset.
|
||||||
|
|
||||||
|
(+) The application program must refresh the WWDG counter at regular
|
||||||
|
intervals during normal operation to prevent an MCU reset using
|
||||||
|
HAL_WWDG_Refresh() function. This operation must occur only when
|
||||||
|
the counter is lower than the window value already programmed.
|
||||||
|
|
||||||
|
(+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
|
||||||
|
the counter reaches 0x40. User can add his own code in weak function
|
||||||
|
HAL_WWDG_EarlyWakeupCallback().
|
||||||
|
|
||||||
|
*** WWDG HAL driver macros list ***
|
||||||
|
==================================
|
||||||
|
[..]
|
||||||
|
Below the list of most used macros in WWDG HAL driver.
|
||||||
|
|
||||||
|
(+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
|
||||||
|
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
|
||||||
|
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||||
|
/** @defgroup WWDG WWDG
|
||||||
|
* @brief WWDG HAL module driver.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
|
||||||
|
* @brief Initialization and Configuration functions.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Initialization and Configuration functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This section provides functions allowing to:
|
||||||
|
(+) Initialize and start the WWDG according to the specified parameters
|
||||||
|
in the WWDG_InitTypeDef of associated handle.
|
||||||
|
(+) Initialize the WWDG MSP.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the WWDG according to the specified.
|
||||||
|
* parameters in the WWDG_InitTypeDef of associated handle.
|
||||||
|
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified WWDG module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
|
||||||
|
{
|
||||||
|
/* Check the WWDG handle allocation */
|
||||||
|
if(hwwdg == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
|
||||||
|
assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
|
||||||
|
assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
|
||||||
|
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
|
||||||
|
assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
|
||||||
|
|
||||||
|
/* Init the low level hardware */
|
||||||
|
HAL_WWDG_MspInit(hwwdg);
|
||||||
|
|
||||||
|
/* Set WWDG Counter */
|
||||||
|
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
|
||||||
|
|
||||||
|
/* Set WWDG Prescaler and Window */
|
||||||
|
WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the WWDG MSP.
|
||||||
|
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified WWDG module.
|
||||||
|
* @note When rewriting this function in user file, mechanism may be added
|
||||||
|
* to avoid multiple initialize when HAL_WWDG_Init function is called
|
||||||
|
* again to change parameters.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hwwdg);
|
||||||
|
|
||||||
|
/* NOTE: This function should not be modified, when the callback is needed,
|
||||||
|
the HAL_WWDG_MspInit could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
|
||||||
|
* @brief IO operation functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### IO operation functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This section provides functions allowing to:
|
||||||
|
(+) Refresh the WWDG.
|
||||||
|
(+) Handle WWDG interrupt request and associated function callback.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Refresh the WWDG.
|
||||||
|
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified WWDG module.
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
|
||||||
|
{
|
||||||
|
/* Write to WWDG CR the WWDG Counter value to refresh with */
|
||||||
|
WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
|
||||||
|
|
||||||
|
/* Return function status */
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Handle WWDG interrupt request.
|
||||||
|
* @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
|
||||||
|
* or data logging must be performed before the actual reset is generated.
|
||||||
|
* The EWI interrupt is enabled by calling HAL_WWDG_Init function with
|
||||||
|
* EWIMode set to WWDG_EWI_ENABLE.
|
||||||
|
* When the downcounter reaches the value 0x40, and EWI interrupt is
|
||||||
|
* generated and the corresponding Interrupt Service Routine (ISR) can
|
||||||
|
* be used to trigger specific actions (such as communications or data
|
||||||
|
* logging), before resetting the device.
|
||||||
|
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified WWDG module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
|
||||||
|
{
|
||||||
|
/* Check if Early Wakeup Interrupt is enable */
|
||||||
|
if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
|
||||||
|
{
|
||||||
|
/* Check if WWDG Early Wakeup Interrupt occurred */
|
||||||
|
if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
|
||||||
|
{
|
||||||
|
/* Clear the WWDG Early Wakeup flag */
|
||||||
|
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
|
||||||
|
|
||||||
|
/* Early Wakeup callback */
|
||||||
|
HAL_WWDG_EarlyWakeupCallback(hwwdg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief WWDG Early Wakeup callback.
|
||||||
|
* @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains
|
||||||
|
* the configuration information for the specified WWDG module.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
|
||||||
|
{
|
||||||
|
/* Prevent unused argument(s) compilation warning */
|
||||||
|
UNUSED(hwwdg);
|
||||||
|
|
||||||
|
/* NOTE: This function should not be modified, when the callback is needed,
|
||||||
|
the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,903 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_adc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief ADC LL module driver
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_adc.h"
|
||||||
|
#include "stm32f1xx_ll_bus.h"
|
||||||
|
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (ADC1) || defined (ADC2) || defined (ADC3)
|
||||||
|
|
||||||
|
/** @addtogroup ADC_LL ADC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup ADC_LL_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Check of parameters for configuration of ADC hierarchical scope: */
|
||||||
|
/* common to several ADC instances. */
|
||||||
|
/* Check of parameters for configuration of ADC hierarchical scope: */
|
||||||
|
/* ADC instance. */
|
||||||
|
#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
|
||||||
|
( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
|
||||||
|
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
|
||||||
|
( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
|
||||||
|
|| ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
|
||||||
|
( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
|
||||||
|
|| ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
|
||||||
|
)
|
||||||
|
|
||||||
|
/* Check of parameters for configuration of ADC hierarchical scope: */
|
||||||
|
/* ADC group regular */
|
||||||
|
#if defined(ADC3)
|
||||||
|
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
|
||||||
|
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
|
||||||
|
? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
|
||||||
|
) \
|
||||||
|
: \
|
||||||
|
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
|
||||||
|
) \
|
||||||
|
)
|
||||||
|
#else
|
||||||
|
#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
|
||||||
|
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
|
||||||
|
)
|
||||||
|
#else
|
||||||
|
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
|
||||||
|
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
|
||||||
|
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
|
||||||
|
)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
|
||||||
|
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|
||||||
|
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
|
||||||
|
( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
|
||||||
|
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
|
||||||
|
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
|
||||||
|
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
|
||||||
|
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|
||||||
|
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
|
||||||
|
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
|
||||||
|
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
|
||||||
|
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
|
||||||
|
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
|
||||||
|
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
|
||||||
|
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
|
||||||
|
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
|
||||||
|
)
|
||||||
|
|
||||||
|
/* Check of parameters for configuration of ADC hierarchical scope: */
|
||||||
|
/* ADC group injected */
|
||||||
|
#if defined(ADC3)
|
||||||
|
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
|
||||||
|
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
|
||||||
|
? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
|
||||||
|
) \
|
||||||
|
: \
|
||||||
|
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
|
||||||
|
) \
|
||||||
|
)
|
||||||
|
#else
|
||||||
|
#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
|
||||||
|
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
|
||||||
|
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
|
||||||
|
)
|
||||||
|
#else
|
||||||
|
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
|
||||||
|
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
|
||||||
|
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
|
||||||
|
)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
|
||||||
|
( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
|
||||||
|
|| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
|
||||||
|
( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
|
||||||
|
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
|
||||||
|
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
|
||||||
|
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
|
||||||
|
( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
|
||||||
|
|| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||||
|
/* Check of parameters for configuration of ADC hierarchical scope: */
|
||||||
|
/* multimode. */
|
||||||
|
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
|
||||||
|
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
|
||||||
|
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
|
||||||
|
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \
|
||||||
|
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \
|
||||||
|
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
|
||||||
|
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
|
||||||
|
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
|
||||||
|
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
|
||||||
|
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \
|
||||||
|
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
|
||||||
|
( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
|
||||||
|
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
|
||||||
|
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup ADC_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ADC_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize registers of all ADC instances belonging to
|
||||||
|
* the same ADC common instance to their default reset values.
|
||||||
|
* @param ADCxy_COMMON ADC common instance
|
||||||
|
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: ADC common registers are de-initialized
|
||||||
|
* - ERROR: not applicable
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
|
||||||
|
|
||||||
|
/* Force reset of ADC clock (core clock) */
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
|
||||||
|
|
||||||
|
/* Release reset of ADC clock (core clock) */
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize some features of ADC common parameters
|
||||||
|
* (all ADC instances belonging to the same ADC common instance)
|
||||||
|
* and multimode (for devices with several ADC instances available).
|
||||||
|
* @note The setting of ADC common parameters is conditioned to
|
||||||
|
* ADC instances state:
|
||||||
|
* All ADC instances belonging to the same ADC common instance
|
||||||
|
* must be disabled.
|
||||||
|
* @param ADCxy_COMMON ADC common instance
|
||||||
|
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
|
||||||
|
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: ADC common registers are initialized
|
||||||
|
* - ERROR: ADC common registers are not initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
|
||||||
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||||
|
assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
|
||||||
|
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||||
|
|
||||||
|
/* Note: Hardware constraint (refer to description of functions */
|
||||||
|
/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
|
||||||
|
/* On this STM32 serie, setting of these features is conditioned to */
|
||||||
|
/* ADC state: */
|
||||||
|
/* All ADC instances of the ADC common group must be disabled. */
|
||||||
|
if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
|
||||||
|
{
|
||||||
|
/* Configuration of ADC hierarchical scope: */
|
||||||
|
/* - common to several ADC */
|
||||||
|
/* (all ADC instances belonging to the same ADC common instance) */
|
||||||
|
/* - multimode (if several ADC instances available on the */
|
||||||
|
/* selected device) */
|
||||||
|
/* - Set ADC multimode configuration */
|
||||||
|
/* - Set ADC multimode DMA transfer */
|
||||||
|
/* - Set ADC multimode: delay between 2 sampling phases */
|
||||||
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||||
|
if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
|
||||||
|
{
|
||||||
|
MODIFY_REG(ADCxy_COMMON->CR1,
|
||||||
|
ADC_CR1_DUALMOD,
|
||||||
|
ADC_CommonInitStruct->Multimode
|
||||||
|
);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
MODIFY_REG(ADCxy_COMMON->CR1,
|
||||||
|
ADC_CR1_DUALMOD,
|
||||||
|
LL_ADC_MULTI_INDEPENDENT
|
||||||
|
);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Initialization error: One or several ADC instances belonging to */
|
||||||
|
/* the same ADC common instance are not disabled. */
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
|
||||||
|
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
|
||||||
|
{
|
||||||
|
/* Set ADC_CommonInitStruct fields to default values */
|
||||||
|
/* Set fields of ADC common */
|
||||||
|
/* (all ADC instances belonging to the same ADC common instance) */
|
||||||
|
|
||||||
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
||||||
|
/* Set fields of ADC multimode */
|
||||||
|
ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
|
||||||
|
#endif /* ADC_MULTIMODE_SUPPORT */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize registers of the selected ADC instance
|
||||||
|
* to their default reset values.
|
||||||
|
* @note To reset all ADC instances quickly (perform a hard reset),
|
||||||
|
* use function @ref LL_ADC_CommonDeInit().
|
||||||
|
* @param ADCx ADC instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: ADC registers are de-initialized
|
||||||
|
* - ERROR: ADC registers are not de-initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
||||||
|
|
||||||
|
/* Disable ADC instance if not already disabled. */
|
||||||
|
if(LL_ADC_IsEnabled(ADCx) == 1U)
|
||||||
|
{
|
||||||
|
/* Set ADC group regular trigger source to SW start to ensure to not */
|
||||||
|
/* have an external trigger event occurring during the conversion stop */
|
||||||
|
/* ADC disable process. */
|
||||||
|
LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
|
||||||
|
|
||||||
|
/* Set ADC group injected trigger source to SW start to ensure to not */
|
||||||
|
/* have an external trigger event occurring during the conversion stop */
|
||||||
|
/* ADC disable process. */
|
||||||
|
LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
|
||||||
|
|
||||||
|
/* Disable the ADC instance */
|
||||||
|
LL_ADC_Disable(ADCx);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check whether ADC state is compliant with expected state */
|
||||||
|
/* (hardware requirements of bits state to reset registers below) */
|
||||||
|
if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
|
||||||
|
{
|
||||||
|
/* ========== Reset ADC registers ========== */
|
||||||
|
/* Reset register SR */
|
||||||
|
CLEAR_BIT(ADCx->SR,
|
||||||
|
( LL_ADC_FLAG_STRT
|
||||||
|
| LL_ADC_FLAG_JSTRT
|
||||||
|
| LL_ADC_FLAG_EOS
|
||||||
|
| LL_ADC_FLAG_JEOS
|
||||||
|
| LL_ADC_FLAG_AWD1 )
|
||||||
|
);
|
||||||
|
|
||||||
|
/* Reset register CR1 */
|
||||||
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
||||||
|
|
||||||
|
CLEAR_BIT(ADCx->CR1,
|
||||||
|
( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DUALMOD
|
||||||
|
| ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
|
||||||
|
| ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
|
||||||
|
| ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
|
||||||
|
| ADC_CR1_AWDCH )
|
||||||
|
);
|
||||||
|
#else
|
||||||
|
|
||||||
|
CLEAR_BIT(ADCx->CR1,
|
||||||
|
( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM
|
||||||
|
| ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO
|
||||||
|
| ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE
|
||||||
|
| ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )
|
||||||
|
);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Reset register CR2 */
|
||||||
|
CLEAR_BIT(ADCx->CR2,
|
||||||
|
( ADC_CR2_TSVREFE
|
||||||
|
| ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
|
||||||
|
| ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
|
||||||
|
| ADC_CR2_ALIGN | ADC_CR2_DMA
|
||||||
|
| ADC_CR2_RSTCAL | ADC_CR2_CAL
|
||||||
|
| ADC_CR2_CONT | ADC_CR2_ADON )
|
||||||
|
);
|
||||||
|
|
||||||
|
/* Reset register SMPR1 */
|
||||||
|
CLEAR_BIT(ADCx->SMPR1,
|
||||||
|
( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
|
||||||
|
| ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
|
||||||
|
| ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
|
||||||
|
);
|
||||||
|
|
||||||
|
/* Reset register SMPR2 */
|
||||||
|
CLEAR_BIT(ADCx->SMPR2,
|
||||||
|
( ADC_SMPR2_SMP9
|
||||||
|
| ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
|
||||||
|
| ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
|
||||||
|
| ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
|
||||||
|
);
|
||||||
|
|
||||||
|
/* Reset register JOFR1 */
|
||||||
|
CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
|
||||||
|
/* Reset register JOFR2 */
|
||||||
|
CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
|
||||||
|
/* Reset register JOFR3 */
|
||||||
|
CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
|
||||||
|
/* Reset register JOFR4 */
|
||||||
|
CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
|
||||||
|
|
||||||
|
/* Reset register HTR */
|
||||||
|
SET_BIT(ADCx->HTR, ADC_HTR_HT);
|
||||||
|
/* Reset register LTR */
|
||||||
|
CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
|
||||||
|
|
||||||
|
/* Reset register SQR1 */
|
||||||
|
CLEAR_BIT(ADCx->SQR1,
|
||||||
|
( ADC_SQR1_L
|
||||||
|
| ADC_SQR1_SQ16
|
||||||
|
| ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
|
||||||
|
);
|
||||||
|
|
||||||
|
/* Reset register SQR2 */
|
||||||
|
CLEAR_BIT(ADCx->SQR2,
|
||||||
|
( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
|
||||||
|
| ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
/* Reset register JSQR */
|
||||||
|
CLEAR_BIT(ADCx->JSQR,
|
||||||
|
( ADC_JSQR_JL
|
||||||
|
| ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
|
||||||
|
| ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
|
||||||
|
);
|
||||||
|
|
||||||
|
/* Reset register DR */
|
||||||
|
/* bits in access mode read only, no direct reset applicable */
|
||||||
|
|
||||||
|
/* Reset registers JDR1, JDR2, JDR3, JDR4 */
|
||||||
|
/* bits in access mode read only, no direct reset applicable */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize some features of ADC instance.
|
||||||
|
* @note These parameters have an impact on ADC scope: ADC instance.
|
||||||
|
* Affects both group regular and group injected (availability
|
||||||
|
* of ADC group injected depends on STM32 families).
|
||||||
|
* Refer to corresponding unitary functions into
|
||||||
|
* @ref ADC_LL_EF_Configuration_ADC_Instance .
|
||||||
|
* @note The setting of these parameters by function @ref LL_ADC_Init()
|
||||||
|
* is conditioned to ADC state:
|
||||||
|
* ADC instance must be disabled.
|
||||||
|
* This condition is applied to all ADC features, for efficiency
|
||||||
|
* and compatibility over all STM32 families. However, the different
|
||||||
|
* features can be set under different ADC state conditions
|
||||||
|
* (setting possible with ADC enabled without conversion on going,
|
||||||
|
* ADC enabled with conversion on going, ...)
|
||||||
|
* Each feature can be updated afterwards with a unitary function
|
||||||
|
* and potentially with ADC in a different state than disabled,
|
||||||
|
* refer to description of each function for setting
|
||||||
|
* conditioned to ADC state.
|
||||||
|
* @note After using this function, some other features must be configured
|
||||||
|
* using LL unitary functions.
|
||||||
|
* The minimum configuration remaining to be done is:
|
||||||
|
* - Set ADC group regular or group injected sequencer:
|
||||||
|
* map channel on the selected sequencer rank.
|
||||||
|
* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
|
||||||
|
* - Set ADC channel sampling time
|
||||||
|
* Refer to function LL_ADC_SetChannelSamplingTime();
|
||||||
|
* @param ADCx ADC instance
|
||||||
|
* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: ADC registers are initialized
|
||||||
|
* - ERROR: ADC registers are not initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
||||||
|
|
||||||
|
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
|
||||||
|
assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
|
||||||
|
|
||||||
|
/* Note: Hardware constraint (refer to description of this function): */
|
||||||
|
/* ADC instance must be disabled. */
|
||||||
|
if(LL_ADC_IsEnabled(ADCx) == 0U)
|
||||||
|
{
|
||||||
|
/* Configuration of ADC hierarchical scope: */
|
||||||
|
/* - ADC instance */
|
||||||
|
/* - Set ADC conversion data alignment */
|
||||||
|
MODIFY_REG(ADCx->CR1,
|
||||||
|
ADC_CR1_SCAN
|
||||||
|
,
|
||||||
|
ADC_InitStruct->SequencersScanMode
|
||||||
|
);
|
||||||
|
|
||||||
|
MODIFY_REG(ADCx->CR2,
|
||||||
|
ADC_CR2_ALIGN
|
||||||
|
,
|
||||||
|
ADC_InitStruct->DataAlignment
|
||||||
|
);
|
||||||
|
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Initialization error: ADC instance is not disabled. */
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
|
||||||
|
* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
|
||||||
|
{
|
||||||
|
/* Set ADC_InitStruct fields to default values */
|
||||||
|
/* Set fields of ADC instance */
|
||||||
|
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
|
||||||
|
|
||||||
|
/* Enable scan mode to have a generic behavior with ADC of other */
|
||||||
|
/* STM32 families, without this setting available: */
|
||||||
|
/* ADC group regular sequencer and ADC group injected sequencer depend */
|
||||||
|
/* only of their own configuration. */
|
||||||
|
ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize some features of ADC group regular.
|
||||||
|
* @note These parameters have an impact on ADC scope: ADC group regular.
|
||||||
|
* Refer to corresponding unitary functions into
|
||||||
|
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
|
||||||
|
* (functions with prefix "REG").
|
||||||
|
* @note The setting of these parameters by function @ref LL_ADC_Init()
|
||||||
|
* is conditioned to ADC state:
|
||||||
|
* ADC instance must be disabled.
|
||||||
|
* This condition is applied to all ADC features, for efficiency
|
||||||
|
* and compatibility over all STM32 families. However, the different
|
||||||
|
* features can be set under different ADC state conditions
|
||||||
|
* (setting possible with ADC enabled without conversion on going,
|
||||||
|
* ADC enabled with conversion on going, ...)
|
||||||
|
* Each feature can be updated afterwards with a unitary function
|
||||||
|
* and potentially with ADC in a different state than disabled,
|
||||||
|
* refer to description of each function for setting
|
||||||
|
* conditioned to ADC state.
|
||||||
|
* @note After using this function, other features must be configured
|
||||||
|
* using LL unitary functions.
|
||||||
|
* The minimum configuration remaining to be done is:
|
||||||
|
* - Set ADC group regular or group injected sequencer:
|
||||||
|
* map channel on the selected sequencer rank.
|
||||||
|
* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
|
||||||
|
* - Set ADC channel sampling time
|
||||||
|
* Refer to function LL_ADC_SetChannelSamplingTime();
|
||||||
|
* @param ADCx ADC instance
|
||||||
|
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: ADC registers are initialized
|
||||||
|
* - ERROR: ADC registers are not initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
||||||
|
#if defined(ADC3)
|
||||||
|
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
|
||||||
|
#else
|
||||||
|
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
|
||||||
|
#endif
|
||||||
|
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
|
||||||
|
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
|
||||||
|
{
|
||||||
|
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
|
||||||
|
}
|
||||||
|
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
|
||||||
|
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
|
||||||
|
|
||||||
|
/* Note: Hardware constraint (refer to description of this function): */
|
||||||
|
/* ADC instance must be disabled. */
|
||||||
|
if(LL_ADC_IsEnabled(ADCx) == 0U)
|
||||||
|
{
|
||||||
|
/* Configuration of ADC hierarchical scope: */
|
||||||
|
/* - ADC group regular */
|
||||||
|
/* - Set ADC group regular trigger source */
|
||||||
|
/* - Set ADC group regular sequencer length */
|
||||||
|
/* - Set ADC group regular sequencer discontinuous mode */
|
||||||
|
/* - Set ADC group regular continuous mode */
|
||||||
|
/* - Set ADC group regular conversion data transfer: no transfer or */
|
||||||
|
/* transfer by DMA, and DMA requests mode */
|
||||||
|
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
|
||||||
|
/* ADC conversion. */
|
||||||
|
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
|
||||||
|
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
|
||||||
|
{
|
||||||
|
MODIFY_REG(ADCx->CR1,
|
||||||
|
ADC_CR1_DISCEN
|
||||||
|
| ADC_CR1_DISCNUM
|
||||||
|
,
|
||||||
|
ADC_REG_InitStruct->SequencerLength
|
||||||
|
| ADC_REG_InitStruct->SequencerDiscont
|
||||||
|
);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
MODIFY_REG(ADCx->CR1,
|
||||||
|
ADC_CR1_DISCEN
|
||||||
|
| ADC_CR1_DISCNUM
|
||||||
|
,
|
||||||
|
ADC_REG_InitStruct->SequencerLength
|
||||||
|
| LL_ADC_REG_SEQ_DISCONT_DISABLE
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
MODIFY_REG(ADCx->CR2,
|
||||||
|
ADC_CR2_EXTSEL
|
||||||
|
| ADC_CR2_CONT
|
||||||
|
| ADC_CR2_DMA
|
||||||
|
,
|
||||||
|
ADC_REG_InitStruct->TriggerSource
|
||||||
|
| ADC_REG_InitStruct->ContinuousMode
|
||||||
|
| ADC_REG_InitStruct->DMATransfer
|
||||||
|
);
|
||||||
|
|
||||||
|
/* Set ADC group regular sequencer length and scan direction */
|
||||||
|
/* Note: Hardware constraint (refer to description of this function): */
|
||||||
|
/* Note: If ADC instance feature scan mode is disabled */
|
||||||
|
/* (refer to ADC instance initialization structure */
|
||||||
|
/* parameter @ref SequencersScanMode */
|
||||||
|
/* or function @ref LL_ADC_SetSequencersScanMode() ), */
|
||||||
|
/* this parameter is discarded. */
|
||||||
|
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Initialization error: ADC instance is not disabled. */
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
|
||||||
|
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
|
||||||
|
{
|
||||||
|
/* Set ADC_REG_InitStruct fields to default values */
|
||||||
|
/* Set fields of ADC group regular */
|
||||||
|
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
|
||||||
|
/* ADC conversion. */
|
||||||
|
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
|
||||||
|
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
|
||||||
|
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
|
||||||
|
ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
|
||||||
|
ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
|
||||||
|
ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize some features of ADC group injected.
|
||||||
|
* @note These parameters have an impact on ADC scope: ADC group injected.
|
||||||
|
* Refer to corresponding unitary functions into
|
||||||
|
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
|
||||||
|
* (functions with prefix "INJ").
|
||||||
|
* @note The setting of these parameters by function @ref LL_ADC_Init()
|
||||||
|
* is conditioned to ADC state:
|
||||||
|
* ADC instance must be disabled.
|
||||||
|
* This condition is applied to all ADC features, for efficiency
|
||||||
|
* and compatibility over all STM32 families. However, the different
|
||||||
|
* features can be set under different ADC state conditions
|
||||||
|
* (setting possible with ADC enabled without conversion on going,
|
||||||
|
* ADC enabled with conversion on going, ...)
|
||||||
|
* Each feature can be updated afterwards with a unitary function
|
||||||
|
* and potentially with ADC in a different state than disabled,
|
||||||
|
* refer to description of each function for setting
|
||||||
|
* conditioned to ADC state.
|
||||||
|
* @note After using this function, other features must be configured
|
||||||
|
* using LL unitary functions.
|
||||||
|
* The minimum configuration remaining to be done is:
|
||||||
|
* - Set ADC group injected sequencer:
|
||||||
|
* map channel on the selected sequencer rank.
|
||||||
|
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
|
||||||
|
* - Set ADC channel sampling time
|
||||||
|
* Refer to function LL_ADC_SetChannelSamplingTime();
|
||||||
|
* @param ADCx ADC instance
|
||||||
|
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: ADC registers are initialized
|
||||||
|
* - ERROR: ADC registers are not initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
||||||
|
#if defined(ADC3)
|
||||||
|
assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
|
||||||
|
#else
|
||||||
|
assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
|
||||||
|
#endif
|
||||||
|
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
|
||||||
|
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
|
||||||
|
{
|
||||||
|
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
|
||||||
|
}
|
||||||
|
assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
|
||||||
|
|
||||||
|
/* Note: Hardware constraint (refer to description of this function): */
|
||||||
|
/* ADC instance must be disabled. */
|
||||||
|
if(LL_ADC_IsEnabled(ADCx) == 0U)
|
||||||
|
{
|
||||||
|
/* Configuration of ADC hierarchical scope: */
|
||||||
|
/* - ADC group injected */
|
||||||
|
/* - Set ADC group injected trigger source */
|
||||||
|
/* - Set ADC group injected sequencer length */
|
||||||
|
/* - Set ADC group injected sequencer discontinuous mode */
|
||||||
|
/* - Set ADC group injected conversion trigger: independent or */
|
||||||
|
/* from ADC group regular */
|
||||||
|
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
|
||||||
|
/* ADC conversion. */
|
||||||
|
/* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
|
||||||
|
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
|
||||||
|
{
|
||||||
|
MODIFY_REG(ADCx->CR1,
|
||||||
|
ADC_CR1_JDISCEN
|
||||||
|
| ADC_CR1_JAUTO
|
||||||
|
,
|
||||||
|
ADC_INJ_InitStruct->SequencerDiscont
|
||||||
|
| ADC_INJ_InitStruct->TrigAuto
|
||||||
|
);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
MODIFY_REG(ADCx->CR1,
|
||||||
|
ADC_CR1_JDISCEN
|
||||||
|
| ADC_CR1_JAUTO
|
||||||
|
,
|
||||||
|
LL_ADC_REG_SEQ_DISCONT_DISABLE
|
||||||
|
| ADC_INJ_InitStruct->TrigAuto
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
MODIFY_REG(ADCx->CR2,
|
||||||
|
ADC_CR2_JEXTSEL
|
||||||
|
,
|
||||||
|
ADC_INJ_InitStruct->TriggerSource
|
||||||
|
);
|
||||||
|
|
||||||
|
/* Note: Hardware constraint (refer to description of this function): */
|
||||||
|
/* Note: If ADC instance feature scan mode is disabled */
|
||||||
|
/* (refer to ADC instance initialization structure */
|
||||||
|
/* parameter @ref SequencersScanMode */
|
||||||
|
/* or function @ref LL_ADC_SetSequencersScanMode() ), */
|
||||||
|
/* this parameter is discarded. */
|
||||||
|
LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Initialization error: ADC instance is not disabled. */
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
|
||||||
|
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
|
||||||
|
{
|
||||||
|
/* Set ADC_INJ_InitStruct fields to default values */
|
||||||
|
/* Set fields of ADC group injected */
|
||||||
|
ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
|
||||||
|
ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
|
||||||
|
ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
|
||||||
|
ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* ADC1 || ADC2 || ADC3 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,126 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_crc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief CRC LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_crc.h"
|
||||||
|
#include "stm32f1xx_ll_bus.h"
|
||||||
|
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (CRC)
|
||||||
|
|
||||||
|
/** @addtogroup CRC_LL
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup CRC_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize CRC registers (Registers restored to their default values).
|
||||||
|
* @param CRCx CRC Instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: CRC registers are de-initialized
|
||||||
|
* - ERROR: CRC registers are not de-initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CRC_ALL_INSTANCE(CRCx));
|
||||||
|
|
||||||
|
if (CRCx == CRC)
|
||||||
|
{
|
||||||
|
|
||||||
|
/* Reset the CRC calculation unit */
|
||||||
|
LL_CRC_ResetCRCCalculationUnit(CRCx);
|
||||||
|
|
||||||
|
/* Reset IDR register */
|
||||||
|
LL_CRC_Write_IDR(CRCx, 0x00U);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (status);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* defined (CRC) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
@ -0,0 +1,274 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_dac.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief DAC LL module driver
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_dac.h"
|
||||||
|
#include "stm32f1xx_ll_bus.h"
|
||||||
|
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (DAC)
|
||||||
|
|
||||||
|
/** @addtogroup DAC_LL DAC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_LL_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
|
||||||
|
( \
|
||||||
|
((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
|
||||||
|
|| ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
|
||||||
|
( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|
||||||
|
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
|
||||||
|
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
|
||||||
|
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
|
||||||
|
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
|
||||||
|
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
|
||||||
|
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
|
||||||
|
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
|
||||||
|
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
|
||||||
|
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
|
||||||
|
)
|
||||||
|
#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
|
||||||
|
( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
|
||||||
|
( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
|
||||||
|
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
|
||||||
|
( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
|
||||||
|
|| ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
|
||||||
|
)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup DAC_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize registers of the selected DAC instance
|
||||||
|
* to their default reset values.
|
||||||
|
* @param DACx DAC instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: DAC registers are de-initialized
|
||||||
|
* - ERROR: not applicable
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_ALL_INSTANCE(DACx));
|
||||||
|
|
||||||
|
/* Force reset of DAC1 clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
|
||||||
|
|
||||||
|
/* Release reset of DAC1 clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize some features of DAC instance.
|
||||||
|
* @note The setting of these parameters by function @ref LL_DAC_Init()
|
||||||
|
* is conditioned to DAC state:
|
||||||
|
* DAC instance must be disabled.
|
||||||
|
* @param DACx DAC instance
|
||||||
|
* @param DAC_Channel This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_DAC_CHANNEL_1
|
||||||
|
* @arg @ref LL_DAC_CHANNEL_2
|
||||||
|
* @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: DAC registers are initialized
|
||||||
|
* - ERROR: DAC registers are not initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_ALL_INSTANCE(DACx));
|
||||||
|
assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
|
||||||
|
assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
|
||||||
|
assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
|
||||||
|
assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
|
||||||
|
if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
|
||||||
|
{
|
||||||
|
assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Note: Hardware constraint (refer to description of this function) */
|
||||||
|
/* DAC instance must be disabled. */
|
||||||
|
if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
|
||||||
|
{
|
||||||
|
/* Configuration of DAC channel: */
|
||||||
|
/* - TriggerSource */
|
||||||
|
/* - WaveAutoGeneration */
|
||||||
|
/* - OutputBuffer */
|
||||||
|
if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
|
||||||
|
{
|
||||||
|
MODIFY_REG(DACx->CR,
|
||||||
|
( DAC_CR_TSEL1
|
||||||
|
| DAC_CR_WAVE1
|
||||||
|
| DAC_CR_MAMP1
|
||||||
|
| DAC_CR_BOFF1
|
||||||
|
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||||
|
,
|
||||||
|
( DAC_InitStruct->TriggerSource
|
||||||
|
| DAC_InitStruct->WaveAutoGeneration
|
||||||
|
| DAC_InitStruct->WaveAutoGenerationConfig
|
||||||
|
| DAC_InitStruct->OutputBuffer
|
||||||
|
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||||
|
);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
MODIFY_REG(DACx->CR,
|
||||||
|
( DAC_CR_TSEL1
|
||||||
|
| DAC_CR_WAVE1
|
||||||
|
| DAC_CR_BOFF1
|
||||||
|
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||||
|
,
|
||||||
|
( DAC_InitStruct->TriggerSource
|
||||||
|
| LL_DAC_WAVE_AUTO_GENERATION_NONE
|
||||||
|
| DAC_InitStruct->OutputBuffer
|
||||||
|
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
|
||||||
|
);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Initialization error: DAC instance is not disabled. */
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_DAC_InitTypeDef field to default value.
|
||||||
|
* @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
|
||||||
|
{
|
||||||
|
/* Set DAC_InitStruct fields to default values */
|
||||||
|
DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
|
||||||
|
DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
|
||||||
|
/* Note: Parameter discarded if wave auto generation is disabled, */
|
||||||
|
/* set anyway to its default value. */
|
||||||
|
DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
|
||||||
|
DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* DAC */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,331 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_dma.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief DMA LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_dma.h"
|
||||||
|
#include "stm32f1xx_ll_bus.h"
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (DMA1) || defined (DMA2)
|
||||||
|
|
||||||
|
/** @defgroup DMA_LL DMA
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @addtogroup DMA_LL_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
|
||||||
|
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
|
||||||
|
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
|
||||||
|
|
||||||
|
#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
|
||||||
|
((__VALUE__) == LL_DMA_MODE_CIRCULAR))
|
||||||
|
|
||||||
|
#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
|
||||||
|
((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
|
||||||
|
|
||||||
|
#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
|
||||||
|
((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
|
||||||
|
|
||||||
|
#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
|
||||||
|
((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
|
||||||
|
((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
|
||||||
|
|
||||||
|
#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
|
||||||
|
((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
|
||||||
|
((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
|
||||||
|
|
||||||
|
#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
|
||||||
|
|
||||||
|
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
|
||||||
|
((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
|
||||||
|
((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
|
||||||
|
((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
|
||||||
|
|
||||||
|
#if defined (DMA2)
|
||||||
|
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
|
||||||
|
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_5) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_6) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_7))) || \
|
||||||
|
(((INSTANCE) == DMA2) && \
|
||||||
|
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_5))))
|
||||||
|
#else
|
||||||
|
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
|
||||||
|
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_2) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_3) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_4) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_5) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_6) || \
|
||||||
|
((CHANNEL) == LL_DMA_CHANNEL_7))))
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup DMA_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DMA_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize the DMA registers to their default reset values.
|
||||||
|
* @param DMAx DMAx Instance
|
||||||
|
* @param Channel This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_1
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_2
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_3
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_4
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_5
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_6
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_7
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: DMA registers are de-initialized
|
||||||
|
* - ERROR: DMA registers are not de-initialized
|
||||||
|
*/
|
||||||
|
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
|
||||||
|
{
|
||||||
|
DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the DMA Instance DMAx and Channel parameters*/
|
||||||
|
assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
|
||||||
|
|
||||||
|
tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
|
||||||
|
|
||||||
|
/* Disable the selected DMAx_Channely */
|
||||||
|
CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
|
||||||
|
|
||||||
|
/* Reset DMAx_Channely control register */
|
||||||
|
LL_DMA_WriteReg(tmp, CCR, 0U);
|
||||||
|
|
||||||
|
/* Reset DMAx_Channely remaining bytes register */
|
||||||
|
LL_DMA_WriteReg(tmp, CNDTR, 0U);
|
||||||
|
|
||||||
|
/* Reset DMAx_Channely peripheral address register */
|
||||||
|
LL_DMA_WriteReg(tmp, CPAR, 0U);
|
||||||
|
|
||||||
|
/* Reset DMAx_Channely memory address register */
|
||||||
|
LL_DMA_WriteReg(tmp, CMAR, 0U);
|
||||||
|
|
||||||
|
if (Channel == LL_DMA_CHANNEL_1)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMAx Channel1 */
|
||||||
|
LL_DMA_ClearFlag_GI1(DMAx);
|
||||||
|
}
|
||||||
|
else if (Channel == LL_DMA_CHANNEL_2)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMAx Channel2 */
|
||||||
|
LL_DMA_ClearFlag_GI2(DMAx);
|
||||||
|
}
|
||||||
|
else if (Channel == LL_DMA_CHANNEL_3)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMAx Channel3 */
|
||||||
|
LL_DMA_ClearFlag_GI3(DMAx);
|
||||||
|
}
|
||||||
|
else if (Channel == LL_DMA_CHANNEL_4)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMAx Channel4 */
|
||||||
|
LL_DMA_ClearFlag_GI4(DMAx);
|
||||||
|
}
|
||||||
|
else if (Channel == LL_DMA_CHANNEL_5)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMAx Channel5 */
|
||||||
|
LL_DMA_ClearFlag_GI5(DMAx);
|
||||||
|
}
|
||||||
|
|
||||||
|
else if (Channel == LL_DMA_CHANNEL_6)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMAx Channel6 */
|
||||||
|
LL_DMA_ClearFlag_GI6(DMAx);
|
||||||
|
}
|
||||||
|
else if (Channel == LL_DMA_CHANNEL_7)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMAx Channel7 */
|
||||||
|
LL_DMA_ClearFlag_GI7(DMAx);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
|
||||||
|
* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
|
||||||
|
* @arg @ref __LL_DMA_GET_INSTANCE
|
||||||
|
* @arg @ref __LL_DMA_GET_CHANNEL
|
||||||
|
* @param DMAx DMAx Instance
|
||||||
|
* @param Channel This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_1
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_2
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_3
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_4
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_5
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_6
|
||||||
|
* @arg @ref LL_DMA_CHANNEL_7
|
||||||
|
* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: DMA registers are initialized
|
||||||
|
* - ERROR: Not applicable
|
||||||
|
*/
|
||||||
|
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
|
||||||
|
{
|
||||||
|
/* Check the DMA Instance DMAx and Channel parameters*/
|
||||||
|
assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
|
||||||
|
|
||||||
|
/* Check the DMA parameters from DMA_InitStruct */
|
||||||
|
assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
|
||||||
|
assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
|
||||||
|
assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
|
||||||
|
assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
|
||||||
|
assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
|
||||||
|
assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
|
||||||
|
assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
|
||||||
|
assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
|
||||||
|
|
||||||
|
/*---------------------------- DMAx CCR Configuration ------------------------
|
||||||
|
* Configure DMAx_Channely: data transfer direction, data transfer mode,
|
||||||
|
* peripheral and memory increment mode,
|
||||||
|
* data size alignment and priority level with parameters :
|
||||||
|
* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
|
||||||
|
* - Mode: DMA_CCR_CIRC bit
|
||||||
|
* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
|
||||||
|
* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
|
||||||
|
* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
|
||||||
|
* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
|
||||||
|
* - Priority: DMA_CCR_PL[1:0] bits
|
||||||
|
*/
|
||||||
|
LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
|
||||||
|
DMA_InitStruct->Mode | \
|
||||||
|
DMA_InitStruct->PeriphOrM2MSrcIncMode | \
|
||||||
|
DMA_InitStruct->MemoryOrM2MDstIncMode | \
|
||||||
|
DMA_InitStruct->PeriphOrM2MSrcDataSize | \
|
||||||
|
DMA_InitStruct->MemoryOrM2MDstDataSize | \
|
||||||
|
DMA_InitStruct->Priority);
|
||||||
|
|
||||||
|
/*-------------------------- DMAx CMAR Configuration -------------------------
|
||||||
|
* Configure the memory or destination base address with parameter :
|
||||||
|
* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
|
||||||
|
*/
|
||||||
|
LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
|
||||||
|
|
||||||
|
/*-------------------------- DMAx CPAR Configuration -------------------------
|
||||||
|
* Configure the peripheral or source base address with parameter :
|
||||||
|
* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
|
||||||
|
*/
|
||||||
|
LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
|
||||||
|
|
||||||
|
/*--------------------------- DMAx CNDTR Configuration -----------------------
|
||||||
|
* Configure the peripheral base address with parameter :
|
||||||
|
* - NbData: DMA_CNDTR_NDT[15:0] bits
|
||||||
|
*/
|
||||||
|
LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
|
||||||
|
* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
|
||||||
|
{
|
||||||
|
/* Set DMA_InitStruct fields to default values */
|
||||||
|
DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
|
||||||
|
DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
|
||||||
|
DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
|
||||||
|
DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
|
||||||
|
DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
|
||||||
|
DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
|
||||||
|
DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
|
||||||
|
DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
|
||||||
|
DMA_InitStruct->NbData = 0x00000000U;
|
||||||
|
DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* DMA1 || DMA2 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,232 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_exti.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief EXTI LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_exti.h"
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (EXTI)
|
||||||
|
|
||||||
|
/** @defgroup EXTI_LL EXTI
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @addtogroup EXTI_LL_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
|
||||||
|
|
||||||
|
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|
||||||
|
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|
||||||
|
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
|
||||||
|
|
||||||
|
|
||||||
|
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
|
||||||
|
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
|
||||||
|
|| ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
|
||||||
|
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup EXTI_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize the EXTI registers to their default reset values.
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: EXTI registers are de-initialized
|
||||||
|
* - ERROR: not applicable
|
||||||
|
*/
|
||||||
|
uint32_t LL_EXTI_DeInit(void)
|
||||||
|
{
|
||||||
|
/* Interrupt mask register set to default reset values */
|
||||||
|
LL_EXTI_WriteReg(IMR, 0x00000000U);
|
||||||
|
/* Event mask register set to default reset values */
|
||||||
|
LL_EXTI_WriteReg(EMR, 0x00000000U);
|
||||||
|
/* Rising Trigger selection register set to default reset values */
|
||||||
|
LL_EXTI_WriteReg(RTSR, 0x00000000U);
|
||||||
|
/* Falling Trigger selection register set to default reset values */
|
||||||
|
LL_EXTI_WriteReg(FTSR, 0x00000000U);
|
||||||
|
/* Software interrupt event register set to default reset values */
|
||||||
|
LL_EXTI_WriteReg(SWIER, 0x00000000U);
|
||||||
|
/* Pending register clear */
|
||||||
|
LL_EXTI_WriteReg(PR, 0x000FFFFFU);
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
|
||||||
|
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: EXTI registers are initialized
|
||||||
|
* - ERROR: not applicable
|
||||||
|
*/
|
||||||
|
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
|
||||||
|
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
|
||||||
|
|
||||||
|
/* ENABLE LineCommand */
|
||||||
|
if (EXTI_InitStruct->LineCommand != DISABLE)
|
||||||
|
{
|
||||||
|
assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
|
||||||
|
|
||||||
|
/* Configure EXTI Lines in range from 0 to 31 */
|
||||||
|
if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
|
||||||
|
{
|
||||||
|
switch (EXTI_InitStruct->Mode)
|
||||||
|
{
|
||||||
|
case LL_EXTI_MODE_IT:
|
||||||
|
/* First Disable Event on provided Lines */
|
||||||
|
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
/* Then Enable IT on provided Lines */
|
||||||
|
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
break;
|
||||||
|
case LL_EXTI_MODE_EVENT:
|
||||||
|
/* First Disable IT on provided Lines */
|
||||||
|
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
/* Then Enable Event on provided Lines */
|
||||||
|
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
break;
|
||||||
|
case LL_EXTI_MODE_IT_EVENT:
|
||||||
|
/* Directly Enable IT & Event on provided Lines */
|
||||||
|
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
status = ERROR;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
|
||||||
|
{
|
||||||
|
switch (EXTI_InitStruct->Trigger)
|
||||||
|
{
|
||||||
|
case LL_EXTI_TRIGGER_RISING:
|
||||||
|
/* First Disable Falling Trigger on provided Lines */
|
||||||
|
LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
/* Then Enable Rising Trigger on provided Lines */
|
||||||
|
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
break;
|
||||||
|
case LL_EXTI_TRIGGER_FALLING:
|
||||||
|
/* First Disable Rising Trigger on provided Lines */
|
||||||
|
LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
/* Then Enable Falling Trigger on provided Lines */
|
||||||
|
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
break;
|
||||||
|
case LL_EXTI_TRIGGER_RISING_FALLING:
|
||||||
|
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
status = ERROR;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* DISABLE LineCommand */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* De-configure EXTI Lines in range from 0 to 31 */
|
||||||
|
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
|
||||||
|
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||||
|
{
|
||||||
|
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
|
||||||
|
EXTI_InitStruct->LineCommand = DISABLE;
|
||||||
|
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
|
||||||
|
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* defined (EXTI) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,931 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_fsmc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief FSMC Low Layer HAL module driver.
|
||||||
|
*
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
|
||||||
|
* + Initialization/de-initialization functions
|
||||||
|
* + Peripheral Control functions
|
||||||
|
* + Peripheral State functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
=============================================================================
|
||||||
|
##### FSMC peripheral features #####
|
||||||
|
=============================================================================
|
||||||
|
[..] The Flexible static memory controller (FSMC) includes following memory controllers:
|
||||||
|
(+) The NOR/PSRAM memory controller
|
||||||
|
(+) The PC Card memory controller
|
||||||
|
(+) The NAND memory controller
|
||||||
|
(PC Card and NAND controllers available only on STM32F101xE, STM32F103xE, STM32F101xG and STM32F103xG)
|
||||||
|
|
||||||
|
[..] The FSMC functional block makes the interface with synchronous and asynchronous static
|
||||||
|
memories and 16-bit PC memory cards. Its main purposes are:
|
||||||
|
(+) to translate AHB transactions into the appropriate external device protocol.
|
||||||
|
(+) to meet the access time requirements of the external memory devices.
|
||||||
|
|
||||||
|
[..] All external memories share the addresses, data and control signals with the controller.
|
||||||
|
Each external device is accessed by means of a unique Chip Select. The FSMC performs
|
||||||
|
only one access at a time to an external device.
|
||||||
|
The main features of the FSMC controller are the following:
|
||||||
|
(+) Interface with static-memory mapped devices including:
|
||||||
|
(++) Static random access memory (SRAM).
|
||||||
|
(++) NOR Flash memory.
|
||||||
|
(++) PSRAM (4 memory banks).
|
||||||
|
(++) 16-bit PC Card compatible devices.
|
||||||
|
(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
|
||||||
|
data.
|
||||||
|
(+) Independent Chip Select control for each memory bank.
|
||||||
|
(+) Independent configuration for each memory bank.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(FSMC_BANK1)
|
||||||
|
|
||||||
|
#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
|
||||||
|
|
||||||
|
/** @defgroup FSMC_LL FSMC Low Layer
|
||||||
|
* @brief FSMC driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions
|
||||||
|
* @brief NORSRAM Controller functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use NORSRAM device driver #####
|
||||||
|
==============================================================================
|
||||||
|
|
||||||
|
[..]
|
||||||
|
This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
|
||||||
|
to run the NORSRAM external devices.
|
||||||
|
|
||||||
|
(+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
|
||||||
|
(+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
|
||||||
|
(+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
|
||||||
|
(+) FSMC NORSRAM bank extended timing configuration using the function
|
||||||
|
FSMC_NORSRAM_Extended_Timing_Init()
|
||||||
|
(+) FSMC NORSRAM bank enable/disable write operation using the functions
|
||||||
|
FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Initialization and de_initialization functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This section provides functions allowing to:
|
||||||
|
(+) Initialize and configure the FSMC NORSRAM interface
|
||||||
|
(+) De-initialize the FSMC NORSRAM interface
|
||||||
|
(+) Configure the FSMC clock and associated GPIOs
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the FSMC_NORSRAM device according to the specified
|
||||||
|
* control parameters in the FSMC_NORSRAM_InitTypeDef
|
||||||
|
* @param Device: Pointer to NORSRAM device instance
|
||||||
|
* @param Init: Pointer to NORSRAM Initialization structure
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
|
||||||
|
assert_param(IS_FSMC_MUX(Init->DataAddressMux));
|
||||||
|
assert_param(IS_FSMC_MEMORY(Init->MemoryType));
|
||||||
|
assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
|
||||||
|
assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
|
||||||
|
assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
|
||||||
|
assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
|
||||||
|
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
|
||||||
|
assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
|
||||||
|
assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
|
||||||
|
assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
|
||||||
|
assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
|
||||||
|
assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
|
||||||
|
|
||||||
|
/* Disable NORSRAM Device */
|
||||||
|
__FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
|
||||||
|
|
||||||
|
/* Set NORSRAM device control parameters */
|
||||||
|
if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
|
||||||
|
{
|
||||||
|
MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE
|
||||||
|
| Init->DataAddressMux
|
||||||
|
| Init->MemoryType
|
||||||
|
| Init->MemoryDataWidth
|
||||||
|
| Init->BurstAccessMode
|
||||||
|
| Init->WaitSignalPolarity
|
||||||
|
| Init->WrapMode
|
||||||
|
| Init->WaitSignalActive
|
||||||
|
| Init->WriteOperation
|
||||||
|
| Init->WaitSignal
|
||||||
|
| Init->ExtendedMode
|
||||||
|
| Init->AsynchronousWait
|
||||||
|
| Init->WriteBurst
|
||||||
|
)
|
||||||
|
);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE
|
||||||
|
| Init->DataAddressMux
|
||||||
|
| Init->MemoryType
|
||||||
|
| Init->MemoryDataWidth
|
||||||
|
| Init->BurstAccessMode
|
||||||
|
| Init->WaitSignalPolarity
|
||||||
|
| Init->WrapMode
|
||||||
|
| Init->WaitSignalActive
|
||||||
|
| Init->WriteOperation
|
||||||
|
| Init->WaitSignal
|
||||||
|
| Init->ExtendedMode
|
||||||
|
| Init->AsynchronousWait
|
||||||
|
| Init->WriteBurst
|
||||||
|
)
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DeInitialize the FSMC_NORSRAM peripheral
|
||||||
|
* @param Device: Pointer to NORSRAM device instance
|
||||||
|
* @param ExDevice: Pointer to NORSRAM extended mode device instance
|
||||||
|
* @param Bank: NORSRAM bank number
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
|
||||||
|
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
|
||||||
|
|
||||||
|
/* Disable the FSMC_NORSRAM device */
|
||||||
|
__FSMC_NORSRAM_DISABLE(Device, Bank);
|
||||||
|
|
||||||
|
/* De-initialize the FSMC_NORSRAM device */
|
||||||
|
/* FSMC_NORSRAM_BANK1 */
|
||||||
|
if(Bank == FSMC_NORSRAM_BANK1)
|
||||||
|
{
|
||||||
|
Device->BTCR[Bank] = 0x000030DBU;
|
||||||
|
}
|
||||||
|
/* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
Device->BTCR[Bank] = 0x000030D2U;
|
||||||
|
}
|
||||||
|
|
||||||
|
Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
|
||||||
|
ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the FSMC_NORSRAM Timing according to the specified
|
||||||
|
* parameters in the FSMC_NORSRAM_TimingTypeDef
|
||||||
|
* @param Device: Pointer to NORSRAM device instance
|
||||||
|
* @param Timing: Pointer to NORSRAM Timing structure
|
||||||
|
* @param Bank: NORSRAM bank number
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
|
||||||
|
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
|
||||||
|
assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
|
||||||
|
assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
|
||||||
|
assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
|
||||||
|
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
|
||||||
|
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
|
||||||
|
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
|
||||||
|
|
||||||
|
/* Set FSMC_NORSRAM device timing parameters */
|
||||||
|
MODIFY_REG(Device->BTCR[Bank + 1U], \
|
||||||
|
BTR_CLEAR_MASK, \
|
||||||
|
(uint32_t)(Timing->AddressSetupTime | \
|
||||||
|
((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | \
|
||||||
|
((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) | \
|
||||||
|
((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) | \
|
||||||
|
(((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \
|
||||||
|
(((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) | \
|
||||||
|
(Timing->AccessMode)));
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
|
||||||
|
* parameters in the FSMC_NORSRAM_TimingTypeDef
|
||||||
|
* @param Device: Pointer to NORSRAM device instance
|
||||||
|
* @param Timing: Pointer to NORSRAM Timing structure
|
||||||
|
* @param Bank: NORSRAM bank number
|
||||||
|
* @param ExtendedMode FSMC Extended Mode
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_EXTENDED_MODE_DISABLE
|
||||||
|
* @arg FSMC_EXTENDED_MODE_ENABLE
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
|
||||||
|
|
||||||
|
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
|
||||||
|
if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
|
||||||
|
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
|
||||||
|
assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
|
||||||
|
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
|
||||||
|
assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
|
||||||
|
#else
|
||||||
|
assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
|
||||||
|
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
||||||
|
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
|
||||||
|
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
|
||||||
|
|
||||||
|
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
|
||||||
|
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
|
||||||
|
MODIFY_REG(Device->BWTR[Bank], \
|
||||||
|
BWTR_CLEAR_MASK, \
|
||||||
|
(uint32_t)(Timing->AddressSetupTime | \
|
||||||
|
((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \
|
||||||
|
((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \
|
||||||
|
Timing->AccessMode | \
|
||||||
|
((Timing->BusTurnAroundDuration) << FSMC_BWTRx_BUSTURN_Pos)));
|
||||||
|
#else
|
||||||
|
MODIFY_REG(Device->BWTR[Bank], \
|
||||||
|
BWTR_CLEAR_MASK, \
|
||||||
|
(uint32_t)(Timing->AddressSetupTime | \
|
||||||
|
((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \
|
||||||
|
((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \
|
||||||
|
Timing->AccessMode | \
|
||||||
|
(((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \
|
||||||
|
(((Timing->DataLatency) - 2U) << FSMC_BWTRx_DATLAT_Pos)));
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
Device->BWTR[Bank] = 0x0FFFFFFFU;
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_NORSRAM_Group2 Control functions
|
||||||
|
* @brief management functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### FSMC_NORSRAM Control functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection provides a set of functions allowing to control dynamically
|
||||||
|
the FSMC NORSRAM interface.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables dynamically FSMC_NORSRAM write operation.
|
||||||
|
* @param Device: Pointer to NORSRAM device instance
|
||||||
|
* @param Bank: NORSRAM bank number
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
|
||||||
|
|
||||||
|
/* Enable write operation */
|
||||||
|
SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables dynamically FSMC_NORSRAM write operation.
|
||||||
|
* @param Device: Pointer to NORSRAM device instance
|
||||||
|
* @param Bank: NORSRAM bank number
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
|
||||||
|
|
||||||
|
/* Disable write operation */
|
||||||
|
CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
|
||||||
|
/** @defgroup FSMC_NAND FSMC NAND Controller functions
|
||||||
|
* @brief NAND Controller functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use NAND device driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This driver contains a set of APIs to interface with the FSMC NAND banks in order
|
||||||
|
to run the NAND external devices.
|
||||||
|
|
||||||
|
(+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
|
||||||
|
(+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
|
||||||
|
(+) FSMC NAND bank common space timing configuration using the function
|
||||||
|
FSMC_NAND_CommonSpace_Timing_Init()
|
||||||
|
(+) FSMC NAND bank attribute space timing configuration using the function
|
||||||
|
FSMC_NAND_AttributeSpace_Timing_Init()
|
||||||
|
(+) FSMC NAND bank enable/disable ECC correction feature using the functions
|
||||||
|
FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
|
||||||
|
(+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Initialization and de_initialization functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This section provides functions allowing to:
|
||||||
|
(+) Initialize and configure the FSMC NAND interface
|
||||||
|
(+) De-initialize the FSMC NAND interface
|
||||||
|
(+) Configure the FSMC clock and associated GPIOs
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC_NAND device according to the specified
|
||||||
|
* control parameters in the FSMC_NAND_HandleTypeDef
|
||||||
|
* @param Device: Pointer to NAND device instance
|
||||||
|
* @param Init: Pointer to NAND Initialization structure
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
|
||||||
|
assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
|
||||||
|
assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
|
||||||
|
assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
|
||||||
|
assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
|
||||||
|
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
|
||||||
|
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
|
||||||
|
|
||||||
|
/* Set NAND device control parameters */
|
||||||
|
if (Init->NandBank == FSMC_NAND_BANK2)
|
||||||
|
{
|
||||||
|
/* NAND bank 2 registers configuration */
|
||||||
|
MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
|
||||||
|
FSMC_PCR_MEMORY_TYPE_NAND |
|
||||||
|
Init->MemoryDataWidth |
|
||||||
|
Init->EccComputation |
|
||||||
|
Init->ECCPageSize |
|
||||||
|
((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
|
||||||
|
((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* NAND bank 3 registers configuration */
|
||||||
|
MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
|
||||||
|
FSMC_PCR_MEMORY_TYPE_NAND |
|
||||||
|
Init->MemoryDataWidth |
|
||||||
|
Init->EccComputation |
|
||||||
|
Init->ECCPageSize |
|
||||||
|
((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
|
||||||
|
((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC_NAND Common space Timing according to the specified
|
||||||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||||||
|
* @param Device: Pointer to NAND device instance
|
||||||
|
* @param Timing: Pointer to NAND timing structure
|
||||||
|
* @param Bank: NAND bank number
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(Bank));
|
||||||
|
|
||||||
|
/* Set FMC_NAND device timing parameters */
|
||||||
|
if(Bank == FSMC_NAND_BANK2)
|
||||||
|
{
|
||||||
|
/* NAND bank 2 registers configuration */
|
||||||
|
MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \
|
||||||
|
((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \
|
||||||
|
((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \
|
||||||
|
((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* NAND bank 3 registers configuration */
|
||||||
|
MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \
|
||||||
|
((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \
|
||||||
|
((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \
|
||||||
|
((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
|
||||||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||||||
|
* @param Device: Pointer to NAND device instance
|
||||||
|
* @param Timing: Pointer to NAND timing structure
|
||||||
|
* @param Bank: NAND bank number
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(Bank));
|
||||||
|
|
||||||
|
/* Set FMC_NAND device timing parameters */
|
||||||
|
if(Bank == FSMC_NAND_BANK2)
|
||||||
|
{
|
||||||
|
/* NAND bank 2 registers configuration */
|
||||||
|
MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \
|
||||||
|
((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
|
||||||
|
((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
|
||||||
|
((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* NAND bank 3 registers configuration */
|
||||||
|
MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \
|
||||||
|
((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
|
||||||
|
((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
|
||||||
|
((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DeInitializes the FSMC_NAND device
|
||||||
|
* @param Device: Pointer to NAND device instance
|
||||||
|
* @param Bank: NAND bank number
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(Bank));
|
||||||
|
|
||||||
|
/* Disable the NAND Bank */
|
||||||
|
__FSMC_NAND_DISABLE(Device, Bank);
|
||||||
|
|
||||||
|
/* De-initialize the NAND Bank */
|
||||||
|
if(Bank == FSMC_NAND_BANK2)
|
||||||
|
{
|
||||||
|
/* Set the FSMC_NAND_BANK2 registers to their reset values */
|
||||||
|
WRITE_REG(Device->PCR2, 0x00000018U);
|
||||||
|
WRITE_REG(Device->SR2, 0x00000040U);
|
||||||
|
WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
|
||||||
|
WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
|
||||||
|
}
|
||||||
|
/* FSMC_Bank3_NAND */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Set the FSMC_NAND_BANK3 registers to their reset values */
|
||||||
|
WRITE_REG(Device->PCR3, 0x00000018U);
|
||||||
|
WRITE_REG(Device->SR3, 0x00000040U);
|
||||||
|
WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
|
||||||
|
WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions
|
||||||
|
* @brief management functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### FSMC_NAND Control functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This subsection provides a set of functions allowing to control dynamically
|
||||||
|
the FSMC NAND interface.
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables dynamically FSMC_NAND ECC feature.
|
||||||
|
* @param Device: Pointer to NAND device instance
|
||||||
|
* @param Bank: NAND bank number
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(Bank));
|
||||||
|
|
||||||
|
/* Enable ECC feature */
|
||||||
|
if(Bank == FSMC_NAND_BANK2)
|
||||||
|
{
|
||||||
|
SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables dynamically FSMC_NAND ECC feature.
|
||||||
|
* @param Device: Pointer to NAND device instance
|
||||||
|
* @param Bank: NAND bank number
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(Bank));
|
||||||
|
|
||||||
|
/* Disable ECC feature */
|
||||||
|
if(Bank == FSMC_NAND_BANK2)
|
||||||
|
{
|
||||||
|
CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables dynamically FSMC_NAND ECC feature.
|
||||||
|
* @param Device: Pointer to NAND device instance
|
||||||
|
* @param ECCval: Pointer to ECC value
|
||||||
|
* @param Bank: NAND bank number
|
||||||
|
* @param Timeout: Timeout wait value
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
|
||||||
|
{
|
||||||
|
uint32_t tickstart = 0U;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NAND_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(Bank));
|
||||||
|
|
||||||
|
/* Get tick */
|
||||||
|
tickstart = HAL_GetTick();
|
||||||
|
|
||||||
|
/* Wait until FIFO is empty */
|
||||||
|
while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
|
||||||
|
{
|
||||||
|
/* Check for the Timeout */
|
||||||
|
if(Timeout != HAL_MAX_DELAY)
|
||||||
|
{
|
||||||
|
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||||
|
{
|
||||||
|
return HAL_TIMEOUT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(Bank == FSMC_NAND_BANK2)
|
||||||
|
{
|
||||||
|
/* Get the ECCR2 register value */
|
||||||
|
*ECCval = (uint32_t)Device->ECCR2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Get the ECCR3 register value */
|
||||||
|
*ECCval = (uint32_t)Device->ECCR3;
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions
|
||||||
|
* @brief PCCARD Controller functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### How to use PCCARD device driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
|
||||||
|
to run the PCCARD/compact flash external devices.
|
||||||
|
|
||||||
|
(+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
|
||||||
|
(+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
|
||||||
|
(+) FSMC PCCARD bank common space timing configuration using the function
|
||||||
|
FSMC_PCCARD_CommonSpace_Timing_Init()
|
||||||
|
(+) FSMC PCCARD bank attribute space timing configuration using the function
|
||||||
|
FSMC_PCCARD_AttributeSpace_Timing_Init()
|
||||||
|
(+) FSMC PCCARD bank IO space timing configuration using the function
|
||||||
|
FSMC_PCCARD_IOSpace_Timing_Init()
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### Initialization and de_initialization functions #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
This section provides functions allowing to:
|
||||||
|
(+) Initialize and configure the FSMC PCCARD interface
|
||||||
|
(+) De-initialize the FSMC PCCARD interface
|
||||||
|
(+) Configure the FSMC clock and associated GPIOs
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC_PCCARD device according to the specified
|
||||||
|
* control parameters in the FSMC_PCCARD_HandleTypeDef
|
||||||
|
* @param Device: Pointer to PCCARD device instance
|
||||||
|
* @param Init: Pointer to PCCARD Initialization structure
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
|
||||||
|
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
|
||||||
|
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
|
||||||
|
|
||||||
|
/* Set FSMC_PCCARD device control parameters */
|
||||||
|
MODIFY_REG(Device->PCR4,
|
||||||
|
(FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN | FSMC_PCRx_PWID |
|
||||||
|
FSMC_PCRx_TCLR | FSMC_PCRx_TAR),
|
||||||
|
(FSMC_PCR_MEMORY_TYPE_PCCARD |
|
||||||
|
Init->Waitfeature |
|
||||||
|
FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |
|
||||||
|
(Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos) |
|
||||||
|
(Init->TARSetupTime << FSMC_PCRx_TAR_Pos)));
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
|
||||||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||||||
|
* @param Device: Pointer to PCCARD device instance
|
||||||
|
* @param Timing: Pointer to PCCARD timing structure
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||||||
|
|
||||||
|
/* Set PCCARD timing parameters */
|
||||||
|
MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
|
||||||
|
(Timing->SetupTime |
|
||||||
|
((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
|
||||||
|
((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
|
||||||
|
((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
|
||||||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||||||
|
* @param Device: Pointer to PCCARD device instance
|
||||||
|
* @param Timing: Pointer to PCCARD timing structure
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||||||
|
|
||||||
|
/* Set PCCARD timing parameters */
|
||||||
|
MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \
|
||||||
|
(Timing->SetupTime | \
|
||||||
|
((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
|
||||||
|
((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
|
||||||
|
((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
|
||||||
|
* parameters in the FSMC_NAND_PCC_TimingTypeDef
|
||||||
|
* @param Device: Pointer to PCCARD device instance
|
||||||
|
* @param Timing: Pointer to PCCARD timing structure
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
||||||
|
|
||||||
|
/* Set FSMC_PCCARD device timing parameters */
|
||||||
|
MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
|
||||||
|
(Timing->SetupTime | \
|
||||||
|
(Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | \
|
||||||
|
(Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | \
|
||||||
|
(Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos)));
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DeInitializes the FSMC_PCCARD device
|
||||||
|
* @param Device: Pointer to PCCARD device instance
|
||||||
|
* @retval HAL status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
|
||||||
|
|
||||||
|
/* Disable the FSMC_PCCARD device */
|
||||||
|
__FSMC_PCCARD_DISABLE(Device);
|
||||||
|
|
||||||
|
/* De-initialize the FSMC_PCCARD device */
|
||||||
|
WRITE_REG(Device->PCR4, 0x00000018U);
|
||||||
|
WRITE_REG(Device->SR4, 0x00000040U);
|
||||||
|
WRITE_REG(Device->PMEM4, 0xFCFCFCFCU);
|
||||||
|
WRITE_REG(Device->PATT4, 0xFCFCFCFCU);
|
||||||
|
WRITE_REG(Device->PIO4, 0xFCFCFCFCU);
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#endif /* FSMC_BANK1 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,265 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_gpio.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief GPIO LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_gpio.h"
|
||||||
|
#include "stm32f1xx_ll_bus.h"
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
|
||||||
|
|
||||||
|
/** @addtogroup GPIO_LL
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @addtogroup GPIO_LL_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
|
||||||
|
|
||||||
|
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_ANALOG) ||\
|
||||||
|
((__VALUE__) == LL_GPIO_MODE_FLOATING) ||\
|
||||||
|
((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
|
||||||
|
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
|
||||||
|
((__VALUE__) == LL_GPIO_MODE_ALTERNATE))
|
||||||
|
|
||||||
|
#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
|
||||||
|
((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||||
|
((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
|
||||||
|
|
||||||
|
#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
|
||||||
|
((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
|
||||||
|
|
||||||
|
#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_DOWN) ||\
|
||||||
|
((__VALUE__) == LL_GPIO_PULL_UP))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup GPIO_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup GPIO_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize GPIO registers (Registers restored to their default values).
|
||||||
|
* @param GPIOx GPIO Port
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: GPIO registers are de-initialized
|
||||||
|
* - ERROR: Wrong GPIO Port
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||||
|
|
||||||
|
/* Force and Release reset on clock of GPIOx Port */
|
||||||
|
if (GPIOx == GPIOA)
|
||||||
|
{
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA);
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA);
|
||||||
|
}
|
||||||
|
else if (GPIOx == GPIOB)
|
||||||
|
{
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB);
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB);
|
||||||
|
}
|
||||||
|
else if (GPIOx == GPIOC)
|
||||||
|
{
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC);
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC);
|
||||||
|
}
|
||||||
|
else if (GPIOx == GPIOD)
|
||||||
|
{
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD);
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD);
|
||||||
|
}
|
||||||
|
#if defined(GPIOE)
|
||||||
|
else if (GPIOx == GPIOE)
|
||||||
|
{
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE);
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if defined(GPIOF)
|
||||||
|
else if (GPIOx == GPIOF)
|
||||||
|
{
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF);
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if defined(GPIOG)
|
||||||
|
else if (GPIOx == GPIOG)
|
||||||
|
{
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG);
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
else
|
||||||
|
{
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (status);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
|
||||||
|
* @param GPIOx GPIO Port
|
||||||
|
* @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
|
||||||
|
* that contains the configuration information for the specified GPIO peripheral.
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
|
||||||
|
* - ERROR: Not applicable
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t pinpos = 0x00000000U;
|
||||||
|
uint32_t currentpin = 0x00000000U;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||||
|
assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
|
||||||
|
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
|
||||||
|
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
|
||||||
|
|
||||||
|
/* ------------------------- Configure the port pins ---------------- */
|
||||||
|
/* Initialize pinpos on first pin set */
|
||||||
|
pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
|
||||||
|
|
||||||
|
/* Configure the port pins */
|
||||||
|
while ((((GPIO_InitStruct->Pin) & 0x0000FFFFU) >> pinpos) != 0x00000000U)
|
||||||
|
{
|
||||||
|
/* Get current io position */
|
||||||
|
if(pinpos <8 )
|
||||||
|
{
|
||||||
|
currentpin = (GPIO_InitStruct->Pin) & (0x00000101U << pinpos);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
currentpin = (GPIO_InitStruct->Pin) & ((0x00010001U << (pinpos-8)) | 0x04000000U);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (currentpin)
|
||||||
|
{
|
||||||
|
/* Pin Mode configuration */
|
||||||
|
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
|
||||||
|
|
||||||
|
/* Pull-up Pull down resistor configuration*/
|
||||||
|
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
|
||||||
|
|
||||||
|
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING))
|
||||||
|
{
|
||||||
|
/* Speed mode configuration */
|
||||||
|
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
pinpos++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING))
|
||||||
|
{
|
||||||
|
/* Check Output mode parameters */
|
||||||
|
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
|
||||||
|
|
||||||
|
/* Output mode configuration*/
|
||||||
|
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
|
||||||
|
}
|
||||||
|
return (SUCCESS);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
|
||||||
|
* @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
|
||||||
|
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
||||||
|
{
|
||||||
|
/* Reset GPIO init structure parameters values */
|
||||||
|
GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
|
||||||
|
GPIO_InitStruct->Mode = LL_GPIO_MODE_FLOATING;
|
||||||
|
GPIO_InitStruct->Speed = 0x00000000U;
|
||||||
|
GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
|
||||||
|
GPIO_InitStruct->Pull = LL_GPIO_PULL_DOWN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
@ -0,0 +1,239 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_i2c.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief I2C LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_i2c.h"
|
||||||
|
#include "stm32f1xx_ll_bus.h"
|
||||||
|
#include "stm32f1xx_ll_rcc.h"
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (I2C1) || defined (I2C2)
|
||||||
|
|
||||||
|
/** @defgroup I2C_LL I2C
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @addtogroup I2C_LL_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
|
||||||
|
((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
|
||||||
|
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
|
||||||
|
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
|
||||||
|
|
||||||
|
#define IS_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
|
||||||
|
|
||||||
|
#define IS_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
|
||||||
|
((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
|
||||||
|
|
||||||
|
#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
|
||||||
|
|
||||||
|
#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
|
||||||
|
((__VALUE__) == LL_I2C_NACK))
|
||||||
|
|
||||||
|
#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
|
||||||
|
((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup I2C_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2C_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize the I2C registers to their default reset values.
|
||||||
|
* @param I2Cx I2C Instance.
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: I2C registers are de-initialized
|
||||||
|
* - ERROR: I2C registers are not de-initialized
|
||||||
|
*/
|
||||||
|
uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the I2C Instance I2Cx */
|
||||||
|
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
|
||||||
|
|
||||||
|
if (I2Cx == I2C1)
|
||||||
|
{
|
||||||
|
/* Force reset of I2C clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
|
||||||
|
|
||||||
|
/* Release reset of I2C clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
|
||||||
|
}
|
||||||
|
#if defined(I2C2)
|
||||||
|
else if (I2Cx == I2C2)
|
||||||
|
{
|
||||||
|
/* Force reset of I2C clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
|
||||||
|
|
||||||
|
/* Release reset of I2C clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif /* I2C2 */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
|
||||||
|
* @param I2Cx I2C Instance.
|
||||||
|
* @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: I2C registers are initialized
|
||||||
|
* - ERROR: Not applicable
|
||||||
|
*/
|
||||||
|
uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
|
||||||
|
{
|
||||||
|
LL_RCC_ClocksTypeDef rcc_clocks;
|
||||||
|
|
||||||
|
/* Check the I2C Instance I2Cx */
|
||||||
|
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
|
||||||
|
|
||||||
|
/* Check the I2C parameters from I2C_InitStruct */
|
||||||
|
assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
|
||||||
|
assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
|
||||||
|
assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
|
||||||
|
assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
|
||||||
|
assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
|
||||||
|
assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
|
||||||
|
|
||||||
|
/* Disable the selected I2Cx Peripheral */
|
||||||
|
LL_I2C_Disable(I2Cx);
|
||||||
|
|
||||||
|
/* Retrieve Clock frequencies */
|
||||||
|
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
|
||||||
|
|
||||||
|
/*---------------------------- I2Cx SCL Clock Speed Configuration ------------
|
||||||
|
* Configure the SCL speed :
|
||||||
|
* - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS,
|
||||||
|
* and I2C_CCR_CCR[11:0] bits
|
||||||
|
* - DutyCycle: I2C_CCR_DUTY[7:0] bits
|
||||||
|
*/
|
||||||
|
LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle);
|
||||||
|
|
||||||
|
/*---------------------------- I2Cx OAR1 Configuration -----------------------
|
||||||
|
* Disable, Configure and Enable I2Cx device own address 1 with parameters :
|
||||||
|
* - OwnAddress1: I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits
|
||||||
|
* - OwnAddrSize: I2C_OAR1_ADDMODE bit
|
||||||
|
*/
|
||||||
|
LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
|
||||||
|
|
||||||
|
/*---------------------------- I2Cx MODE Configuration -----------------------
|
||||||
|
* Configure I2Cx peripheral mode with parameter :
|
||||||
|
* - PeripheralMode: I2C_CR1_SMBUS, I2C_CR1_SMBTYPE and I2C_CR1_ENARP bits
|
||||||
|
*/
|
||||||
|
LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
|
||||||
|
|
||||||
|
/* Enable the selected I2Cx Peripheral */
|
||||||
|
LL_I2C_Enable(I2Cx);
|
||||||
|
|
||||||
|
/*---------------------------- I2Cx CR2 Configuration ------------------------
|
||||||
|
* Configure the ACKnowledge or Non ACKnowledge condition
|
||||||
|
* after the address receive match code or next received byte with parameter :
|
||||||
|
* - TypeAcknowledge: I2C_CR2_NACK bit
|
||||||
|
*/
|
||||||
|
LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_I2C_InitTypeDef field to default value.
|
||||||
|
* @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
|
||||||
|
{
|
||||||
|
/* Set I2C_InitStruct fields to default values */
|
||||||
|
I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
|
||||||
|
I2C_InitStruct->ClockSpeed = 5000U;
|
||||||
|
I2C_InitStruct->DutyCycle = LL_I2C_DUTYCYCLE_2;
|
||||||
|
I2C_InitStruct->OwnAddress1 = 0U;
|
||||||
|
I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
|
||||||
|
I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* I2C1 || I2C2 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,103 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_pwr.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief PWR LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_pwr.h"
|
||||||
|
#include "stm32f1xx_ll_bus.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(PWR)
|
||||||
|
|
||||||
|
/** @defgroup PWR_LL PWR
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup PWR_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PWR_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize the PWR registers to their default reset values.
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: PWR registers are de-initialized
|
||||||
|
* - ERROR: not applicable
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_PWR_DeInit(void)
|
||||||
|
{
|
||||||
|
/* Force reset of PWR clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
|
||||||
|
|
||||||
|
/* Release reset of PWR clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* defined(PWR) */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,507 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_rcc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief RCC LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_rcc.h"
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif /* USE_FULL_ASSERT */
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(RCC)
|
||||||
|
|
||||||
|
/** @defgroup RCC_LL RCC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @addtogroup RCC_LL_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined(RCC_PLLI2S_SUPPORT)
|
||||||
|
#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
|
||||||
|
|| ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
|
||||||
|
#endif /* RCC_PLLI2S_SUPPORT */
|
||||||
|
|
||||||
|
#if defined(USB) || defined(USB_OTG_FS)
|
||||||
|
#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
|
||||||
|
#endif /* USB */
|
||||||
|
|
||||||
|
#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/** @defgroup RCC_LL_Private_Functions RCC Private functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
uint32_t RCC_GetSystemClockFreq(void);
|
||||||
|
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
|
||||||
|
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
|
||||||
|
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
|
||||||
|
uint32_t RCC_PLL_GetFreqDomain_SYS(void);
|
||||||
|
#if defined(RCC_PLLI2S_SUPPORT)
|
||||||
|
uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
|
||||||
|
#endif /* RCC_PLLI2S_SUPPORT */
|
||||||
|
#if defined(RCC_PLL2_SUPPORT)
|
||||||
|
uint32_t RCC_PLL2_GetFreqClockFreq(void);
|
||||||
|
#endif /* RCC_PLL2_SUPPORT */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup RCC_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RCC_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset the RCC clock configuration to the default reset state.
|
||||||
|
* @note The default reset state of the clock configuration is given below:
|
||||||
|
* - HSI ON and used as system clock source
|
||||||
|
* - HSE PLL, PLL2, PLL3 OFF
|
||||||
|
* - AHB, APB1 and APB2 prescaler set to 1.
|
||||||
|
* - CSS, MCO OFF
|
||||||
|
* - All interrupts disabled
|
||||||
|
* @note This function doesn't modify the configuration of the
|
||||||
|
* - Peripheral clocks
|
||||||
|
* - LSI, LSE and RTC clocks
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: RCC registers are de-initialized
|
||||||
|
* - ERROR: not applicable
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RCC_DeInit(void)
|
||||||
|
{
|
||||||
|
uint32_t vl_mask = 0U;
|
||||||
|
|
||||||
|
/* Set HSION bit */
|
||||||
|
LL_RCC_HSI_Enable();
|
||||||
|
|
||||||
|
/* Reset SW, HPRE, PPRE, MCOSEL, PLLXTPRE, PLLSRC and ADCPRE bits */
|
||||||
|
vl_mask = 0xFFFFFFFFU;
|
||||||
|
CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL |\
|
||||||
|
RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_ADCPRE));
|
||||||
|
|
||||||
|
#if defined(USB)
|
||||||
|
/* Reset USBPRE bit */
|
||||||
|
CLEAR_BIT(vl_mask, RCC_CFGR_USBPRE);
|
||||||
|
#elif defined(USB_OTG_FS)
|
||||||
|
/* Reset OTGFSPRE bit */
|
||||||
|
CLEAR_BIT(vl_mask, RCC_CFGR_OTGFSPRE);
|
||||||
|
#endif /* USB */
|
||||||
|
|
||||||
|
#if defined(RCC_CFGR_PLLMULL2)
|
||||||
|
/* Set PLL multiplication factor to 2 */
|
||||||
|
vl_mask |= RCC_CFGR_PLLMULL2;
|
||||||
|
#else
|
||||||
|
/* Set PLL multiplication factor to 4 */
|
||||||
|
vl_mask |= RCC_CFGR_PLLMULL4;
|
||||||
|
#endif /* RCC_CFGR_PLLMULL2 */
|
||||||
|
|
||||||
|
LL_RCC_WriteReg(CFGR, vl_mask);
|
||||||
|
|
||||||
|
/* Reset HSEON, HSEBYP, CSSON, PLLON bits */
|
||||||
|
vl_mask = 0xFFFFFFFFU;
|
||||||
|
CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
|
||||||
|
|
||||||
|
#if defined(RCC_CR_PLL2ON)
|
||||||
|
/* Reset PLL2ON bit */
|
||||||
|
CLEAR_BIT(vl_mask, RCC_CR_PLL2ON);
|
||||||
|
#endif /* RCC_CR_PLL2ON */
|
||||||
|
|
||||||
|
#if defined(RCC_CR_PLL3ON)
|
||||||
|
/* Reset PLL3ON bit */
|
||||||
|
CLEAR_BIT(vl_mask, RCC_CR_PLL3ON);
|
||||||
|
#endif /* RCC_CR_PLL3ON */
|
||||||
|
|
||||||
|
LL_RCC_WriteReg(CR, vl_mask);
|
||||||
|
|
||||||
|
/* Set HSITRIM bits to the reset value */
|
||||||
|
LL_RCC_HSI_SetCalibTrimming(0x10U);
|
||||||
|
|
||||||
|
#if defined(RCC_CFGR2_PREDIV1)
|
||||||
|
/* Reset CFGR2 register */
|
||||||
|
vl_mask = 0x00000000U;
|
||||||
|
|
||||||
|
#if defined(RCC_PLL2_SUPPORT)
|
||||||
|
/* Set PLL2 multiplication factor to 8 */
|
||||||
|
vl_mask |= RCC_CFGR2_PLL2MUL8;
|
||||||
|
#endif /* RCC_PLL2_SUPPORT */
|
||||||
|
|
||||||
|
#if defined(RCC_PLLI2S_SUPPORT)
|
||||||
|
/* Set PLL3 multiplication factor to 8 */
|
||||||
|
vl_mask |= RCC_CFGR2_PLL3MUL8;
|
||||||
|
#endif /* RCC_PLLI2S_SUPPORT */
|
||||||
|
|
||||||
|
LL_RCC_WriteReg(CFGR2, vl_mask);
|
||||||
|
#endif /* RCC_CFGR2_PREDIV1 */
|
||||||
|
|
||||||
|
/* Disable all interrupts */
|
||||||
|
LL_RCC_WriteReg(CIR, 0x00000000U);
|
||||||
|
|
||||||
|
return SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RCC_LL_EF_Get_Freq
|
||||||
|
* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
|
||||||
|
* and different peripheral clocks available on the device.
|
||||||
|
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
|
||||||
|
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
|
||||||
|
* @note If SYSCLK source is PLL, function returns values based on
|
||||||
|
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
|
||||||
|
* @note (**) HSI_VALUE is a defined constant but the real value may vary
|
||||||
|
* depending on the variations in voltage and temperature.
|
||||||
|
* @note (***) HSE_VALUE is a defined constant, user has to ensure that
|
||||||
|
* HSE_VALUE is same as the real frequency of the crystal used.
|
||||||
|
* Otherwise, this function may have wrong result.
|
||||||
|
* @note The result of this function could be incorrect when using fractional
|
||||||
|
* value for HSE crystal.
|
||||||
|
* @note This function can be used by the user application to compute the
|
||||||
|
* baud-rate for the communication peripherals or configure other parameters.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
|
||||||
|
* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
|
||||||
|
* must be called to update structure fields. Otherwise, any
|
||||||
|
* configuration based on this function will be incorrect.
|
||||||
|
* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
|
||||||
|
{
|
||||||
|
/* Get SYSCLK frequency */
|
||||||
|
RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
|
||||||
|
|
||||||
|
/* HCLK clock frequency */
|
||||||
|
RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
|
||||||
|
|
||||||
|
/* PCLK1 clock frequency */
|
||||||
|
RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
|
||||||
|
|
||||||
|
/* PCLK2 clock frequency */
|
||||||
|
RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(RCC_CFGR2_I2S2SRC)
|
||||||
|
/**
|
||||||
|
* @brief Return I2Sx clock frequency
|
||||||
|
* @param I2SxSource This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_RCC_I2S2_CLKSOURCE
|
||||||
|
* @arg @ref LL_RCC_I2S3_CLKSOURCE
|
||||||
|
* @retval I2S clock frequency (in Hz)
|
||||||
|
*/
|
||||||
|
uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
|
||||||
|
{
|
||||||
|
uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
|
||||||
|
|
||||||
|
/* Check parameter */
|
||||||
|
assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
|
||||||
|
|
||||||
|
/* I2S1CLK clock frequency */
|
||||||
|
switch (LL_RCC_GetI2SClockSource(I2SxSource))
|
||||||
|
{
|
||||||
|
case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
|
||||||
|
case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
|
||||||
|
i2s_frequency = RCC_GetSystemClockFreq();
|
||||||
|
break;
|
||||||
|
|
||||||
|
case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
|
||||||
|
case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
|
||||||
|
default:
|
||||||
|
i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return i2s_frequency;
|
||||||
|
}
|
||||||
|
#endif /* RCC_CFGR2_I2S2SRC */
|
||||||
|
|
||||||
|
#if defined(USB) || defined(USB_OTG_FS)
|
||||||
|
/**
|
||||||
|
* @brief Return USBx clock frequency
|
||||||
|
* @param USBxSource This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_RCC_USB_CLKSOURCE
|
||||||
|
* @retval USB clock frequency (in Hz)
|
||||||
|
* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
|
||||||
|
*/
|
||||||
|
uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
|
||||||
|
{
|
||||||
|
uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
|
||||||
|
|
||||||
|
/* Check parameter */
|
||||||
|
assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
|
||||||
|
|
||||||
|
/* USBCLK clock frequency */
|
||||||
|
switch (LL_RCC_GetUSBClockSource(USBxSource))
|
||||||
|
{
|
||||||
|
#if defined(RCC_CFGR_USBPRE)
|
||||||
|
case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
|
||||||
|
if (LL_RCC_PLL_IsReady())
|
||||||
|
{
|
||||||
|
usb_frequency = RCC_PLL_GetFreqDomain_SYS();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
|
||||||
|
default:
|
||||||
|
if (LL_RCC_PLL_IsReady())
|
||||||
|
{
|
||||||
|
usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
#endif /* RCC_CFGR_USBPRE */
|
||||||
|
#if defined(RCC_CFGR_OTGFSPRE)
|
||||||
|
/* USBCLK = PLLVCO/2
|
||||||
|
= (2 x PLLCLK) / 2
|
||||||
|
= PLLCLK */
|
||||||
|
case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
|
||||||
|
if (LL_RCC_PLL_IsReady())
|
||||||
|
{
|
||||||
|
usb_frequency = RCC_PLL_GetFreqDomain_SYS();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
/* USBCLK = PLLVCO/3
|
||||||
|
= (2 x PLLCLK) / 3 */
|
||||||
|
case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
|
||||||
|
default:
|
||||||
|
if (LL_RCC_PLL_IsReady())
|
||||||
|
{
|
||||||
|
usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
#endif /* RCC_CFGR_OTGFSPRE */
|
||||||
|
}
|
||||||
|
|
||||||
|
return usb_frequency;
|
||||||
|
}
|
||||||
|
#endif /* USB */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return ADCx clock frequency
|
||||||
|
* @param ADCxSource This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_RCC_ADC_CLKSOURCE
|
||||||
|
* @retval ADC clock frequency (in Hz)
|
||||||
|
*/
|
||||||
|
uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
|
||||||
|
{
|
||||||
|
uint32_t adc_prescaler = 0U;
|
||||||
|
uint32_t adc_frequency = 0U;
|
||||||
|
|
||||||
|
/* Check parameter */
|
||||||
|
assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
|
||||||
|
|
||||||
|
/* Get ADC prescaler */
|
||||||
|
adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
|
||||||
|
|
||||||
|
/* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
|
||||||
|
adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
|
||||||
|
/ (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
|
||||||
|
|
||||||
|
return adc_frequency;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RCC_LL_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return SYSTEM clock frequency
|
||||||
|
* @retval SYSTEM clock frequency (in Hz)
|
||||||
|
*/
|
||||||
|
uint32_t RCC_GetSystemClockFreq(void)
|
||||||
|
{
|
||||||
|
uint32_t frequency = 0U;
|
||||||
|
|
||||||
|
/* Get SYSCLK source -------------------------------------------------------*/
|
||||||
|
switch (LL_RCC_GetSysClkSource())
|
||||||
|
{
|
||||||
|
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
||||||
|
frequency = HSI_VALUE;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
|
||||||
|
frequency = HSE_VALUE;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
|
||||||
|
frequency = RCC_PLL_GetFreqDomain_SYS();
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
frequency = HSI_VALUE;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return frequency;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return HCLK clock frequency
|
||||||
|
* @param SYSCLK_Frequency SYSCLK clock frequency
|
||||||
|
* @retval HCLK clock frequency (in Hz)
|
||||||
|
*/
|
||||||
|
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
|
||||||
|
{
|
||||||
|
/* HCLK clock frequency */
|
||||||
|
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return PCLK1 clock frequency
|
||||||
|
* @param HCLK_Frequency HCLK clock frequency
|
||||||
|
* @retval PCLK1 clock frequency (in Hz)
|
||||||
|
*/
|
||||||
|
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
|
||||||
|
{
|
||||||
|
/* PCLK1 clock frequency */
|
||||||
|
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return PCLK2 clock frequency
|
||||||
|
* @param HCLK_Frequency HCLK clock frequency
|
||||||
|
* @retval PCLK2 clock frequency (in Hz)
|
||||||
|
*/
|
||||||
|
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
|
||||||
|
{
|
||||||
|
/* PCLK2 clock frequency */
|
||||||
|
return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return PLL clock frequency used for system domain
|
||||||
|
* @retval PLL clock frequency (in Hz)
|
||||||
|
*/
|
||||||
|
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
|
||||||
|
{
|
||||||
|
uint32_t pllinputfreq = 0U, pllsource = 0U;
|
||||||
|
|
||||||
|
/* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
|
||||||
|
|
||||||
|
/* Get PLL source */
|
||||||
|
pllsource = LL_RCC_PLL_GetMainSource();
|
||||||
|
|
||||||
|
switch (pllsource)
|
||||||
|
{
|
||||||
|
case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
|
||||||
|
pllinputfreq = HSI_VALUE / 2U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
||||||
|
pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
|
||||||
|
break;
|
||||||
|
|
||||||
|
#if defined(RCC_PLL2_SUPPORT)
|
||||||
|
case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
|
||||||
|
pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
|
||||||
|
break;
|
||||||
|
#endif /* RCC_PLL2_SUPPORT */
|
||||||
|
|
||||||
|
default:
|
||||||
|
pllinputfreq = HSI_VALUE / 2U;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(RCC_PLL2_SUPPORT)
|
||||||
|
/**
|
||||||
|
* @brief Return PLL clock frequency used for system domain
|
||||||
|
* @retval PLL clock frequency (in Hz)
|
||||||
|
*/
|
||||||
|
uint32_t RCC_PLL2_GetFreqClockFreq(void)
|
||||||
|
{
|
||||||
|
return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
|
||||||
|
}
|
||||||
|
#endif /* RCC_PLL2_SUPPORT */
|
||||||
|
|
||||||
|
#if defined(RCC_PLLI2S_SUPPORT)
|
||||||
|
/**
|
||||||
|
* @brief Return PLL clock frequency used for system domain
|
||||||
|
* @retval PLL clock frequency (in Hz)
|
||||||
|
*/
|
||||||
|
uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
|
||||||
|
{
|
||||||
|
return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
|
||||||
|
}
|
||||||
|
#endif /* RCC_PLLI2S_SUPPORT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* defined(RCC) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,558 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_rtc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief RTC LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_rtc.h"
|
||||||
|
#include "stm32f1xx_ll_cortex.h"
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(RTC)
|
||||||
|
|
||||||
|
/** @addtogroup RTC_LL
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @addtogroup RTC_LL_Private_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Default values used for prescaler */
|
||||||
|
#define RTC_ASYNCH_PRESC_DEFAULT 0x00007FFFU
|
||||||
|
|
||||||
|
/* Values used for timeout */
|
||||||
|
#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
|
||||||
|
#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @addtogroup RTC_LL_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0xFFFFFU)
|
||||||
|
|
||||||
|
#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
|
||||||
|
|| ((__VALUE__) == LL_RTC_FORMAT_BCD))
|
||||||
|
|
||||||
|
#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
|
||||||
|
#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
|
||||||
|
#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
|
||||||
|
#define IS_LL_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_NONE) || \
|
||||||
|
((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_RTCCLOCK) || \
|
||||||
|
((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_ALARM) || \
|
||||||
|
((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_SECOND))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup RTC_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RTC_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-Initializes the RTC registers to their default reset values.
|
||||||
|
* @note This function doesn't reset the RTC Clock source and RTC Backup Data
|
||||||
|
* registers.
|
||||||
|
* @param RTCx RTC Instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: RTC registers are de-initialized
|
||||||
|
* - ERROR: RTC registers are not de-initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
|
||||||
|
{
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||||
|
|
||||||
|
/* Disable the write protection for RTC registers */
|
||||||
|
LL_RTC_DisableWriteProtection(RTCx);
|
||||||
|
|
||||||
|
/* Set Initialization mode */
|
||||||
|
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||||
|
{
|
||||||
|
LL_RTC_WriteReg(RTCx,CNTL, 0x0000);
|
||||||
|
LL_RTC_WriteReg(RTCx,CNTH, 0x0000);
|
||||||
|
LL_RTC_WriteReg(RTCx,PRLH, 0x0000);
|
||||||
|
LL_RTC_WriteReg(RTCx,PRLL, 0x8000);
|
||||||
|
LL_RTC_WriteReg(RTCx,CRH, 0x0000);
|
||||||
|
LL_RTC_WriteReg(RTCx,CRL, 0x0020);
|
||||||
|
|
||||||
|
/* Reset Tamper and alternate functions configuration register */
|
||||||
|
LL_RTC_WriteReg(BKP,RTCCR, 0x00000000U);
|
||||||
|
LL_RTC_WriteReg(BKP,CR, 0x00000000U);
|
||||||
|
LL_RTC_WriteReg(BKP,CSR, 0x00000000U);
|
||||||
|
|
||||||
|
/* Exit Initialization Mode */
|
||||||
|
if(LL_RTC_ExitInitMode(RTCx) == ERROR)
|
||||||
|
{
|
||||||
|
return ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Wait till the RTC RSF flag is set */
|
||||||
|
status = LL_RTC_WaitForSynchro(RTCx);
|
||||||
|
|
||||||
|
/* Clear RSF Flag */
|
||||||
|
LL_RTC_ClearFlag_RS(RTCx);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable the write protection for RTC registers */
|
||||||
|
LL_RTC_EnableWriteProtection(RTCx);
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the RTC registers according to the specified parameters
|
||||||
|
* in RTC_InitStruct.
|
||||||
|
* @param RTCx RTC Instance
|
||||||
|
* @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
|
||||||
|
* the configuration information for the RTC peripheral.
|
||||||
|
* @note The RTC Prescaler register is write protected and can be written in
|
||||||
|
* initialization mode only.
|
||||||
|
* @note the user should call LL_RTC_StructInit() or the structure of Prescaler
|
||||||
|
* need to be initialized before RTC init()
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: RTC registers are initialized
|
||||||
|
* - ERROR: RTC registers are not initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||||
|
assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
|
||||||
|
assert_param(IS_LL_RTC_CALIB_OUTPUT(RTC_InitStruct->OutPutSource));
|
||||||
|
/* Waiting for synchro */
|
||||||
|
if(LL_RTC_WaitForSynchro(RTCx) != ERROR)
|
||||||
|
{
|
||||||
|
/* Set Initialization mode */
|
||||||
|
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||||
|
{
|
||||||
|
/* Clear Flag Bits */
|
||||||
|
LL_RTC_ClearFlag_ALR(RTCx);
|
||||||
|
LL_RTC_ClearFlag_OW(RTCx);
|
||||||
|
LL_RTC_ClearFlag_SEC(RTCx);
|
||||||
|
|
||||||
|
if(RTC_InitStruct->OutPutSource != LL_RTC_CALIB_OUTPUT_NONE)
|
||||||
|
{
|
||||||
|
/* Disable the selected Tamper Pin */
|
||||||
|
LL_RTC_TAMPER_Disable(BKP);
|
||||||
|
}
|
||||||
|
/* Set the signal which will be routed to RTC Tamper Pin */
|
||||||
|
LL_RTC_SetOutputSource(BKP, RTC_InitStruct->OutPutSource);
|
||||||
|
|
||||||
|
/* Configure Synchronous and Asynchronous prescaler factor */
|
||||||
|
LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
|
||||||
|
|
||||||
|
/* Exit Initialization Mode */
|
||||||
|
LL_RTC_ExitInitMode(RTCx);
|
||||||
|
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_RTC_InitTypeDef field to default value.
|
||||||
|
* @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
|
||||||
|
{
|
||||||
|
/* Set RTC_InitStruct fields to default values */
|
||||||
|
RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
|
||||||
|
RTC_InitStruct->OutPutSource = LL_RTC_CALIB_OUTPUT_NONE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the RTC current time.
|
||||||
|
* @param RTCx RTC Instance
|
||||||
|
* @param RTC_Format This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_RTC_FORMAT_BIN
|
||||||
|
* @arg @ref LL_RTC_FORMAT_BCD
|
||||||
|
* @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
|
||||||
|
* the time configuration information for the RTC.
|
||||||
|
* @note The user should call LL_RTC_TIME_StructInit() or the structure
|
||||||
|
* of time need to be initialized before time init()
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: RTC Time register is configured
|
||||||
|
* - ERROR: RTC Time register is not configured
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
uint32_t counter_time = 0U;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||||
|
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
|
||||||
|
|
||||||
|
if (RTC_Format == LL_RTC_FORMAT_BIN)
|
||||||
|
{
|
||||||
|
assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
|
||||||
|
assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
|
||||||
|
assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
|
||||||
|
assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
|
||||||
|
assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enter Initialization mode */
|
||||||
|
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||||
|
{
|
||||||
|
/* Check the input parameters format */
|
||||||
|
if (RTC_Format != LL_RTC_FORMAT_BIN)
|
||||||
|
{
|
||||||
|
counter_time = (uint32_t)(((uint32_t)RTC_TimeStruct->Hours * 3600U) + \
|
||||||
|
((uint32_t)RTC_TimeStruct->Minutes * 60U) + \
|
||||||
|
((uint32_t)RTC_TimeStruct->Seconds));
|
||||||
|
LL_RTC_TIME_Set(RTCx, counter_time);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
counter_time = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)) * 3600U) + \
|
||||||
|
((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)) * 60U) + \
|
||||||
|
((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))));
|
||||||
|
LL_RTC_TIME_Set(RTCx, counter_time);
|
||||||
|
}
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
/* Exit Initialization mode */
|
||||||
|
LL_RTC_ExitInitMode(RTCx);
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
|
||||||
|
* @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
|
||||||
|
{
|
||||||
|
/* Time = 00h:00min:00sec */
|
||||||
|
RTC_TimeStruct->Hours = 0U;
|
||||||
|
RTC_TimeStruct->Minutes = 0U;
|
||||||
|
RTC_TimeStruct->Seconds = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the RTC Alarm.
|
||||||
|
* @param RTCx RTC Instance
|
||||||
|
* @param RTC_Format This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_RTC_FORMAT_BIN
|
||||||
|
* @arg @ref LL_RTC_FORMAT_BCD
|
||||||
|
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
|
||||||
|
* contains the alarm configuration parameters.
|
||||||
|
* @note the user should call LL_RTC_ALARM_StructInit() or the structure
|
||||||
|
* of Alarm need to be initialized before Alarm init()
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: ALARM registers are configured
|
||||||
|
* - ERROR: ALARM registers are not configured
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
uint32_t counter_alarm = 0U;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||||
|
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
|
||||||
|
|
||||||
|
if (RTC_Format == LL_RTC_FORMAT_BIN)
|
||||||
|
{
|
||||||
|
assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
|
||||||
|
assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
|
||||||
|
assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
|
||||||
|
assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
|
||||||
|
assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enter Initialization mode */
|
||||||
|
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||||
|
{
|
||||||
|
/* Check the input parameters format */
|
||||||
|
if (RTC_Format != LL_RTC_FORMAT_BIN)
|
||||||
|
{
|
||||||
|
counter_alarm = (uint32_t)(((uint32_t)RTC_AlarmStruct->AlarmTime.Hours * 3600U) + \
|
||||||
|
((uint32_t)RTC_AlarmStruct->AlarmTime.Minutes * 60U) + \
|
||||||
|
((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds));
|
||||||
|
LL_RTC_ALARM_Set(RTCx, counter_alarm);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
counter_alarm = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)) * 3600U) + \
|
||||||
|
((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)) * 60U) + \
|
||||||
|
((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))));
|
||||||
|
LL_RTC_ALARM_Set(RTCx, counter_alarm);
|
||||||
|
}
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
/* Exit Initialization mode */
|
||||||
|
LL_RTC_ExitInitMode(RTCx);
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_RTC_AlarmTypeDef of ALARM field to default value (Time = 00h:00mn:00sec /
|
||||||
|
* Day = 1st day of the month/Mask = all fields are masked).
|
||||||
|
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
|
||||||
|
{
|
||||||
|
/* Alarm Time Settings : Time = 00h:00mn:00sec */
|
||||||
|
RTC_AlarmStruct->AlarmTime.Hours = 0U;
|
||||||
|
RTC_AlarmStruct->AlarmTime.Minutes = 0U;
|
||||||
|
RTC_AlarmStruct->AlarmTime.Seconds = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enters the RTC Initialization mode.
|
||||||
|
* @param RTCx RTC Instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: RTC is in Init mode
|
||||||
|
* - ERROR: RTC is not in Init mode
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
|
||||||
|
{
|
||||||
|
__IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
uint32_t tmp = 0U;
|
||||||
|
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||||
|
|
||||||
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
||||||
|
tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
|
||||||
|
while ((timeout != 0U) && (tmp != 1U))
|
||||||
|
{
|
||||||
|
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
|
||||||
|
{
|
||||||
|
timeout --;
|
||||||
|
}
|
||||||
|
tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
|
||||||
|
if (timeout == 0U)
|
||||||
|
{
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Disable the write protection for RTC registers */
|
||||||
|
LL_RTC_DisableWriteProtection(RTCx);
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Exit the RTC Initialization mode.
|
||||||
|
* @note When the initialization sequence is complete, the calendar restarts
|
||||||
|
* counting after 4 RTCCLK cycles.
|
||||||
|
* @param RTCx RTC Instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: RTC exited from in Init mode
|
||||||
|
* - ERROR: Not applicable
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
|
||||||
|
{
|
||||||
|
__IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
uint32_t tmp = 0U;
|
||||||
|
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||||
|
|
||||||
|
/* Disable initialization mode */
|
||||||
|
LL_RTC_EnableWriteProtection(RTCx);
|
||||||
|
|
||||||
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
||||||
|
tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
|
||||||
|
while ((timeout != 0U) && (tmp != 1U))
|
||||||
|
{
|
||||||
|
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
|
||||||
|
{
|
||||||
|
timeout --;
|
||||||
|
}
|
||||||
|
tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
|
||||||
|
if (timeout == 0U)
|
||||||
|
{
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Time Counter
|
||||||
|
* @param RTCx RTC Instance
|
||||||
|
* @param TimeCounter this value can be from 0 to 0xFFFFFFFF
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: RTC Counter register configured
|
||||||
|
* - ERROR: Not applicable
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter)
|
||||||
|
{
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||||
|
|
||||||
|
/* Enter Initialization mode */
|
||||||
|
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||||
|
{
|
||||||
|
LL_RTC_TIME_Set(RTCx, TimeCounter);
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
/* Exit Initialization mode */
|
||||||
|
LL_RTC_ExitInitMode(RTCx);
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Alarm Counter.
|
||||||
|
* @param RTCx RTC Instance
|
||||||
|
* @param AlarmCounter this value can be from 0 to 0xFFFFFFFF
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: RTC exited from in Init mode
|
||||||
|
* - ERROR: Not applicable
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter)
|
||||||
|
{
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||||
|
|
||||||
|
/* Enter Initialization mode */
|
||||||
|
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
|
||||||
|
{
|
||||||
|
LL_RTC_ALARM_Set(RTCx, AlarmCounter);
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
/* Exit Initialization mode */
|
||||||
|
LL_RTC_ExitInitMode(RTCx);
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Waits until the RTC registers are synchronized with RTC APB clock.
|
||||||
|
* @note The RTC Resynchronization mode is write protected, use the
|
||||||
|
* @ref LL_RTC_DisableWriteProtection before calling this function.
|
||||||
|
* @param RTCx RTC Instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: RTC registers are synchronised
|
||||||
|
* - ERROR: RTC registers are not synchronised
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
|
||||||
|
{
|
||||||
|
__IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
uint32_t tmp = 0U;
|
||||||
|
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
|
||||||
|
|
||||||
|
/* Clear RSF flag */
|
||||||
|
LL_RTC_ClearFlag_RS(RTCx);
|
||||||
|
|
||||||
|
/* Wait the registers to be synchronised */
|
||||||
|
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
|
||||||
|
while ((timeout != 0U) && (tmp != 0U))
|
||||||
|
{
|
||||||
|
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
|
||||||
|
{
|
||||||
|
timeout--;
|
||||||
|
}
|
||||||
|
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
|
||||||
|
if (timeout == 0U)
|
||||||
|
{
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return (status);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* defined(RTC) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,562 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_spi.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief SPI LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_spi.h"
|
||||||
|
#include "stm32f1xx_ll_bus.h"
|
||||||
|
#include "stm32f1xx_ll_rcc.h"
|
||||||
|
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (SPI1) || defined (SPI2) || defined (SPI3)
|
||||||
|
|
||||||
|
/** @addtogroup SPI_LL
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup SPI_LL_Private_Constants SPI Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* SPI registers Masks */
|
||||||
|
#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
|
||||||
|
SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
|
||||||
|
SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
|
||||||
|
SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
|
||||||
|
SPI_CR1_BIDIMODE)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
|
||||||
|
|
||||||
|
#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_MODE_SLAVE))
|
||||||
|
|
||||||
|
#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
|
||||||
|
|
||||||
|
#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_POLARITY_HIGH))
|
||||||
|
|
||||||
|
#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_PHASE_2EDGE))
|
||||||
|
|
||||||
|
#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
|
||||||
|
|
||||||
|
#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
|
||||||
|
|
||||||
|
#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_MSB_FIRST))
|
||||||
|
|
||||||
|
#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
|
||||||
|
|| ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
|
||||||
|
|
||||||
|
#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup SPI_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize the SPI registers to their default reset values.
|
||||||
|
* @param SPIx SPI Instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: SPI registers are de-initialized
|
||||||
|
* - ERROR: SPI registers are not de-initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_INSTANCE(SPIx));
|
||||||
|
|
||||||
|
#if defined(SPI1)
|
||||||
|
if (SPIx == SPI1)
|
||||||
|
{
|
||||||
|
/* Force reset of SPI clock */
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
|
||||||
|
|
||||||
|
/* Release reset of SPI clock */
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
|
||||||
|
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
#endif /* SPI1 */
|
||||||
|
#if defined(SPI2)
|
||||||
|
if (SPIx == SPI2)
|
||||||
|
{
|
||||||
|
/* Force reset of SPI clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
|
||||||
|
|
||||||
|
/* Release reset of SPI clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
|
||||||
|
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
#endif /* SPI2 */
|
||||||
|
#if defined(SPI3)
|
||||||
|
if (SPIx == SPI3)
|
||||||
|
{
|
||||||
|
/* Force reset of SPI clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
|
||||||
|
|
||||||
|
/* Release reset of SPI clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
|
||||||
|
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
#endif /* SPI3 */
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
|
||||||
|
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
||||||
|
* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
|
* @param SPIx SPI Instance
|
||||||
|
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
|
||||||
|
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
|
||||||
|
/* Check the SPI Instance SPIx*/
|
||||||
|
assert_param(IS_SPI_ALL_INSTANCE(SPIx));
|
||||||
|
|
||||||
|
/* Check the SPI parameters from SPI_InitStruct*/
|
||||||
|
assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
|
||||||
|
assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
|
||||||
|
assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
|
||||||
|
assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
|
||||||
|
assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
|
||||||
|
assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
|
||||||
|
assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
|
||||||
|
assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
|
||||||
|
assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
|
||||||
|
|
||||||
|
if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
|
||||||
|
{
|
||||||
|
/*---------------------------- SPIx CR1 Configuration ------------------------
|
||||||
|
* Configure SPIx CR1 with parameters:
|
||||||
|
* - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
|
||||||
|
* - Master/Slave Mode: SPI_CR1_MSTR bit
|
||||||
|
* - DataWidth: SPI_CR1_DFF bit
|
||||||
|
* - ClockPolarity: SPI_CR1_CPOL bit
|
||||||
|
* - ClockPhase: SPI_CR1_CPHA bit
|
||||||
|
* - NSS management: SPI_CR1_SSM bit
|
||||||
|
* - BaudRate prescaler: SPI_CR1_BR[2:0] bits
|
||||||
|
* - BitOrder: SPI_CR1_LSBFIRST bit
|
||||||
|
* - CRCCalculation: SPI_CR1_CRCEN bit
|
||||||
|
*/
|
||||||
|
MODIFY_REG(SPIx->CR1,
|
||||||
|
SPI_CR1_CLEAR_MASK,
|
||||||
|
SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
|
||||||
|
SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
|
||||||
|
SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
|
||||||
|
SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
|
||||||
|
|
||||||
|
/*---------------------------- SPIx CR2 Configuration ------------------------
|
||||||
|
* Configure SPIx CR2 with parameters:
|
||||||
|
* - NSS management: SSOE bit
|
||||||
|
*/
|
||||||
|
MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
|
||||||
|
|
||||||
|
/*---------------------------- SPIx CRCPR Configuration ----------------------
|
||||||
|
* Configure SPIx CRCPR with parameters:
|
||||||
|
* - CRCPoly: CRCPOLY[15:0] bits
|
||||||
|
*/
|
||||||
|
if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
|
||||||
|
{
|
||||||
|
assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
|
||||||
|
LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
|
||||||
|
}
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined (SPI_I2S_SUPPORT)
|
||||||
|
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
|
||||||
|
CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
||||||
|
#endif /* SPI_I2S_SUPPORT */
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_SPI_InitTypeDef field to default value.
|
||||||
|
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
|
||||||
|
{
|
||||||
|
/* Set SPI_InitStruct fields to default values */
|
||||||
|
SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
|
||||||
|
SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
|
||||||
|
SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
|
||||||
|
SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
|
||||||
|
SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
|
||||||
|
SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
|
||||||
|
SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
|
||||||
|
SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
|
||||||
|
SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
|
||||||
|
SPI_InitStruct->CRCPoly = 7U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(SPI_I2S_SUPPORT)
|
||||||
|
/** @addtogroup I2S_LL
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @defgroup I2S_LL_Private_Constants I2S Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* I2S registers Masks */
|
||||||
|
#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
|
||||||
|
SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
|
||||||
|
SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
|
||||||
|
|
||||||
|
#define I2S_I2SPR_CLEAR_MASK 0x0002U
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup I2S_LL_Private_Macros I2S Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
|
||||||
|
|
||||||
|
#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_POLARITY_HIGH))
|
||||||
|
|
||||||
|
#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_STANDARD_MSB) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_STANDARD_LSB) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
|
||||||
|
|
||||||
|
#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
|
||||||
|
|
||||||
|
#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
|
||||||
|
|
||||||
|
#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
|
||||||
|
&& ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
|
||||||
|
|
||||||
|
#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
|
||||||
|
|
||||||
|
#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
|
||||||
|
|| ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup I2S_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2S_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize the SPI/I2S registers to their default reset values.
|
||||||
|
* @param SPIx SPI Instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: SPI registers are de-initialized
|
||||||
|
* - ERROR: SPI registers are not de-initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
return LL_SPI_DeInit(SPIx);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
|
||||||
|
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
||||||
|
* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
|
* @param SPIx SPI Instance
|
||||||
|
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: SPI registers are Initialized
|
||||||
|
* - ERROR: SPI registers are not Initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||||
|
{
|
||||||
|
uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
|
||||||
|
uint32_t tmp = 0U;
|
||||||
|
uint32_t sourceclock = 0U;
|
||||||
|
#if defined(I2S2_I2S3_CLOCK_FEATURE)
|
||||||
|
#else
|
||||||
|
LL_RCC_ClocksTypeDef rcc_clocks;
|
||||||
|
#endif /* I2S2_I2S3_CLOCK_FEATURE */
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
|
||||||
|
/* Check the I2S parameters */
|
||||||
|
assert_param(IS_I2S_ALL_INSTANCE(SPIx));
|
||||||
|
assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
|
||||||
|
assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
|
||||||
|
assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
|
||||||
|
assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
|
||||||
|
assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
|
||||||
|
assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
|
||||||
|
|
||||||
|
if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
|
||||||
|
{
|
||||||
|
/*---------------------------- SPIx I2SCFGR Configuration --------------------
|
||||||
|
* Configure SPIx I2SCFGR with parameters:
|
||||||
|
* - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
|
||||||
|
* - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
|
||||||
|
* - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
|
||||||
|
* - ClockPolarity: SPI_I2SCFGR_CKPOL bit
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Write to SPIx I2SCFGR */
|
||||||
|
MODIFY_REG(SPIx->I2SCFGR,
|
||||||
|
I2S_I2SCFGR_CLEAR_MASK,
|
||||||
|
I2S_InitStruct->Mode | I2S_InitStruct->Standard |
|
||||||
|
I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
|
||||||
|
SPI_I2SCFGR_I2SMOD);
|
||||||
|
|
||||||
|
/*---------------------------- SPIx I2SPR Configuration ----------------------
|
||||||
|
* Configure SPIx I2SPR with parameters:
|
||||||
|
* - MCLKOutput: SPI_I2SPR_MCKOE bit
|
||||||
|
* - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
|
||||||
|
* else, default values are used: i2sodd = 0U, i2sdiv = 2U.
|
||||||
|
*/
|
||||||
|
if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
|
||||||
|
{
|
||||||
|
/* Check the frame length (For the Prescaler computing)
|
||||||
|
* Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
|
||||||
|
*/
|
||||||
|
if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
|
||||||
|
{
|
||||||
|
/* Packet length is 32 bits */
|
||||||
|
packetlength = 2U;
|
||||||
|
}
|
||||||
|
#if defined(I2S2_I2S3_CLOCK_FEATURE)
|
||||||
|
/* If an external I2S clock has to be used, the specific define should be set
|
||||||
|
in the project configuration or in the stm32f1xx_ll_rcc.h file */
|
||||||
|
if(SPIx == SPI2)
|
||||||
|
{
|
||||||
|
/* Get the I2S source clock value */
|
||||||
|
sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
|
||||||
|
}
|
||||||
|
else /* SPI3 */
|
||||||
|
{
|
||||||
|
/* Get the I2S source clock value */
|
||||||
|
sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S3_CLKSOURCE);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
/* I2S Clock source is System clock: Get System Clock frequency */
|
||||||
|
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
|
||||||
|
|
||||||
|
/* Get the source clock value: based on System Clock value */
|
||||||
|
sourceclock = rcc_clocks.SYSCLK_Frequency;
|
||||||
|
#endif /* I2S2_I2S3_CLOCK_FEATURE */
|
||||||
|
/* Compute the Real divider depending on the MCLK output state with a floating point */
|
||||||
|
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
|
||||||
|
{
|
||||||
|
/* MCLK output is enabled */
|
||||||
|
tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* MCLK output is disabled */
|
||||||
|
tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Remove the floating point */
|
||||||
|
tmp = tmp / 10U;
|
||||||
|
|
||||||
|
/* Check the parity of the divider */
|
||||||
|
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
|
||||||
|
|
||||||
|
/* Compute the i2sdiv prescaler */
|
||||||
|
i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
|
||||||
|
|
||||||
|
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
|
||||||
|
i2sodd = (uint16_t)(i2sodd << 8U);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
||||||
|
if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
|
||||||
|
{
|
||||||
|
/* Set the default values */
|
||||||
|
i2sdiv = 2U;
|
||||||
|
i2sodd = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Write to SPIx I2SPR register the computed value */
|
||||||
|
WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
|
||||||
|
|
||||||
|
status = SUCCESS;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_I2S_InitTypeDef field to default value.
|
||||||
|
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||||
|
{
|
||||||
|
/*--------------- Reset I2S init structure parameters values -----------------*/
|
||||||
|
I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
|
||||||
|
I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
|
||||||
|
I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
|
||||||
|
I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
|
||||||
|
I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
|
||||||
|
I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set linear and parity prescaler.
|
||||||
|
* @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
|
||||||
|
* Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
|
||||||
|
* @param SPIx SPI Instance
|
||||||
|
* @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
|
||||||
|
* @param PrescalerParity This parameter can be one of the following values:
|
||||||
|
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
|
||||||
|
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
|
||||||
|
{
|
||||||
|
/* Check the I2S parameters */
|
||||||
|
assert_param(IS_I2S_ALL_INSTANCE(SPIx));
|
||||||
|
assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
|
||||||
|
assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
|
||||||
|
|
||||||
|
/* Write to SPIx I2SPR */
|
||||||
|
MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* SPI_I2S_SUPPORT */
|
||||||
|
|
||||||
|
#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
1216
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c
Normal file
1216
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,451 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f1xx_ll_usart.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V1.1.1
|
||||||
|
* @date 12-May-2017
|
||||||
|
* @brief USART LL module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f1xx_ll_usart.h"
|
||||||
|
#include "stm32f1xx_ll_rcc.h"
|
||||||
|
#include "stm32f1xx_ll_bus.h"
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
#include "stm32_assert.h"
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32F1xx_LL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
|
||||||
|
|
||||||
|
/** @addtogroup USART_LL
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/** @addtogroup USART_LL_Private_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @addtogroup USART_LL_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
|
||||||
|
* divided by the smallest oversampling used on the USART (i.e. 8) */
|
||||||
|
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
|
||||||
|
|
||||||
|
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|
||||||
|
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|
||||||
|
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|
||||||
|
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
|
||||||
|
|
||||||
|
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
|
||||||
|
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|
||||||
|
|| ((__VALUE__) == LL_USART_PARITY_ODD))
|
||||||
|
|
||||||
|
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|
||||||
|
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
|
||||||
|
|
||||||
|
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
|
||||||
|
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
|
||||||
|
|
||||||
|
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
|
||||||
|
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
|
||||||
|
|
||||||
|
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
|
||||||
|
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
|
||||||
|
|
||||||
|
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
|
||||||
|
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
|
||||||
|
|
||||||
|
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
|
||||||
|
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
|
||||||
|
|
||||||
|
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
|
||||||
|
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|
||||||
|
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|
||||||
|
|| ((__VALUE__) == LL_USART_STOPBITS_2))
|
||||||
|
|
||||||
|
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|
||||||
|
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|
||||||
|
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|
||||||
|
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup USART_LL_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USART_LL_EF_Init
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief De-initialize USART registers (Registers restored to their default values).
|
||||||
|
* @param USARTx USART Instance
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: USART registers are de-initialized
|
||||||
|
* - ERROR: USART registers are not de-initialized
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_UART_INSTANCE(USARTx));
|
||||||
|
|
||||||
|
if (USARTx == USART1)
|
||||||
|
{
|
||||||
|
/* Force reset of USART clock */
|
||||||
|
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
|
||||||
|
|
||||||
|
/* Release reset of USART clock */
|
||||||
|
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
|
||||||
|
}
|
||||||
|
else if (USARTx == USART2)
|
||||||
|
{
|
||||||
|
/* Force reset of USART clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
|
||||||
|
|
||||||
|
/* Release reset of USART clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
|
||||||
|
}
|
||||||
|
#if defined(USART3)
|
||||||
|
else if (USARTx == USART3)
|
||||||
|
{
|
||||||
|
/* Force reset of USART clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
|
||||||
|
|
||||||
|
/* Release reset of USART clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
|
||||||
|
}
|
||||||
|
#endif /* USART3 */
|
||||||
|
#if defined(UART4)
|
||||||
|
else if (USARTx == UART4)
|
||||||
|
{
|
||||||
|
/* Force reset of UART clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
|
||||||
|
|
||||||
|
/* Release reset of UART clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
|
||||||
|
}
|
||||||
|
#endif /* UART4 */
|
||||||
|
#if defined(UART5)
|
||||||
|
else if (USARTx == UART5)
|
||||||
|
{
|
||||||
|
/* Force reset of UART clock */
|
||||||
|
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
|
||||||
|
|
||||||
|
/* Release reset of UART clock */
|
||||||
|
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
|
||||||
|
}
|
||||||
|
#endif /* UART5 */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (status);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize USART registers according to the specified
|
||||||
|
* parameters in USART_InitStruct.
|
||||||
|
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
|
||||||
|
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
|
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
|
||||||
|
* @param USARTx USART Instance
|
||||||
|
* @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
|
||||||
|
* that contains the configuration information for the specified USART peripheral.
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
|
||||||
|
* - ERROR: Problem occurred during USART Registers initialization
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = ERROR;
|
||||||
|
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
|
||||||
|
LL_RCC_ClocksTypeDef rcc_clocks;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_UART_INSTANCE(USARTx));
|
||||||
|
assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
|
||||||
|
assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
|
||||||
|
assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
|
||||||
|
assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
|
||||||
|
assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
|
||||||
|
assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
|
||||||
|
#if defined(USART_CR1_OVER8)
|
||||||
|
assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
|
||||||
|
#endif /* USART_OverSampling_Feature */
|
||||||
|
|
||||||
|
/* USART needs to be in disabled state, in order to be able to configure some bits in
|
||||||
|
CRx registers */
|
||||||
|
if (LL_USART_IsEnabled(USARTx) == 0U)
|
||||||
|
{
|
||||||
|
/*---------------------------- USART CR1 Configuration -----------------------
|
||||||
|
* Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
|
||||||
|
* - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
|
||||||
|
* - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
|
||||||
|
* - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
|
||||||
|
* - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
|
||||||
|
*/
|
||||||
|
#if defined(USART_CR1_OVER8)
|
||||||
|
MODIFY_REG(USARTx->CR1,
|
||||||
|
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
|
||||||
|
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
||||||
|
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
|
||||||
|
USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
|
||||||
|
#else
|
||||||
|
MODIFY_REG(USARTx->CR1,
|
||||||
|
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
|
||||||
|
USART_CR1_TE | USART_CR1_RE),
|
||||||
|
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
|
||||||
|
USART_InitStruct->TransferDirection));
|
||||||
|
#endif /* USART_OverSampling_Feature */
|
||||||
|
|
||||||
|
/*---------------------------- USART CR2 Configuration -----------------------
|
||||||
|
* Configure USARTx CR2 (Stop bits) with parameters:
|
||||||
|
* - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
|
||||||
|
* - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
|
||||||
|
*/
|
||||||
|
LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
|
||||||
|
|
||||||
|
/*---------------------------- USART CR3 Configuration -----------------------
|
||||||
|
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
|
||||||
|
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
|
||||||
|
*/
|
||||||
|
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
|
||||||
|
|
||||||
|
/*---------------------------- USART BRR Configuration -----------------------
|
||||||
|
* Retrieve Clock frequency used for USART Peripheral
|
||||||
|
*/
|
||||||
|
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
|
||||||
|
if (USARTx == USART1)
|
||||||
|
{
|
||||||
|
periphclk = rcc_clocks.PCLK2_Frequency;
|
||||||
|
}
|
||||||
|
else if (USARTx == USART2)
|
||||||
|
{
|
||||||
|
periphclk = rcc_clocks.PCLK1_Frequency;
|
||||||
|
}
|
||||||
|
#if defined(USART3)
|
||||||
|
else if (USARTx == USART3)
|
||||||
|
{
|
||||||
|
periphclk = rcc_clocks.PCLK1_Frequency;
|
||||||
|
}
|
||||||
|
#endif /* USART3 */
|
||||||
|
#if defined(UART4)
|
||||||
|
else if (USARTx == UART4)
|
||||||
|
{
|
||||||
|
periphclk = rcc_clocks.PCLK1_Frequency;
|
||||||
|
}
|
||||||
|
#endif /* UART4 */
|
||||||
|
#if defined(UART5)
|
||||||
|
else if (USARTx == UART5)
|
||||||
|
{
|
||||||
|
periphclk = rcc_clocks.PCLK1_Frequency;
|
||||||
|
}
|
||||||
|
#endif /* UART5 */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Nothing to do, as error code is already assigned to ERROR value */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configure the USART Baud Rate :
|
||||||
|
- valid baud rate value (different from 0) is required
|
||||||
|
- Peripheral clock as returned by RCC service, should be valid (different from 0).
|
||||||
|
*/
|
||||||
|
if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
|
||||||
|
&& (USART_InitStruct->BaudRate != 0U))
|
||||||
|
{
|
||||||
|
status = SUCCESS;
|
||||||
|
#if defined(USART_CR1_OVER8)
|
||||||
|
LL_USART_SetBaudRate(USARTx,
|
||||||
|
periphclk,
|
||||||
|
USART_InitStruct->OverSampling,
|
||||||
|
USART_InitStruct->BaudRate);
|
||||||
|
#else
|
||||||
|
LL_USART_SetBaudRate(USARTx,
|
||||||
|
periphclk,
|
||||||
|
USART_InitStruct->BaudRate);
|
||||||
|
#endif /* USART_OverSampling_Feature */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Endif (=> USART not in Disabled state => return ERROR) */
|
||||||
|
|
||||||
|
return (status);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
|
||||||
|
* @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
|
||||||
|
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
|
||||||
|
{
|
||||||
|
/* Set USART_InitStruct fields to default values */
|
||||||
|
USART_InitStruct->BaudRate = 9600U;
|
||||||
|
USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
|
||||||
|
USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
|
||||||
|
USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
|
||||||
|
USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
|
||||||
|
USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
|
||||||
|
#if defined(USART_CR1_OVER8)
|
||||||
|
USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
|
||||||
|
#endif /* USART_OverSampling_Feature */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize USART Clock related settings according to the
|
||||||
|
* specified parameters in the USART_ClockInitStruct.
|
||||||
|
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
|
||||||
|
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
|
* @param USARTx USART Instance
|
||||||
|
* @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||||
|
* that contains the Clock configuration information for the specified USART peripheral.
|
||||||
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
|
||||||
|
* - ERROR: Problem occurred during USART Registers initialization
|
||||||
|
*/
|
||||||
|
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||||
|
{
|
||||||
|
ErrorStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* Check USART Instance and Clock signal output parameters */
|
||||||
|
assert_param(IS_UART_INSTANCE(USARTx));
|
||||||
|
assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
|
||||||
|
|
||||||
|
/* USART needs to be in disabled state, in order to be able to configure some bits in
|
||||||
|
CRx registers */
|
||||||
|
if (LL_USART_IsEnabled(USARTx) == 0U)
|
||||||
|
{
|
||||||
|
/*---------------------------- USART CR2 Configuration -----------------------*/
|
||||||
|
/* If Clock signal has to be output */
|
||||||
|
if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
|
||||||
|
{
|
||||||
|
/* Deactivate Clock signal delivery :
|
||||||
|
* - Disable Clock Output: USART_CR2_CLKEN cleared
|
||||||
|
*/
|
||||||
|
LL_USART_DisableSCLKOutput(USARTx);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Ensure USART instance is USART capable */
|
||||||
|
assert_param(IS_USART_INSTANCE(USARTx));
|
||||||
|
|
||||||
|
/* Check clock related parameters */
|
||||||
|
assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
|
||||||
|
assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
|
||||||
|
assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
|
||||||
|
|
||||||
|
/*---------------------------- USART CR2 Configuration -----------------------
|
||||||
|
* Configure USARTx CR2 (Clock signal related bits) with parameters:
|
||||||
|
* - Enable Clock Output: USART_CR2_CLKEN set
|
||||||
|
* - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
|
||||||
|
* - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
|
||||||
|
* - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
|
||||||
|
*/
|
||||||
|
MODIFY_REG(USARTx->CR2,
|
||||||
|
USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
|
||||||
|
USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
|
||||||
|
USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Else (USART not in Disabled state => return ERROR */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (status);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
|
||||||
|
* @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||||
|
* whose fields will be set to default values.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||||
|
{
|
||||||
|
/* Set LL_USART_ClockInitStruct fields with default values */
|
||||||
|
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
|
||||||
|
USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
|
||||||
|
USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
|
||||||
|
USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* USE_FULL_LL_DRIVER */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
2338
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c
Normal file
2338
bsp/stm32f103rc/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c
Normal file
File diff suppressed because it is too large
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Reference in New Issue
Block a user