demos/printf_demo/main.elf: file format elf32-littlearm Disassembly of section .text: 00000000 : 0: 00 50 00 20 e5 59 00 00 29 5a 00 00 29 5a 00 00 .P. .Y..)Z..)Z.. 10: 29 5a 00 00 29 5a 00 00 29 5a 00 00 00 00 00 00 )Z..)Z..)Z...... ... 2c: 29 5a 00 00 29 5a 00 00 00 00 00 00 29 5a 00 00 )Z..)Z......)Z.. 3c: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. 4c: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. 5c: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. 6c: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. 7c: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. 8c: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. 9c: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. ac: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. bc: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. cc: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. dc: 29 5a 00 00 29 5a 00 00 29 5a 00 00 29 5a 00 00 )Z..)Z..)Z..)Z.. ... 108: 5f f8 08 f1 _... 0000010c <__get_PSP>: * Return the actual process stack pointer */ uint32_t __get_PSP(void) __attribute__( ( naked ) ); uint32_t __get_PSP(void) { uint32_t result=0; 10c: 2400 movs r4, #0 __ASM volatile ("MRS %0, psp\n\t" 10e: f3ef 8309 mrs r3, PSP 112: 4618 mov r0, r3 114: 4770 bx lr 116: 461c mov r4, r3 "MOV r0, %0 \n\t" "BX lr \n\t" : "=r" (result) ); return(result); 118: 4623 mov r3, r4 } 11a: 4618 mov r0, r3 0000011c <__set_PSP>: * Assign the value ProcessStackPointer to the MSP * (process stack pointer) Cortex processor register */ void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); void __set_PSP(uint32_t topOfProcStack) { 11c: 4603 mov r3, r0 __ASM volatile ("MSR psp, %0\n\t" 11e: f383 8809 msr PSP, r3 122: 4770 bx lr "BX lr \n\t" : : "r" (topOfProcStack) ); } 124: bf00 nop 00000126 <__get_MSP>: * Cortex processor register */ uint32_t __get_MSP(void) __attribute__( ( naked ) ); uint32_t __get_MSP(void) { uint32_t result=0; 126: 2400 movs r4, #0 __ASM volatile ("MRS %0, msp\n\t" 128: f3ef 8308 mrs r3, MSP 12c: 4618 mov r0, r3 12e: 4770 bx lr 130: 461c mov r4, r3 "MOV r0, %0 \n\t" "BX lr \n\t" : "=r" (result) ); return(result); 132: 4623 mov r3, r4 } 134: 4618 mov r0, r3 00000136 <__set_MSP>: * Assign the value mainStackPointer to the MSP * (main stack pointer) Cortex processor register */ void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); void __set_MSP(uint32_t topOfMainStack) { 136: 4603 mov r3, r0 __ASM volatile ("MSR msp, %0\n\t" 138: f383 8808 msr MSP, r3 13c: 4770 bx lr "BX lr \n\t" : : "r" (topOfMainStack) ); } 13e: bf00 nop 00000140 <__get_BASEPRI>: * @return BasePriority * * Return the content of the base priority register */ uint32_t __get_BASEPRI(void) { 140: b480 push {r7} 142: b083 sub sp, #12 144: af00 add r7, sp, #0 uint32_t result=0; 146: 2300 movs r3, #0 148: 607b str r3, [r7, #4] __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); 14a: f3ef 8312 mrs r3, BASEPRI_MAX 14e: 607b str r3, [r7, #4] return(result); 150: 687b ldr r3, [r7, #4] } 152: 4618 mov r0, r3 154: 370c adds r7, #12 156: 46bd mov sp, r7 158: bc80 pop {r7} 15a: 4770 bx lr 0000015c <__set_BASEPRI>: * @param basePri BasePriority * * Set the base priority register */ void __set_BASEPRI(uint32_t value) { 15c: b480 push {r7} 15e: b083 sub sp, #12 160: af00 add r7, sp, #0 162: 6078 str r0, [r7, #4] __ASM volatile ("MSR basepri, %0" : : "r" (value) ); 164: 687b ldr r3, [r7, #4] 166: f383 8811 msr BASEPRI, r3 } 16a: bf00 nop 16c: 370c adds r7, #12 16e: 46bd mov sp, r7 170: bc80 pop {r7} 172: 4770 bx lr 00000174 <__get_PRIMASK>: * @return PriMask * * Return state of the priority mask bit from the priority mask register */ uint32_t __get_PRIMASK(void) { 174: b480 push {r7} 176: b083 sub sp, #12 178: af00 add r7, sp, #0 uint32_t result=0; 17a: 2300 movs r3, #0 17c: 607b str r3, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) ); 17e: f3ef 8310 mrs r3, PRIMASK 182: 607b str r3, [r7, #4] return(result); 184: 687b ldr r3, [r7, #4] } 186: 4618 mov r0, r3 188: 370c adds r7, #12 18a: 46bd mov sp, r7 18c: bc80 pop {r7} 18e: 4770 bx lr 00000190 <__set_PRIMASK>: * @param priMask PriMask * * Set the priority mask bit in the priority mask register */ void __set_PRIMASK(uint32_t priMask) { 190: b480 push {r7} 192: b083 sub sp, #12 194: af00 add r7, sp, #0 196: 6078 str r0, [r7, #4] __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); 198: 687b ldr r3, [r7, #4] 19a: f383 8810 msr PRIMASK, r3 } 19e: bf00 nop 1a0: 370c adds r7, #12 1a2: 46bd mov sp, r7 1a4: bc80 pop {r7} 1a6: 4770 bx lr 000001a8 <__get_FAULTMASK>: * @return FaultMask * * Return the content of the fault mask register */ uint32_t __get_FAULTMASK(void) { 1a8: b480 push {r7} 1aa: b083 sub sp, #12 1ac: af00 add r7, sp, #0 uint32_t result=0; 1ae: 2300 movs r3, #0 1b0: 607b str r3, [r7, #4] __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 1b2: f3ef 8313 mrs r3, FAULTMASK 1b6: 607b str r3, [r7, #4] return(result); 1b8: 687b ldr r3, [r7, #4] } 1ba: 4618 mov r0, r3 1bc: 370c adds r7, #12 1be: 46bd mov sp, r7 1c0: bc80 pop {r7} 1c2: 4770 bx lr 000001c4 <__set_FAULTMASK>: * @param faultMask faultMask value * * Set the fault mask register */ void __set_FAULTMASK(uint32_t faultMask) { 1c4: b480 push {r7} 1c6: b083 sub sp, #12 1c8: af00 add r7, sp, #0 1ca: 6078 str r0, [r7, #4] __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); 1cc: 687b ldr r3, [r7, #4] 1ce: f383 8813 msr FAULTMASK, r3 } 1d2: bf00 nop 1d4: 370c adds r7, #12 1d6: 46bd mov sp, r7 1d8: bc80 pop {r7} 1da: 4770 bx lr 000001dc <__get_CONTROL>: * @return Control value * * Return the content of the control register */ uint32_t __get_CONTROL(void) { 1dc: b480 push {r7} 1de: b083 sub sp, #12 1e0: af00 add r7, sp, #0 uint32_t result=0; 1e2: 2300 movs r3, #0 1e4: 607b str r3, [r7, #4] __ASM volatile ("MRS %0, control" : "=r" (result) ); 1e6: f3ef 8314 mrs r3, CONTROL 1ea: 607b str r3, [r7, #4] return(result); 1ec: 687b ldr r3, [r7, #4] } 1ee: 4618 mov r0, r3 1f0: 370c adds r7, #12 1f2: 46bd mov sp, r7 1f4: bc80 pop {r7} 1f6: 4770 bx lr 000001f8 <__set_CONTROL>: * @param control Control value * * Set the control register */ void __set_CONTROL(uint32_t control) { 1f8: b480 push {r7} 1fa: b083 sub sp, #12 1fc: af00 add r7, sp, #0 1fe: 6078 str r0, [r7, #4] __ASM volatile ("MSR control, %0" : : "r" (control) ); 200: 687b ldr r3, [r7, #4] 202: f383 8814 msr CONTROL, r3 } 206: bf00 nop 208: 370c adds r7, #12 20a: 46bd mov sp, r7 20c: bc80 pop {r7} 20e: 4770 bx lr 00000210 <__REV>: * @return reversed value * * Reverse byte order in integer value */ uint32_t __REV(uint32_t value) { 210: b480 push {r7} 212: b085 sub sp, #20 214: af00 add r7, sp, #0 216: 6078 str r0, [r7, #4] uint32_t result=0; 218: 2300 movs r3, #0 21a: 60fb str r3, [r7, #12] __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); 21c: 687b ldr r3, [r7, #4] 21e: ba1b rev r3, r3 220: 60fb str r3, [r7, #12] return(result); 222: 68fb ldr r3, [r7, #12] } 224: 4618 mov r0, r3 226: 3714 adds r7, #20 228: 46bd mov sp, r7 22a: bc80 pop {r7} 22c: 4770 bx lr 0000022e <__REV16>: * @return reversed value * * Reverse byte order in unsigned short value */ uint32_t __REV16(uint16_t value) { 22e: b480 push {r7} 230: b085 sub sp, #20 232: af00 add r7, sp, #0 234: 4603 mov r3, r0 236: 80fb strh r3, [r7, #6] uint32_t result=0; 238: 2300 movs r3, #0 23a: 60fb str r3, [r7, #12] __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); 23c: 88fb ldrh r3, [r7, #6] 23e: ba5b rev16 r3, r3 240: 60fb str r3, [r7, #12] return(result); 242: 68fb ldr r3, [r7, #12] } 244: 4618 mov r0, r3 246: 3714 adds r7, #20 248: 46bd mov sp, r7 24a: bc80 pop {r7} 24c: 4770 bx lr 0000024e <__REVSH>: * @return reversed value * * Reverse byte order in signed short value with sign extension to integer */ int32_t __REVSH(int16_t value) { 24e: b480 push {r7} 250: b085 sub sp, #20 252: af00 add r7, sp, #0 254: 4603 mov r3, r0 256: 80fb strh r3, [r7, #6] uint32_t result=0; 258: 2300 movs r3, #0 25a: 60fb str r3, [r7, #12] __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); 25c: 88fb ldrh r3, [r7, #6] 25e: badb revsh r3, r3 260: 60fb str r3, [r7, #12] return(result); 262: 68fb ldr r3, [r7, #12] } 264: 4618 mov r0, r3 266: 3714 adds r7, #20 268: 46bd mov sp, r7 26a: bc80 pop {r7} 26c: 4770 bx lr 0000026e <__RBIT>: * @return reversed value * * Reverse bit order of value */ uint32_t __RBIT(uint32_t value) { 26e: b480 push {r7} 270: b085 sub sp, #20 272: af00 add r7, sp, #0 274: 6078 str r0, [r7, #4] uint32_t result=0; 276: 2300 movs r3, #0 278: 60fb str r3, [r7, #12] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 27a: 687b ldr r3, [r7, #4] 27c: fa93 f3a3 rbit r3, r3 280: 60fb str r3, [r7, #12] return(result); 282: 68fb ldr r3, [r7, #12] } 284: 4618 mov r0, r3 286: 3714 adds r7, #20 288: 46bd mov sp, r7 28a: bc80 pop {r7} 28c: 4770 bx lr 0000028e <__LDREXB>: * @return value of (*address) * * Exclusive LDR command for 8 bit value */ uint8_t __LDREXB(uint8_t *addr) { 28e: b480 push {r7} 290: b085 sub sp, #20 292: af00 add r7, sp, #0 294: 6078 str r0, [r7, #4] uint8_t result=0; 296: 2300 movs r3, #0 298: 73fb strb r3, [r7, #15] __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); 29a: 687b ldr r3, [r7, #4] 29c: e8d3 3f4f ldrexb r3, [r3] 2a0: 73fb strb r3, [r7, #15] return(result); 2a2: 7bfb ldrb r3, [r7, #15] } 2a4: 4618 mov r0, r3 2a6: 3714 adds r7, #20 2a8: 46bd mov sp, r7 2aa: bc80 pop {r7} 2ac: 4770 bx lr 000002ae <__LDREXH>: * @return value of (*address) * * Exclusive LDR command for 16 bit values */ uint16_t __LDREXH(uint16_t *addr) { 2ae: b480 push {r7} 2b0: b085 sub sp, #20 2b2: af00 add r7, sp, #0 2b4: 6078 str r0, [r7, #4] uint16_t result=0; 2b6: 2300 movs r3, #0 2b8: 81fb strh r3, [r7, #14] __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); 2ba: 687b ldr r3, [r7, #4] 2bc: e8d3 3f5f ldrexh r3, [r3] 2c0: 81fb strh r3, [r7, #14] return(result); 2c2: 89fb ldrh r3, [r7, #14] } 2c4: 4618 mov r0, r3 2c6: 3714 adds r7, #20 2c8: 46bd mov sp, r7 2ca: bc80 pop {r7} 2cc: 4770 bx lr 000002ce <__LDREXW>: * @return value of (*address) * * Exclusive LDR command for 32 bit values */ uint32_t __LDREXW(uint32_t *addr) { 2ce: b480 push {r7} 2d0: b085 sub sp, #20 2d2: af00 add r7, sp, #0 2d4: 6078 str r0, [r7, #4] uint32_t result=0; 2d6: 2300 movs r3, #0 2d8: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); 2da: 687b ldr r3, [r7, #4] 2dc: e853 3f00 ldrex r3, [r3] 2e0: 60fb str r3, [r7, #12] return(result); 2e2: 68fb ldr r3, [r7, #12] } 2e4: 4618 mov r0, r3 2e6: 3714 adds r7, #20 2e8: 46bd mov sp, r7 2ea: bc80 pop {r7} 2ec: 4770 bx lr 000002ee <__STREXB>: * @return successful / failed * * Exclusive STR command for 8 bit values */ uint32_t __STREXB(uint8_t value, uint8_t *addr) { 2ee: b480 push {r7} 2f0: b085 sub sp, #20 2f2: af00 add r7, sp, #0 2f4: 4603 mov r3, r0 2f6: 6039 str r1, [r7, #0] 2f8: 71fb strb r3, [r7, #7] uint32_t result=0; 2fa: 2300 movs r3, #0 2fc: 60fb str r3, [r7, #12] __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); 2fe: 683a ldr r2, [r7, #0] 300: 79f9 ldrb r1, [r7, #7] 302: e8c2 1f43 strexb r3, r1, [r2] 306: 60fb str r3, [r7, #12] return(result); 308: 68fb ldr r3, [r7, #12] } 30a: 4618 mov r0, r3 30c: 3714 adds r7, #20 30e: 46bd mov sp, r7 310: bc80 pop {r7} 312: 4770 bx lr 00000314 <__STREXH>: * @return successful / failed * * Exclusive STR command for 16 bit values */ uint32_t __STREXH(uint16_t value, uint16_t *addr) { 314: b480 push {r7} 316: b085 sub sp, #20 318: af00 add r7, sp, #0 31a: 4603 mov r3, r0 31c: 6039 str r1, [r7, #0] 31e: 80fb strh r3, [r7, #6] uint32_t result=0; 320: 2300 movs r3, #0 322: 60fb str r3, [r7, #12] __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); 324: 683a ldr r2, [r7, #0] 326: 88f9 ldrh r1, [r7, #6] 328: e8c2 1f53 strexh r3, r1, [r2] 32c: 60fb str r3, [r7, #12] return(result); 32e: 68fb ldr r3, [r7, #12] } 330: 4618 mov r0, r3 332: 3714 adds r7, #20 334: 46bd mov sp, r7 336: bc80 pop {r7} 338: 4770 bx lr 0000033a <__STREXW>: * @return successful / failed * * Exclusive STR command for 32 bit values */ uint32_t __STREXW(uint32_t value, uint32_t *addr) { 33a: b480 push {r7} 33c: b085 sub sp, #20 33e: af00 add r7, sp, #0 340: 6078 str r0, [r7, #4] 342: 6039 str r1, [r7, #0] uint32_t result=0; 344: 2300 movs r3, #0 346: 60fb str r3, [r7, #12] __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); 348: 683b ldr r3, [r7, #0] 34a: 687a ldr r2, [r7, #4] 34c: e843 2300 strex r3, r2, [r3] 350: 60fb str r3, [r7, #12] return(result); 352: 68fb ldr r3, [r7, #12] } 354: 4618 mov r0, r3 356: 3714 adds r7, #20 358: 46bd mov sp, r7 35a: bc80 pop {r7} 35c: 4770 bx lr ... 00000360 : * @note This function should be used only after reset. * @param None * @retval None */ void SystemInit (void) { 360: b580 push {r7, lr} 362: af00 add r7, sp, #0 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; 364: 4b15 ldr r3, [pc, #84] ; (3bc ) 366: 681b ldr r3, [r3, #0] 368: 4a14 ldr r2, [pc, #80] ; (3bc ) 36a: f043 0301 orr.w r3, r3, #1 36e: 6013 str r3, [r2, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; 370: 4b12 ldr r3, [pc, #72] ; (3bc ) 372: 685a ldr r2, [r3, #4] 374: 4911 ldr r1, [pc, #68] ; (3bc ) 376: 4b12 ldr r3, [pc, #72] ; (3c0 ) 378: 4013 ands r3, r2 37a: 604b str r3, [r1, #4] #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; 37c: 4b0f ldr r3, [pc, #60] ; (3bc ) 37e: 681b ldr r3, [r3, #0] 380: 4a0e ldr r2, [pc, #56] ; (3bc ) 382: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 386: f423 3380 bic.w r3, r3, #65536 ; 0x10000 38a: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; 38c: 4b0b ldr r3, [pc, #44] ; (3bc ) 38e: 681b ldr r3, [r3, #0] 390: 4a0a ldr r2, [pc, #40] ; (3bc ) 392: f423 2380 bic.w r3, r3, #262144 ; 0x40000 396: 6013 str r3, [r2, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; 398: 4b08 ldr r3, [pc, #32] ; (3bc ) 39a: 685b ldr r3, [r3, #4] 39c: 4a07 ldr r2, [pc, #28] ; (3bc ) 39e: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 3a2: 6053 str r3, [r2, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; 3a4: 4b05 ldr r3, [pc, #20] ; (3bc ) 3a6: f44f 021f mov.w r2, #10420224 ; 0x9f0000 3aa: 609a str r2, [r3, #8] #endif /* DATA_IN_ExtSRAM */ #endif /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ /* Configure the Flash Latency cycles and enable prefetch buffer */ SetSysClock(); 3ac: f000 f87e bl 4ac #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 3b0: 4b04 ldr r3, [pc, #16] ; (3c4 ) 3b2: f04f 6200 mov.w r2, #134217728 ; 0x8000000 3b6: 609a str r2, [r3, #8] #endif } 3b8: bf00 nop 3ba: bd80 pop {r7, pc} 3bc: 40021000 .word 0x40021000 3c0: f8ff0000 .word 0xf8ff0000 3c4: e000ed00 .word 0xe000ed00 000003c8 : * value for HSE crystal. * @param None * @retval None */ void SystemCoreClockUpdate (void) { 3c8: b480 push {r7} 3ca: b085 sub sp, #20 3cc: af00 add r7, sp, #0 uint32_t tmp = 0, pllmull = 0, pllsource = 0; 3ce: 2300 movs r3, #0 3d0: 60fb str r3, [r7, #12] 3d2: 2300 movs r3, #0 3d4: 60bb str r3, [r7, #8] 3d6: 2300 movs r3, #0 3d8: 607b str r3, [r7, #4] #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) uint32_t prediv1factor = 0; #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; 3da: 4b2f ldr r3, [pc, #188] ; (498 ) 3dc: 685b ldr r3, [r3, #4] 3de: f003 030c and.w r3, r3, #12 3e2: 60fb str r3, [r7, #12] switch (tmp) 3e4: 68fb ldr r3, [r7, #12] 3e6: 2b08 cmp r3, #8 3e8: d011 beq.n 40e 3ea: 68fb ldr r3, [r7, #12] 3ec: 2b08 cmp r3, #8 3ee: d83a bhi.n 466 3f0: 68fb ldr r3, [r7, #12] 3f2: 2b00 cmp r3, #0 3f4: d003 beq.n 3fe 3f6: 68fb ldr r3, [r7, #12] 3f8: 2b04 cmp r3, #4 3fa: d004 beq.n 406 3fc: e033 b.n 466 { case 0x00: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; 3fe: 4b27 ldr r3, [pc, #156] ; (49c ) 400: 4a27 ldr r2, [pc, #156] ; (4a0 ) 402: 601a str r2, [r3, #0] break; 404: e033 b.n 46e case 0x04: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; 406: 4b25 ldr r3, [pc, #148] ; (49c ) 408: 4a25 ldr r2, [pc, #148] ; (4a0 ) 40a: 601a str r2, [r3, #0] break; 40c: e02f b.n 46e case 0x08: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 40e: 4b22 ldr r3, [pc, #136] ; (498 ) 410: 685b ldr r3, [r3, #4] 412: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 416: 60bb str r3, [r7, #8] pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 418: 4b1f ldr r3, [pc, #124] ; (498 ) 41a: 685b ldr r3, [r3, #4] 41c: f403 3380 and.w r3, r3, #65536 ; 0x10000 420: 607b str r3, [r7, #4] #ifndef STM32F10X_CL pllmull = ( pllmull >> 18) + 2; 422: 68bb ldr r3, [r7, #8] 424: 0c9b lsrs r3, r3, #18 426: 3302 adds r3, #2 428: 60bb str r3, [r7, #8] if (pllsource == 0x00) 42a: 687b ldr r3, [r7, #4] 42c: 2b00 cmp r3, #0 42e: d106 bne.n 43e { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 430: 68bb ldr r3, [r7, #8] 432: 4a1c ldr r2, [pc, #112] ; (4a4 ) 434: fb02 f303 mul.w r3, r2, r3 438: 4a18 ldr r2, [pc, #96] ; (49c ) 43a: 6013 str r3, [r2, #0] pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 43c: e017 b.n 46e if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) 43e: 4b16 ldr r3, [pc, #88] ; (498 ) 440: 685b ldr r3, [r3, #4] 442: f403 3300 and.w r3, r3, #131072 ; 0x20000 446: 2b00 cmp r3, #0 448: d006 beq.n 458 SystemCoreClock = (HSE_VALUE >> 1) * pllmull; 44a: 68bb ldr r3, [r7, #8] 44c: 4a15 ldr r2, [pc, #84] ; (4a4 ) 44e: fb02 f303 mul.w r3, r2, r3 452: 4a12 ldr r2, [pc, #72] ; (49c ) 454: 6013 str r3, [r2, #0] break; 456: e00a b.n 46e SystemCoreClock = HSE_VALUE * pllmull; 458: 68bb ldr r3, [r7, #8] 45a: 4a11 ldr r2, [pc, #68] ; (4a0 ) 45c: fb02 f303 mul.w r3, r2, r3 460: 4a0e ldr r2, [pc, #56] ; (49c ) 462: 6013 str r3, [r2, #0] break; 464: e003 b.n 46e default: SystemCoreClock = HSI_VALUE; 466: 4b0d ldr r3, [pc, #52] ; (49c ) 468: 4a0d ldr r2, [pc, #52] ; (4a0 ) 46a: 601a str r2, [r3, #0] break; 46c: bf00 nop } /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 46e: 4b0a ldr r3, [pc, #40] ; (498 ) 470: 685b ldr r3, [r3, #4] 472: 091b lsrs r3, r3, #4 474: f003 030f and.w r3, r3, #15 478: 4a0b ldr r2, [pc, #44] ; (4a8 ) 47a: 5cd3 ldrb r3, [r2, r3] 47c: b2db uxtb r3, r3 47e: 60fb str r3, [r7, #12] /* HCLK clock frequency */ SystemCoreClock >>= tmp; 480: 4b06 ldr r3, [pc, #24] ; (49c ) 482: 681a ldr r2, [r3, #0] 484: 68fb ldr r3, [r7, #12] 486: fa22 f303 lsr.w r3, r2, r3 48a: 4a04 ldr r2, [pc, #16] ; (49c ) 48c: 6013 str r3, [r2, #0] } 48e: bf00 nop 490: 3714 adds r7, #20 492: 46bd mov sp, r7 494: bc80 pop {r7} 496: 4770 bx lr 498: 40021000 .word 0x40021000 49c: 20000000 .word 0x20000000 4a0: 007a1200 .word 0x007a1200 4a4: 003d0900 .word 0x003d0900 4a8: 20000004 .word 0x20000004 000004ac : * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. * @param None * @retval None */ static void SetSysClock(void) { 4ac: b580 push {r7, lr} 4ae: af00 add r7, sp, #0 #elif defined SYSCLK_FREQ_48MHz SetSysClockTo48(); #elif defined SYSCLK_FREQ_56MHz SetSysClockTo56(); #elif defined SYSCLK_FREQ_72MHz SetSysClockTo72(); 4b0: f000 f802 bl 4b8 #endif /* If none of the define above is enabled, the HSI is used as System clock source (default after reset) */ } 4b4: bf00 nop 4b6: bd80 pop {r7, pc} 000004b8 : * @note This function should be used only after reset. * @param None * @retval None */ static void SetSysClockTo72(void) { 4b8: b480 push {r7} 4ba: b083 sub sp, #12 4bc: af00 add r7, sp, #0 __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 4be: 2300 movs r3, #0 4c0: 607b str r3, [r7, #4] 4c2: 2300 movs r3, #0 4c4: 603b str r3, [r7, #0] /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); 4c6: 4b3a ldr r3, [pc, #232] ; (5b0 ) 4c8: 681b ldr r3, [r3, #0] 4ca: 4a39 ldr r2, [pc, #228] ; (5b0 ) 4cc: f443 3380 orr.w r3, r3, #65536 ; 0x10000 4d0: 6013 str r3, [r2, #0] /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; 4d2: 4b37 ldr r3, [pc, #220] ; (5b0 ) 4d4: 681b ldr r3, [r3, #0] 4d6: f403 3300 and.w r3, r3, #131072 ; 0x20000 4da: 603b str r3, [r7, #0] StartUpCounter++; 4dc: 687b ldr r3, [r7, #4] 4de: 3301 adds r3, #1 4e0: 607b str r3, [r7, #4] } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 4e2: 683b ldr r3, [r7, #0] 4e4: 2b00 cmp r3, #0 4e6: d103 bne.n 4f0 4e8: 687b ldr r3, [r7, #4] 4ea: f5b3 6fa0 cmp.w r3, #1280 ; 0x500 4ee: d1f0 bne.n 4d2 if ((RCC->CR & RCC_CR_HSERDY) != RESET) 4f0: 4b2f ldr r3, [pc, #188] ; (5b0 ) 4f2: 681b ldr r3, [r3, #0] 4f4: f403 3300 and.w r3, r3, #131072 ; 0x20000 4f8: 2b00 cmp r3, #0 4fa: d002 beq.n 502 { HSEStatus = (uint32_t)0x01; 4fc: 2301 movs r3, #1 4fe: 603b str r3, [r7, #0] 500: e001 b.n 506 } else { HSEStatus = (uint32_t)0x00; 502: 2300 movs r3, #0 504: 603b str r3, [r7, #0] } if (HSEStatus == (uint32_t)0x01) 506: 683b ldr r3, [r7, #0] 508: 2b01 cmp r3, #1 50a: d14b bne.n 5a4 { /* Enable Prefetch Buffer */ FLASH->ACR |= FLASH_ACR_PRFTBE; 50c: 4b29 ldr r3, [pc, #164] ; (5b4 ) 50e: 681b ldr r3, [r3, #0] 510: 4a28 ldr r2, [pc, #160] ; (5b4 ) 512: f043 0310 orr.w r3, r3, #16 516: 6013 str r3, [r2, #0] /* Flash 2 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 518: 4b26 ldr r3, [pc, #152] ; (5b4 ) 51a: 681b ldr r3, [r3, #0] 51c: 4a25 ldr r2, [pc, #148] ; (5b4 ) 51e: f023 0303 bic.w r3, r3, #3 522: 6013 str r3, [r2, #0] FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; 524: 4b23 ldr r3, [pc, #140] ; (5b4 ) 526: 681b ldr r3, [r3, #0] 528: 4a22 ldr r2, [pc, #136] ; (5b4 ) 52a: f043 0302 orr.w r3, r3, #2 52e: 6013 str r3, [r2, #0] /* HCLK = SYSCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 530: 4b1f ldr r3, [pc, #124] ; (5b0 ) 532: 4a1f ldr r2, [pc, #124] ; (5b0 ) 534: 685b ldr r3, [r3, #4] 536: 6053 str r3, [r2, #4] /* PCLK2 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 538: 4b1d ldr r3, [pc, #116] ; (5b0 ) 53a: 4a1d ldr r2, [pc, #116] ; (5b0 ) 53c: 685b ldr r3, [r3, #4] 53e: 6053 str r3, [r2, #4] /* PCLK1 = HCLK */ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; 540: 4b1b ldr r3, [pc, #108] ; (5b0 ) 542: 685b ldr r3, [r3, #4] 544: 4a1a ldr r2, [pc, #104] ; (5b0 ) 546: f443 6380 orr.w r3, r3, #1024 ; 0x400 54a: 6053 str r3, [r2, #4] RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9); #else /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | 54c: 4b18 ldr r3, [pc, #96] ; (5b0 ) 54e: 685b ldr r3, [r3, #4] 550: 4a17 ldr r2, [pc, #92] ; (5b0 ) 552: f423 137c bic.w r3, r3, #4128768 ; 0x3f0000 556: 6053 str r3, [r2, #4] RCC_CFGR_PLLMULL)); RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); 558: 4b15 ldr r3, [pc, #84] ; (5b0 ) 55a: 685b ldr r3, [r3, #4] 55c: 4a14 ldr r2, [pc, #80] ; (5b0 ) 55e: f443 13e8 orr.w r3, r3, #1900544 ; 0x1d0000 562: 6053 str r3, [r2, #4] #endif /* STM32F10X_CL */ /* Enable PLL */ RCC->CR |= RCC_CR_PLLON; 564: 4b12 ldr r3, [pc, #72] ; (5b0 ) 566: 681b ldr r3, [r3, #0] 568: 4a11 ldr r2, [pc, #68] ; (5b0 ) 56a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 56e: 6013 str r3, [r2, #0] /* Wait till PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) 570: bf00 nop 572: 4b0f ldr r3, [pc, #60] ; (5b0 ) 574: 681b ldr r3, [r3, #0] 576: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 57a: 2b00 cmp r3, #0 57c: d0f9 beq.n 572 { } /* Select PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 57e: 4b0c ldr r3, [pc, #48] ; (5b0 ) 580: 685b ldr r3, [r3, #4] 582: 4a0b ldr r2, [pc, #44] ; (5b0 ) 584: f023 0303 bic.w r3, r3, #3 588: 6053 str r3, [r2, #4] RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 58a: 4b09 ldr r3, [pc, #36] ; (5b0 ) 58c: 685b ldr r3, [r3, #4] 58e: 4a08 ldr r2, [pc, #32] ; (5b0 ) 590: f043 0302 orr.w r3, r3, #2 594: 6053 str r3, [r2, #4] /* Wait till PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) 596: bf00 nop 598: 4b05 ldr r3, [pc, #20] ; (5b0 ) 59a: 685b ldr r3, [r3, #4] 59c: f003 030c and.w r3, r3, #12 5a0: 2b08 cmp r3, #8 5a2: d1f9 bne.n 598 } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } 5a4: bf00 nop 5a6: 370c adds r7, #12 5a8: 46bd mov sp, r7 5aa: bc80 pop {r7} 5ac: 4770 bx lr 5ae: bf00 nop 5b0: 40021000 .word 0x40021000 5b4: 40022000 .word 0x40022000 5b8: 00005bad .word 0x00005bad 5bc: 20000000 .word 0x20000000 5c0: 20000028 .word 0x20000028 5c4: 20000028 .word 0x20000028 5c8: 20000028 .word 0x20000028 000005cc : #include "stm32f10x_exti.h" #include "stm32f10x_adc.h" #include "misc.h" void init_led(void) { 5cc: b580 push {r7, lr} 5ce: b082 sub sp, #8 5d0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStructure; /* Enable GPIO C clock. */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); 5d2: 2101 movs r1, #1 5d4: 2010 movs r0, #16 5d6: f001 f897 bl 1708 /* Set the LED pin state such that the LED is off. The LED is connected * between power and the microcontroller pin, which makes it turn on when * the pin is low. */ GPIO_WriteBit(GPIOC,GPIO_Pin_12,Bit_SET); 5da: 2201 movs r2, #1 5dc: f44f 5180 mov.w r1, #4096 ; 0x1000 5e0: 4809 ldr r0, [pc, #36] ; (608 ) 5e2: f001 fb5e bl 1ca2 /* Configure the LED pin as push-pull output. */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; 5e6: f44f 5380 mov.w r3, #4096 ; 0x1000 5ea: 80bb strh r3, [r7, #4] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 5ec: 2310 movs r3, #16 5ee: 71fb strb r3, [r7, #7] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 5f0: 2303 movs r3, #3 5f2: 71bb strb r3, [r7, #6] GPIO_Init(GPIOC, &GPIO_InitStructure); 5f4: 1d3b adds r3, r7, #4 5f6: 4619 mov r1, r3 5f8: 4803 ldr r0, [pc, #12] ; (608 ) 5fa: f001 fa1d bl 1a38 } 5fe: bf00 nop 600: 3708 adds r7, #8 602: 46bd mov sp, r7 604: bd80 pop {r7, pc} 606: bf00 nop 608: 40011000 .word 0x40011000 0000060c : void init_button(void) { 60c: b580 push {r7, lr} 60e: b082 sub sp, #8 610: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStructure; /* Enable GPIO A clock */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 612: 2101 movs r1, #1 614: 2004 movs r0, #4 616: f001 f877 bl 1708 /* Configure the button pin as a floating input. */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; 61a: 2301 movs r3, #1 61c: 80bb strh r3, [r7, #4] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; 61e: 2304 movs r3, #4 620: 71fb strb r3, [r7, #7] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 622: 2303 movs r3, #3 624: 71bb strb r3, [r7, #6] GPIO_Init(GPIOC, &GPIO_InitStructure); 626: 1d3b adds r3, r7, #4 628: 4619 mov r1, r3 62a: 4803 ldr r0, [pc, #12] ; (638 ) 62c: f001 fa04 bl 1a38 } 630: bf00 nop 632: 3708 adds r7, #8 634: 46bd mov sp, r7 636: bd80 pop {r7, pc} 638: 40011000 .word 0x40011000 0000063c : void enable_button_interrupts(void) { 63c: b580 push {r7, lr} 63e: b084 sub sp, #16 640: af00 add r7, sp, #0 NVIC_InitTypeDef NVIC_InitStructure; /* Enable the AFIO clock. GPIO_EXTILineConfig sets registers in * the AFIO. */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); 642: 2101 movs r1, #1 644: 2001 movs r0, #1 646: f001 f85f bl 1708 /* Connect EXTI Line 0 to the button GPIO Pin */ GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource0); 64a: 2100 movs r1, #0 64c: 2000 movs r0, #0 64e: f001 fc13 bl 1e78 /* Configure the EXTI line to generate an interrupt when the button is * pressed. The button pin is high when pressed, so it needs to trigger * when rising from low to high. */ EXTI_InitStructure.EXTI_Line = EXTI_Line0; 652: 2301 movs r3, #1 654: 60bb str r3, [r7, #8] EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; 656: 2300 movs r3, #0 658: 733b strb r3, [r7, #12] EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; 65a: 2308 movs r3, #8 65c: 737b strb r3, [r7, #13] EXTI_InitStructure.EXTI_LineCmd = ENABLE; 65e: 2301 movs r3, #1 660: 73bb strb r3, [r7, #14] EXTI_Init(&EXTI_InitStructure); 662: f107 0308 add.w r3, r7, #8 666: 4618 mov r0, r3 668: f002 f8dc bl 2824 /* Enable and set Button EXTI Interrupt to the lowest priority */ NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; 66c: 2306 movs r3, #6 66e: 713b strb r3, [r7, #4] NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; 670: 230f movs r3, #15 672: 717b strb r3, [r7, #5] NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; 674: 230f movs r3, #15 676: 71bb strb r3, [r7, #6] NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 678: 2301 movs r3, #1 67a: 71fb strb r3, [r7, #7] NVIC_Init(&NVIC_InitStructure); 67c: 1d3b adds r3, r7, #4 67e: 4618 mov r0, r3 680: f005 f87c bl 577c } 684: bf00 nop 686: 3710 adds r7, #16 688: 46bd mov sp, r7 68a: bd80 pop {r7, pc} 0000068c : void init_rs232(void) { 68c: b580 push {r7, lr} 68e: b086 sub sp, #24 690: af00 add r7, sp, #0 USART_InitTypeDef USART_InitStructure; GPIO_InitTypeDef GPIO_InitStructure; /* Enable peripheral clocks. */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE); 692: 2101 movs r1, #1 694: 2005 movs r0, #5 696: f001 f837 bl 1708 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); 69a: 2101 movs r1, #1 69c: f44f 3000 mov.w r0, #131072 ; 0x20000 6a0: f001 f850 bl 1744 /* Configure USART2 Rx pin as floating input. */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; 6a4: 2308 movs r3, #8 6a6: 80bb strh r3, [r7, #4] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; 6a8: 2304 movs r3, #4 6aa: 71fb strb r3, [r7, #7] GPIO_Init(GPIOA, &GPIO_InitStructure); 6ac: 1d3b adds r3, r7, #4 6ae: 4619 mov r1, r3 6b0: 4814 ldr r0, [pc, #80] ; (704 ) 6b2: f001 f9c1 bl 1a38 /* Configure USART2 Tx as alternate function push-pull. */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 6b6: 2304 movs r3, #4 6b8: 80bb strh r3, [r7, #4] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 6ba: 2303 movs r3, #3 6bc: 71bb strb r3, [r7, #6] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 6be: 2318 movs r3, #24 6c0: 71fb strb r3, [r7, #7] GPIO_Init(GPIOA, &GPIO_InitStructure); 6c2: 1d3b adds r3, r7, #4 6c4: 4619 mov r1, r3 6c6: 480f ldr r0, [pc, #60] ; (704 ) 6c8: f001 f9b6 bl 1a38 /* Configure the USART2 */ USART_InitStructure.USART_BaudRate = 9600; 6cc: f44f 5316 mov.w r3, #9600 ; 0x2580 6d0: 60bb str r3, [r7, #8] USART_InitStructure.USART_WordLength = USART_WordLength_8b; 6d2: 2300 movs r3, #0 6d4: 81bb strh r3, [r7, #12] USART_InitStructure.USART_StopBits = USART_StopBits_1; 6d6: 2300 movs r3, #0 6d8: 81fb strh r3, [r7, #14] USART_InitStructure.USART_Parity = USART_Parity_No; 6da: 2300 movs r3, #0 6dc: 823b strh r3, [r7, #16] USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 6de: 2300 movs r3, #0 6e0: 82bb strh r3, [r7, #20] USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 6e2: 230c movs r3, #12 6e4: 827b strh r3, [r7, #18] USART_Init(USART2, &USART_InitStructure); 6e6: f107 0308 add.w r3, r7, #8 6ea: 4619 mov r1, r3 6ec: 4806 ldr r0, [pc, #24] ; (708 ) 6ee: f001 fc6d bl 1fcc USART_Cmd(USART2, ENABLE); 6f2: 2101 movs r1, #1 6f4: 4804 ldr r0, [pc, #16] ; (708 ) 6f6: f001 fd7f bl 21f8 } 6fa: bf00 nop 6fc: 3718 adds r7, #24 6fe: 46bd mov sp, r7 700: bd80 pop {r7, pc} 702: bf00 nop 704: 40010800 .word 0x40010800 708: 40004400 .word 0x40004400 0000070c : void enable_rs232_interrupts(void) { 70c: b580 push {r7, lr} 70e: b082 sub sp, #8 710: af00 add r7, sp, #0 NVIC_InitTypeDef NVIC_InitStructure; /* Enable transmit and receive interrupts for the USART2. */ USART_ITConfig(USART2, USART_IT_TXE, DISABLE); 712: 2200 movs r2, #0 714: f240 7127 movw r1, #1831 ; 0x727 718: 480b ldr r0, [pc, #44] ; (748 ) 71a: f001 fd8c bl 2236 USART_ITConfig(USART2, USART_IT_RXNE, ENABLE); 71e: 2201 movs r2, #1 720: f240 5125 movw r1, #1317 ; 0x525 724: 4808 ldr r0, [pc, #32] ; (748 ) 726: f001 fd86 bl 2236 /* Enable the USART2 IRQ in the NVIC module (so that the USART2 interrupt * handler is enabled). */ NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn; 72a: 2326 movs r3, #38 ; 0x26 72c: 713b strb r3, [r7, #4] NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; 72e: 2300 movs r3, #0 730: 71bb strb r3, [r7, #6] NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 732: 2301 movs r3, #1 734: 71fb strb r3, [r7, #7] NVIC_Init(&NVIC_InitStructure); 736: 1d3b adds r3, r7, #4 738: 4618 mov r0, r3 73a: f005 f81f bl 577c } 73e: bf00 nop 740: 3708 adds r7, #8 742: 46bd mov sp, r7 744: bd80 pop {r7, pc} 746: bf00 nop 748: 40004400 .word 0x40004400 0000074c : void enable_rs232(void) { 74c: b580 push {r7, lr} 74e: af00 add r7, sp, #0 /* Enable the RS232 port. */ USART_Cmd(USART2, ENABLE); 750: 2101 movs r1, #1 752: 4802 ldr r0, [pc, #8] ; (75c ) 754: f001 fd50 bl 21f8 } 758: bf00 nop 75a: bd80 pop {r7, pc} 75c: 40004400 .word 0x40004400 00000760 : void rs232_print_str(const char *str) { 760: b580 push {r7, lr} 762: b084 sub sp, #16 764: af00 add r7, sp, #0 766: 6078 str r0, [r7, #4] const char *curr_char = str; 768: 687b ldr r3, [r7, #4] 76a: 60fb str r3, [r7, #12] while(*curr_char != '\0') { 76c: e011 b.n 792 while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); 76e: bf00 nop 770: 2180 movs r1, #128 ; 0x80 772: 480c ldr r0, [pc, #48] ; (7a4 ) 774: f001 ff9a bl 26ac 778: 4603 mov r3, r0 77a: 2b00 cmp r3, #0 77c: d0f8 beq.n 770 USART_SendData(USART2, *curr_char); 77e: 68fb ldr r3, [r7, #12] 780: 781b ldrb r3, [r3, #0] 782: b29b uxth r3, r3 784: 4619 mov r1, r3 786: 4807 ldr r0, [pc, #28] ; (7a4 ) 788: f001 fe4f bl 242a curr_char++; 78c: 68fb ldr r3, [r7, #12] 78e: 3301 adds r3, #1 790: 60fb str r3, [r7, #12] while(*curr_char != '\0') { 792: 68fb ldr r3, [r7, #12] 794: 781b ldrb r3, [r3, #0] 796: 2b00 cmp r3, #0 798: d1e9 bne.n 76e } } 79a: bf00 nop 79c: bf00 nop 79e: 3710 adds r7, #16 7a0: 46bd mov sp, r7 7a2: bd80 pop {r7, pc} 7a4: 40004400 .word 0x40004400 000007a8 : /* Functions for sending numbers through the UART */ char hex_to_char(unsigned hex_number) { 7a8: b480 push {r7} 7aa: b083 sub sp, #12 7ac: af00 add r7, sp, #0 7ae: 6078 str r0, [r7, #4] if(hex_number < 0xA) { 7b0: 687b ldr r3, [r7, #4] 7b2: 2b09 cmp r3, #9 7b4: d804 bhi.n 7c0 return hex_number + '0'; 7b6: 687b ldr r3, [r7, #4] 7b8: b2db uxtb r3, r3 7ba: 3330 adds r3, #48 ; 0x30 7bc: b2db uxtb r3, r3 7be: e003 b.n 7c8 } else { return hex_number - 0xA + 'A'; 7c0: 687b ldr r3, [r7, #4] 7c2: b2db uxtb r3, r3 7c4: 3337 adds r3, #55 ; 0x37 7c6: b2db uxtb r3, r3 } } 7c8: 4618 mov r0, r3 7ca: 370c adds r7, #12 7cc: 46bd mov sp, r7 7ce: bc80 pop {r7} 7d0: 4770 bx lr 000007d2 : void send_byte(uint8_t b) { 7d2: b580 push {r7, lr} 7d4: b082 sub sp, #8 7d6: af00 add r7, sp, #0 7d8: 4603 mov r3, r0 7da: 71fb strb r3, [r7, #7] /* Wait until the RS232 port can receive another byte. */ while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); 7dc: bf00 nop 7de: 2180 movs r1, #128 ; 0x80 7e0: 480a ldr r0, [pc, #40] ; (80c ) 7e2: f001 ff63 bl 26ac 7e6: 4603 mov r3, r0 7e8: 2b00 cmp r3, #0 7ea: d0f8 beq.n 7de /* Toggle the LED just to show that progress is being made. */ GPIOC->ODR ^= 0x00001000; 7ec: 4b08 ldr r3, [pc, #32] ; (810 ) 7ee: 68db ldr r3, [r3, #12] 7f0: 4a07 ldr r2, [pc, #28] ; (810 ) 7f2: f483 5380 eor.w r3, r3, #4096 ; 0x1000 7f6: 60d3 str r3, [r2, #12] /* Send the byte */ USART_SendData(USART2, b); 7f8: 79fb ldrb r3, [r7, #7] 7fa: b29b uxth r3, r3 7fc: 4619 mov r1, r3 7fe: 4803 ldr r0, [pc, #12] ; (80c ) 800: f001 fe13 bl 242a } 804: bf00 nop 806: 3708 adds r7, #8 808: 46bd mov sp, r7 80a: bd80 pop {r7, pc} 80c: 40004400 .word 0x40004400 810: 40011000 .word 0x40011000 00000814 : void send_number(unsigned long sample, int radix) { 814: b580 push {r7, lr} 816: b09e sub sp, #120 ; 0x78 818: af00 add r7, sp, #0 81a: 6078 str r0, [r7, #4] 81c: 6039 str r1, [r7, #0] int digit; unsigned long mod; char str[100]; digit = 0; 81e: 2300 movs r3, #0 820: 677b str r3, [r7, #116] ; 0x74 do { mod = sample % radix; 822: 683a ldr r2, [r7, #0] 824: 687b ldr r3, [r7, #4] 826: fbb3 f1f2 udiv r1, r3, r2 82a: fb02 f201 mul.w r2, r2, r1 82e: 1a9b subs r3, r3, r2 830: 673b str r3, [r7, #112] ; 0x70 str[digit] = hex_to_char(mod); 832: 6f38 ldr r0, [r7, #112] ; 0x70 834: f7ff ffb8 bl 7a8 838: 4603 mov r3, r0 83a: 4619 mov r1, r3 83c: f107 020c add.w r2, r7, #12 840: 6f7b ldr r3, [r7, #116] ; 0x74 842: 4413 add r3, r2 844: 460a mov r2, r1 846: 701a strb r2, [r3, #0] sample /= radix; 848: 683b ldr r3, [r7, #0] 84a: 687a ldr r2, [r7, #4] 84c: fbb2 f3f3 udiv r3, r2, r3 850: 607b str r3, [r7, #4] digit++; 852: 6f7b ldr r3, [r7, #116] ; 0x74 854: 3301 adds r3, #1 856: 677b str r3, [r7, #116] ; 0x74 } while(sample != 0); 858: 687b ldr r3, [r7, #4] 85a: 2b00 cmp r3, #0 85c: d1e1 bne.n 822 while(digit != 0) { 85e: e014 b.n 88a digit--; 860: 6f7b ldr r3, [r7, #116] ; 0x74 862: 3b01 subs r3, #1 864: 677b str r3, [r7, #116] ; 0x74 while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); 866: bf00 nop 868: 2180 movs r1, #128 ; 0x80 86a: 480c ldr r0, [pc, #48] ; (89c ) 86c: f001 ff1e bl 26ac 870: 4603 mov r3, r0 872: 2b00 cmp r3, #0 874: d0f8 beq.n 868 USART_SendData(USART2, str[digit]); 876: f107 020c add.w r2, r7, #12 87a: 6f7b ldr r3, [r7, #116] ; 0x74 87c: 4413 add r3, r2 87e: 781b ldrb r3, [r3, #0] 880: b29b uxth r3, r3 882: 4619 mov r1, r3 884: 4805 ldr r0, [pc, #20] ; (89c ) 886: f001 fdd0 bl 242a while(digit != 0) { 88a: 6f7b ldr r3, [r7, #116] ; 0x74 88c: 2b00 cmp r3, #0 88e: d1e7 bne.n 860 } } 890: bf00 nop 892: bf00 nop 894: 3778 adds r7, #120 ; 0x78 896: 46bd mov sp, r7 898: bd80 pop {r7, pc} 89a: bf00 nop 89c: 40004400 .word 0x40004400 000008a0 : #define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ #define SMALL 64 /* use 'abcdef' instead of 'ABCDEF' */ #define PBSIZE 128 /* Print Buffer Size */ void myprintf_init() { 8a0: b580 push {r7, lr} 8a2: af00 add r7, sp, #0 init_rs232(); 8a4: f7ff fef2 bl 68c enable_rs232_interrupts(); 8a8: f7ff ff30 bl 70c enable_rs232(); 8ac: f7ff ff4e bl 74c } 8b0: bf00 nop 8b2: bd80 pop {r7, pc} 000008b4 : void usart_send_bytes(uint8_t data) { 8b4: b580 push {r7, lr} 8b6: b082 sub sp, #8 8b8: af00 add r7, sp, #0 8ba: 4603 mov r3, r0 8bc: 71fb strb r3, [r7, #7] while(!USART_GetFlagStatus(USART2 ,USART_FLAG_TXE)) { 8be: bf00 nop 8c0: 2180 movs r1, #128 ; 0x80 8c2: 4808 ldr r0, [pc, #32] ; (8e4 ) 8c4: f001 fef2 bl 26ac 8c8: 4603 mov r3, r0 8ca: 2b00 cmp r3, #0 8cc: d0f8 beq.n 8c0 } USART_SendData( USART2, data); 8ce: 79fb ldrb r3, [r7, #7] 8d0: b29b uxth r3, r3 8d2: 4619 mov r1, r3 8d4: 4803 ldr r0, [pc, #12] ; (8e4 ) 8d6: f001 fda8 bl 242a } 8da: bf00 nop 8dc: 3708 adds r7, #8 8de: 46bd mov sp, r7 8e0: bd80 pop {r7, pc} 8e2: bf00 nop 8e4: 40004400 .word 0x40004400 000008e8 : signed int mystrnlen (const char * s, signed int count) { 8e8: b480 push {r7} 8ea: b085 sub sp, #20 8ec: af00 add r7, sp, #0 8ee: 6078 str r0, [r7, #4] 8f0: 6039 str r1, [r7, #0] const char *sc; for (sc = s; count-- && *sc != '\0'; ++sc) { 8f2: 687b ldr r3, [r7, #4] 8f4: 60fb str r3, [r7, #12] 8f6: e002 b.n 8fe 8f8: 68fb ldr r3, [r7, #12] 8fa: 3301 adds r3, #1 8fc: 60fb str r3, [r7, #12] 8fe: 683b ldr r3, [r7, #0] 900: 1e5a subs r2, r3, #1 902: 603a str r2, [r7, #0] 904: 2b00 cmp r3, #0 906: d003 beq.n 910 908: 68fb ldr r3, [r7, #12] 90a: 781b ldrb r3, [r3, #0] 90c: 2b00 cmp r3, #0 90e: d1f3 bne.n 8f8 /* nothing */ } return sc - s; 910: 68fa ldr r2, [r7, #12] 912: 687b ldr r3, [r7, #4] 914: 1ad3 subs r3, r2, r3 } 916: 4618 mov r0, r3 918: 3714 adds r7, #20 91a: 46bd mov sp, r7 91c: bc80 pop {r7} 91e: 4770 bx lr 00000920 : static int myskip_atoi (const char **s) { 920: b480 push {r7} 922: b085 sub sp, #20 924: af00 add r7, sp, #0 926: 6078 str r0, [r7, #4] int i = 0; 928: 2300 movs r3, #0 92a: 60fb str r3, [r7, #12] while (isdigit(**s) != 0) { 92c: e00e b.n 94c i = i * 10 + *((*s)++) - '0'; 92e: 68fa ldr r2, [r7, #12] 930: 4613 mov r3, r2 932: 009b lsls r3, r3, #2 934: 4413 add r3, r2 936: 005b lsls r3, r3, #1 938: 4618 mov r0, r3 93a: 687b ldr r3, [r7, #4] 93c: 681b ldr r3, [r3, #0] 93e: 1c59 adds r1, r3, #1 940: 687a ldr r2, [r7, #4] 942: 6011 str r1, [r2, #0] 944: 781b ldrb r3, [r3, #0] 946: 4403 add r3, r0 948: 3b30 subs r3, #48 ; 0x30 94a: 60fb str r3, [r7, #12] while (isdigit(**s) != 0) { 94c: 687b ldr r3, [r7, #4] 94e: 681b ldr r3, [r3, #0] 950: 781b ldrb r3, [r3, #0] 952: 3301 adds r3, #1 954: 4a06 ldr r2, [pc, #24] ; (970 ) 956: 4413 add r3, r2 958: 781b ldrb r3, [r3, #0] 95a: f003 0304 and.w r3, r3, #4 95e: 2b00 cmp r3, #0 960: d1e5 bne.n 92e } return i; 962: 68fb ldr r3, [r7, #12] } 964: 4618 mov r0, r3 966: 3714 adds r7, #20 968: 46bd mov sp, r7 96a: bc80 pop {r7} 96c: 4770 bx lr 96e: bf00 nop 970: 00005aac .word 0x00005aac 00000974 : static char * mynumber (char * str, long num, int base, int size, int precision ,int type) { 974: b580 push {r7, lr} 976: b09a sub sp, #104 ; 0x68 978: af00 add r7, sp, #0 97a: 60f8 str r0, [r7, #12] 97c: 60b9 str r1, [r7, #8] 97e: 607a str r2, [r7, #4] 980: 603b str r3, [r7, #0] char c = 0; 982: 2300 movs r3, #0 984: f887 305b strb.w r3, [r7, #91] ; 0x5b char sign = 0; 988: 2300 movs r3, #0 98a: f887 3067 strb.w r3, [r7, #103] ; 0x67 char tmp[66] = {0}; 98e: 2300 movs r3, #0 990: 613b str r3, [r7, #16] 992: f107 0314 add.w r3, r7, #20 996: 223e movs r2, #62 ; 0x3e 998: 2100 movs r1, #0 99a: 4618 mov r0, r3 99c: f004 ffd2 bl 5944 int i = 0; 9a0: 2300 movs r3, #0 9a2: 663b str r3, [r7, #96] ; 0x60 const char *digits = "0123456789abcdefghijklmnopqrstuvwxyz"; 9a4: 4b85 ldr r3, [pc, #532] ; (bbc ) 9a6: 65fb str r3, [r7, #92] ; 0x5c if ((type & LARGE) != 0) { 9a8: 6f7b ldr r3, [r7, #116] ; 0x74 9aa: f003 0340 and.w r3, r3, #64 ; 0x40 9ae: 2b00 cmp r3, #0 9b0: d001 beq.n 9b6 digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; 9b2: 4b83 ldr r3, [pc, #524] ; (bc0 ) 9b4: 65fb str r3, [r7, #92] ; 0x5c } if ((type & LEFT) != 0) { 9b6: 6f7b ldr r3, [r7, #116] ; 0x74 9b8: f003 0310 and.w r3, r3, #16 9bc: 2b00 cmp r3, #0 9be: d003 beq.n 9c8 type &= ~ZEROPAD; 9c0: 6f7b ldr r3, [r7, #116] ; 0x74 9c2: f023 0301 bic.w r3, r3, #1 9c6: 677b str r3, [r7, #116] ; 0x74 } if ((base < 2) || (base > 36)) { 9c8: 687b ldr r3, [r7, #4] 9ca: 2b01 cmp r3, #1 9cc: dd02 ble.n 9d4 9ce: 687b ldr r3, [r7, #4] 9d0: 2b24 cmp r3, #36 ; 0x24 9d2: dd01 ble.n 9d8 return 0; 9d4: 2300 movs r3, #0 9d6: e0ec b.n bb2 } c = (type & ZEROPAD) ? '0' : ' '; 9d8: 6f7b ldr r3, [r7, #116] ; 0x74 9da: f003 0301 and.w r3, r3, #1 9de: 2b00 cmp r3, #0 9e0: d001 beq.n 9e6 9e2: 2330 movs r3, #48 ; 0x30 9e4: e000 b.n 9e8 9e6: 2320 movs r3, #32 9e8: f887 305b strb.w r3, [r7, #91] ; 0x5b sign = 0; 9ec: 2300 movs r3, #0 9ee: f887 3067 strb.w r3, [r7, #103] ; 0x67 if ((type & SIGN) != 0) { 9f2: 6f7b ldr r3, [r7, #116] ; 0x74 9f4: f003 0302 and.w r3, r3, #2 9f8: 2b00 cmp r3, #0 9fa: d023 beq.n a44 if (num < 0) { 9fc: 68bb ldr r3, [r7, #8] 9fe: 2b00 cmp r3, #0 a00: da09 bge.n a16 sign = '-'; a02: 232d movs r3, #45 ; 0x2d a04: f887 3067 strb.w r3, [r7, #103] ; 0x67 num = -num; a08: 68bb ldr r3, [r7, #8] a0a: 425b negs r3, r3 a0c: 60bb str r3, [r7, #8] size--; a0e: 683b ldr r3, [r7, #0] a10: 3b01 subs r3, #1 a12: 603b str r3, [r7, #0] a14: e016 b.n a44 } else if ((type & PLUS) != 0) { a16: 6f7b ldr r3, [r7, #116] ; 0x74 a18: f003 0304 and.w r3, r3, #4 a1c: 2b00 cmp r3, #0 a1e: d006 beq.n a2e sign = '+'; a20: 232b movs r3, #43 ; 0x2b a22: f887 3067 strb.w r3, [r7, #103] ; 0x67 size--; a26: 683b ldr r3, [r7, #0] a28: 3b01 subs r3, #1 a2a: 603b str r3, [r7, #0] a2c: e00a b.n a44 } else if ((type & SPACE) != 0) { a2e: 6f7b ldr r3, [r7, #116] ; 0x74 a30: f003 0308 and.w r3, r3, #8 a34: 2b00 cmp r3, #0 a36: d005 beq.n a44 sign = ' '; a38: 2320 movs r3, #32 a3a: f887 3067 strb.w r3, [r7, #103] ; 0x67 size--; a3e: 683b ldr r3, [r7, #0] a40: 3b01 subs r3, #1 a42: 603b str r3, [r7, #0] } } if ((type & SPECIAL) != 0) { a44: 6f7b ldr r3, [r7, #116] ; 0x74 a46: f003 0320 and.w r3, r3, #32 a4a: 2b00 cmp r3, #0 a4c: d00c beq.n a68 if (16 == base) { a4e: 687b ldr r3, [r7, #4] a50: 2b10 cmp r3, #16 a52: d103 bne.n a5c size -= 2; a54: 683b ldr r3, [r7, #0] a56: 3b02 subs r3, #2 a58: 603b str r3, [r7, #0] a5a: e005 b.n a68 } else if (8 == base) { a5c: 687b ldr r3, [r7, #4] a5e: 2b08 cmp r3, #8 a60: d102 bne.n a68 size--; a62: 683b ldr r3, [r7, #0] a64: 3b01 subs r3, #1 a66: 603b str r3, [r7, #0] } } i = 0; a68: 2300 movs r3, #0 a6a: 663b str r3, [r7, #96] ; 0x60 if (0 == num) { a6c: 68bb ldr r3, [r7, #8] a6e: 2b00 cmp r3, #0 a70: d123 bne.n aba tmp[i++] = '0'; a72: 6e3b ldr r3, [r7, #96] ; 0x60 a74: 1c5a adds r2, r3, #1 a76: 663a str r2, [r7, #96] ; 0x60 a78: f107 0268 add.w r2, r7, #104 ; 0x68 a7c: 4413 add r3, r2 a7e: 2230 movs r2, #48 ; 0x30 a80: f803 2c58 strb.w r2, [r3, #-88] a84: e01c b.n ac0 } else { while (num != 0) { tmp[i++] = digits[mydo_div(num,base)]; a86: 68bb ldr r3, [r7, #8] a88: 687a ldr r2, [r7, #4] a8a: fbb3 f1f2 udiv r1, r3, r2 a8e: fb02 f201 mul.w r2, r2, r1 a92: 1a9b subs r3, r3, r2 a94: 657b str r3, [r7, #84] ; 0x54 a96: 68ba ldr r2, [r7, #8] a98: 687b ldr r3, [r7, #4] a9a: fbb2 f3f3 udiv r3, r2, r3 a9e: 60bb str r3, [r7, #8] aa0: 6d7b ldr r3, [r7, #84] ; 0x54 aa2: 461a mov r2, r3 aa4: 6dfb ldr r3, [r7, #92] ; 0x5c aa6: 441a add r2, r3 aa8: 6e3b ldr r3, [r7, #96] ; 0x60 aaa: 1c59 adds r1, r3, #1 aac: 6639 str r1, [r7, #96] ; 0x60 aae: 7812 ldrb r2, [r2, #0] ab0: f107 0168 add.w r1, r7, #104 ; 0x68 ab4: 440b add r3, r1 ab6: f803 2c58 strb.w r2, [r3, #-88] while (num != 0) { aba: 68bb ldr r3, [r7, #8] abc: 2b00 cmp r3, #0 abe: d1e2 bne.n a86 } } if (i > precision) { ac0: 6e3a ldr r2, [r7, #96] ; 0x60 ac2: 6f3b ldr r3, [r7, #112] ; 0x70 ac4: 429a cmp r2, r3 ac6: dd01 ble.n acc precision = i; ac8: 6e3b ldr r3, [r7, #96] ; 0x60 aca: 673b str r3, [r7, #112] ; 0x70 } size -= precision; acc: 683a ldr r2, [r7, #0] ace: 6f3b ldr r3, [r7, #112] ; 0x70 ad0: 1ad3 subs r3, r2, r3 ad2: 603b str r3, [r7, #0] if (0 == (type & (ZEROPAD + LEFT))) { ad4: 6f7b ldr r3, [r7, #116] ; 0x74 ad6: f003 0311 and.w r3, r3, #17 ada: 2b00 cmp r3, #0 adc: d10a bne.n af4 while (size-- > 0) { ade: e004 b.n aea *str++ = ' '; ae0: 68fb ldr r3, [r7, #12] ae2: 1c5a adds r2, r3, #1 ae4: 60fa str r2, [r7, #12] ae6: 2220 movs r2, #32 ae8: 701a strb r2, [r3, #0] while (size-- > 0) { aea: 683b ldr r3, [r7, #0] aec: 1e5a subs r2, r3, #1 aee: 603a str r2, [r7, #0] af0: 2b00 cmp r3, #0 af2: dcf5 bgt.n ae0 } } if (sign != 0) { af4: f897 3067 ldrb.w r3, [r7, #103] ; 0x67 af8: 2b00 cmp r3, #0 afa: d005 beq.n b08 *str++ = sign; afc: 68fb ldr r3, [r7, #12] afe: 1c5a adds r2, r3, #1 b00: 60fa str r2, [r7, #12] b02: f897 2067 ldrb.w r2, [r7, #103] ; 0x67 b06: 701a strb r2, [r3, #0] } if ((type & SPECIAL) != 0) { b08: 6f7b ldr r3, [r7, #116] ; 0x74 b0a: f003 0320 and.w r3, r3, #32 b0e: 2b00 cmp r3, #0 b10: d017 beq.n b42 if (8 == base) { b12: 687b ldr r3, [r7, #4] b14: 2b08 cmp r3, #8 b16: d105 bne.n b24 *str++ = '0'; b18: 68fb ldr r3, [r7, #12] b1a: 1c5a adds r2, r3, #1 b1c: 60fa str r2, [r7, #12] b1e: 2230 movs r2, #48 ; 0x30 b20: 701a strb r2, [r3, #0] b22: e00e b.n b42 } else if (16 == base) { b24: 687b ldr r3, [r7, #4] b26: 2b10 cmp r3, #16 b28: d10b bne.n b42 *str++ = '0'; b2a: 68fb ldr r3, [r7, #12] b2c: 1c5a adds r2, r3, #1 b2e: 60fa str r2, [r7, #12] b30: 2230 movs r2, #48 ; 0x30 b32: 701a strb r2, [r3, #0] *str++ = digits[33]; b34: 68fb ldr r3, [r7, #12] b36: 1c5a adds r2, r3, #1 b38: 60fa str r2, [r7, #12] b3a: 6dfa ldr r2, [r7, #92] ; 0x5c b3c: f892 2021 ldrb.w r2, [r2, #33] ; 0x21 b40: 701a strb r2, [r3, #0] } } if (0 == (type & LEFT)) { b42: 6f7b ldr r3, [r7, #116] ; 0x74 b44: f003 0310 and.w r3, r3, #16 b48: 2b00 cmp r3, #0 b4a: d111 bne.n b70 while (size-- > 0) { b4c: e005 b.n b5a *str++ = c; b4e: 68fb ldr r3, [r7, #12] b50: 1c5a adds r2, r3, #1 b52: 60fa str r2, [r7, #12] b54: f897 205b ldrb.w r2, [r7, #91] ; 0x5b b58: 701a strb r2, [r3, #0] while (size-- > 0) { b5a: 683b ldr r3, [r7, #0] b5c: 1e5a subs r2, r3, #1 b5e: 603a str r2, [r7, #0] b60: 2b00 cmp r3, #0 b62: dcf4 bgt.n b4e } } while (i < precision--) { b64: e004 b.n b70 *str++ = '0'; b66: 68fb ldr r3, [r7, #12] b68: 1c5a adds r2, r3, #1 b6a: 60fa str r2, [r7, #12] b6c: 2230 movs r2, #48 ; 0x30 b6e: 701a strb r2, [r3, #0] while (i < precision--) { b70: 6f3b ldr r3, [r7, #112] ; 0x70 b72: 1e5a subs r2, r3, #1 b74: 673a str r2, [r7, #112] ; 0x70 b76: 6e3a ldr r2, [r7, #96] ; 0x60 b78: 429a cmp r2, r3 b7a: dbf4 blt.n b66 } while (i-- > 0) { b7c: e008 b.n b90 *str++ = tmp[i]; b7e: 68fb ldr r3, [r7, #12] b80: 1c5a adds r2, r3, #1 b82: 60fa str r2, [r7, #12] b84: f107 0110 add.w r1, r7, #16 b88: 6e3a ldr r2, [r7, #96] ; 0x60 b8a: 440a add r2, r1 b8c: 7812 ldrb r2, [r2, #0] b8e: 701a strb r2, [r3, #0] while (i-- > 0) { b90: 6e3b ldr r3, [r7, #96] ; 0x60 b92: 1e5a subs r2, r3, #1 b94: 663a str r2, [r7, #96] ; 0x60 b96: 2b00 cmp r3, #0 b98: dcf1 bgt.n b7e } while (size-- > 0) { b9a: e004 b.n ba6 *str++ = ' '; b9c: 68fb ldr r3, [r7, #12] b9e: 1c5a adds r2, r3, #1 ba0: 60fa str r2, [r7, #12] ba2: 2220 movs r2, #32 ba4: 701a strb r2, [r3, #0] while (size-- > 0) { ba6: 683b ldr r3, [r7, #0] ba8: 1e5a subs r2, r3, #1 baa: 603a str r2, [r7, #0] bac: 2b00 cmp r3, #0 bae: dcf5 bgt.n b9c } return str; bb0: 68fb ldr r3, [r7, #12] } bb2: 4618 mov r0, r3 bb4: 3768 adds r7, #104 ; 0x68 bb6: 46bd mov sp, r7 bb8: bd80 pop {r7, pc} bba: bf00 nop bbc: 00005a2c .word 0x00005a2c bc0: 00005a54 .word 0x00005a54 00000bc4 : * * If you're not already dealing with a va_list consider using sprintf(). */ int myvsprintf (char *buf, const char *fmt, va_list args) { bc4: b580 push {r7, lr} bc6: b092 sub sp, #72 ; 0x48 bc8: af02 add r7, sp, #8 bca: 60f8 str r0, [r7, #12] bcc: 60b9 str r1, [r7, #8] bce: 607a str r2, [r7, #4] int qualifier; //'h', 'l', or 'q' for integer fields char * str; const char *s; unsigned long num; for (str = buf; *fmt; ++fmt) { bd0: 68fb ldr r3, [r7, #12] bd2: 627b str r3, [r7, #36] ; 0x24 bd4: e272 b.n 10bc if (*fmt != '%') { bd6: 68bb ldr r3, [r7, #8] bd8: 781b ldrb r3, [r3, #0] bda: 2b25 cmp r3, #37 ; 0x25 bdc: d006 beq.n bec *str++ = *fmt; bde: 68ba ldr r2, [r7, #8] be0: 6a7b ldr r3, [r7, #36] ; 0x24 be2: 1c59 adds r1, r3, #1 be4: 6279 str r1, [r7, #36] ; 0x24 be6: 7812 ldrb r2, [r2, #0] be8: 701a strb r2, [r3, #0] continue; bea: e264 b.n 10b6 } flags = 0; //process flags bec: 2300 movs r3, #0 bee: 63bb str r3, [r7, #56] ; 0x38 repeat: ++fmt; //this also skips first '%' bf0: 68bb ldr r3, [r7, #8] bf2: 3301 adds r3, #1 bf4: 60bb str r3, [r7, #8] switch (*fmt) { bf6: 68bb ldr r3, [r7, #8] bf8: 781b ldrb r3, [r3, #0] bfa: 3b20 subs r3, #32 bfc: 2b10 cmp r3, #16 bfe: d83e bhi.n c7e c00: a201 add r2, pc, #4 ; (adr r2, c08 ) c02: f852 f023 ldr.w pc, [r2, r3, lsl #2] c06: bf00 nop c08: 00000c61 .word 0x00000c61 c0c: 00000c7f .word 0x00000c7f c10: 00000c7f .word 0x00000c7f c14: 00000c6b .word 0x00000c6b c18: 00000c7f .word 0x00000c7f c1c: 00000c7f .word 0x00000c7f c20: 00000c7f .word 0x00000c7f c24: 00000c7f .word 0x00000c7f c28: 00000c7f .word 0x00000c7f c2c: 00000c7f .word 0x00000c7f c30: 00000c7f .word 0x00000c7f c34: 00000c57 .word 0x00000c57 c38: 00000c7f .word 0x00000c7f c3c: 00000c4d .word 0x00000c4d c40: 00000c7f .word 0x00000c7f c44: 00000c7f .word 0x00000c7f c48: 00000c75 .word 0x00000c75 case '-': flags |= LEFT; c4c: 6bbb ldr r3, [r7, #56] ; 0x38 c4e: f043 0310 orr.w r3, r3, #16 c52: 63bb str r3, [r7, #56] ; 0x38 goto repeat; c54: e7cc b.n bf0 case '+': flags |= PLUS; c56: 6bbb ldr r3, [r7, #56] ; 0x38 c58: f043 0304 orr.w r3, r3, #4 c5c: 63bb str r3, [r7, #56] ; 0x38 goto repeat; c5e: e7c7 b.n bf0 case ' ': flags |= SPACE; c60: 6bbb ldr r3, [r7, #56] ; 0x38 c62: f043 0308 orr.w r3, r3, #8 c66: 63bb str r3, [r7, #56] ; 0x38 goto repeat; c68: e7c2 b.n bf0 case '#': flags |= SPECIAL; c6a: 6bbb ldr r3, [r7, #56] ; 0x38 c6c: f043 0320 orr.w r3, r3, #32 c70: 63bb str r3, [r7, #56] ; 0x38 goto repeat; c72: e7bd b.n bf0 case '0': flags |= ZEROPAD; c74: 6bbb ldr r3, [r7, #56] ; 0x38 c76: f043 0301 orr.w r3, r3, #1 c7a: 63bb str r3, [r7, #56] ; 0x38 goto repeat; c7c: e7b8 b.n bf0 } field_width = -1; //get field width c7e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff c82: 633b str r3, [r7, #48] ; 0x30 if (isdigit(*fmt) != 0) { c84: 68bb ldr r3, [r7, #8] c86: 781b ldrb r3, [r3, #0] c88: 3301 adds r3, #1 c8a: 4ab9 ldr r2, [pc, #740] ; (f70 ) c8c: 4413 add r3, r2 c8e: 781b ldrb r3, [r3, #0] c90: f003 0304 and.w r3, r3, #4 c94: 2b00 cmp r3, #0 c96: d006 beq.n ca6 field_width = myskip_atoi(&fmt); c98: f107 0308 add.w r3, r7, #8 c9c: 4618 mov r0, r3 c9e: f7ff fe3f bl 920 ca2: 6338 str r0, [r7, #48] ; 0x30 ca4: e015 b.n cd2 } else if ('*' == *fmt) { ca6: 68bb ldr r3, [r7, #8] ca8: 781b ldrb r3, [r3, #0] caa: 2b2a cmp r3, #42 ; 0x2a cac: d111 bne.n cd2 ++fmt; cae: 68bb ldr r3, [r7, #8] cb0: 3301 adds r3, #1 cb2: 60bb str r3, [r7, #8] field_width = va_arg(args, int); //it's the next argument cb4: 687b ldr r3, [r7, #4] cb6: 1d1a adds r2, r3, #4 cb8: 607a str r2, [r7, #4] cba: 681b ldr r3, [r3, #0] cbc: 633b str r3, [r7, #48] ; 0x30 if (field_width < 0) { cbe: 6b3b ldr r3, [r7, #48] ; 0x30 cc0: 2b00 cmp r3, #0 cc2: da06 bge.n cd2 field_width = -field_width; cc4: 6b3b ldr r3, [r7, #48] ; 0x30 cc6: 425b negs r3, r3 cc8: 633b str r3, [r7, #48] ; 0x30 flags |= LEFT; cca: 6bbb ldr r3, [r7, #56] ; 0x38 ccc: f043 0310 orr.w r3, r3, #16 cd0: 63bb str r3, [r7, #56] ; 0x38 } } precision = -1; //get the precision cd2: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff cd6: 62fb str r3, [r7, #44] ; 0x2c if ('.' == *fmt) { cd8: 68bb ldr r3, [r7, #8] cda: 781b ldrb r3, [r3, #0] cdc: 2b2e cmp r3, #46 ; 0x2e cde: d124 bne.n d2a ++fmt; ce0: 68bb ldr r3, [r7, #8] ce2: 3301 adds r3, #1 ce4: 60bb str r3, [r7, #8] if (isdigit(*fmt)) { ce6: 68bb ldr r3, [r7, #8] ce8: 781b ldrb r3, [r3, #0] cea: 3301 adds r3, #1 cec: 4aa0 ldr r2, [pc, #640] ; (f70 ) cee: 4413 add r3, r2 cf0: 781b ldrb r3, [r3, #0] cf2: f003 0304 and.w r3, r3, #4 cf6: 2b00 cmp r3, #0 cf8: d006 beq.n d08 precision = myskip_atoi(&fmt); cfa: f107 0308 add.w r3, r7, #8 cfe: 4618 mov r0, r3 d00: f7ff fe0e bl 920 d04: 62f8 str r0, [r7, #44] ; 0x2c d06: e00b b.n d20 } else if ('*' == *fmt) { d08: 68bb ldr r3, [r7, #8] d0a: 781b ldrb r3, [r3, #0] d0c: 2b2a cmp r3, #42 ; 0x2a d0e: d107 bne.n d20 ++fmt; d10: 68bb ldr r3, [r7, #8] d12: 3301 adds r3, #1 d14: 60bb str r3, [r7, #8] precision = va_arg(args, int); //it's the next argument d16: 687b ldr r3, [r7, #4] d18: 1d1a adds r2, r3, #4 d1a: 607a str r2, [r7, #4] d1c: 681b ldr r3, [r3, #0] d1e: 62fb str r3, [r7, #44] ; 0x2c } if (precision < 0) { d20: 6afb ldr r3, [r7, #44] ; 0x2c d22: 2b00 cmp r3, #0 d24: da01 bge.n d2a precision = 0; d26: 2300 movs r3, #0 d28: 62fb str r3, [r7, #44] ; 0x2c } } qualifier = -1; //get the conversion qualifier d2a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff d2e: 62bb str r3, [r7, #40] ; 0x28 if (('h' == *fmt) || ('l' == *fmt) || ('q' == *fmt)) { d30: 68bb ldr r3, [r7, #8] d32: 781b ldrb r3, [r3, #0] d34: 2b68 cmp r3, #104 ; 0x68 d36: d007 beq.n d48 d38: 68bb ldr r3, [r7, #8] d3a: 781b ldrb r3, [r3, #0] d3c: 2b6c cmp r3, #108 ; 0x6c d3e: d003 beq.n d48 d40: 68bb ldr r3, [r7, #8] d42: 781b ldrb r3, [r3, #0] d44: 2b71 cmp r3, #113 ; 0x71 d46: d105 bne.n d54 qualifier = *fmt; d48: 68bb ldr r3, [r7, #8] d4a: 781b ldrb r3, [r3, #0] d4c: 62bb str r3, [r7, #40] ; 0x28 ++fmt; d4e: 68bb ldr r3, [r7, #8] d50: 3301 adds r3, #1 d52: 60bb str r3, [r7, #8] } base = 10; //default base d54: 230a movs r3, #10 d56: 637b str r3, [r7, #52] ; 0x34 switch (*fmt) { d58: 68bb ldr r3, [r7, #8] d5a: 781b ldrb r3, [r3, #0] d5c: 3b25 subs r3, #37 ; 0x25 d5e: 2b53 cmp r3, #83 ; 0x53 d60: f200 815e bhi.w 1020 d64: a201 add r2, pc, #4 ; (adr r2, d6c ) d66: f852 f023 ldr.w pc, [r2, r3, lsl #2] d6a: bf00 nop d6c: 00000ff7 .word 0x00000ff7 d70: 00001021 .word 0x00001021 d74: 00001021 .word 0x00001021 d78: 00001021 .word 0x00001021 d7c: 00001021 .word 0x00001021 d80: 00001021 .word 0x00001021 d84: 00001021 .word 0x00001021 d88: 00001021 .word 0x00001021 d8c: 00001021 .word 0x00001021 d90: 00001021 .word 0x00001021 d94: 00001021 .word 0x00001021 d98: 00001021 .word 0x00001021 d9c: 00001021 .word 0x00001021 da0: 00001021 .word 0x00001021 da4: 00001021 .word 0x00001021 da8: 00001021 .word 0x00001021 dac: 00001021 .word 0x00001021 db0: 00001021 .word 0x00001021 db4: 00001021 .word 0x00001021 db8: 00001021 .word 0x00001021 dbc: 00001021 .word 0x00001021 dc0: 00001021 .word 0x00001021 dc4: 00001021 .word 0x00001021 dc8: 00001021 .word 0x00001021 dcc: 00001021 .word 0x00001021 dd0: 00001021 .word 0x00001021 dd4: 00001021 .word 0x00001021 dd8: 00001021 .word 0x00001021 ddc: 00001021 .word 0x00001021 de0: 00001021 .word 0x00001021 de4: 00001021 .word 0x00001021 de8: 00001021 .word 0x00001021 dec: 00001021 .word 0x00001021 df0: 00001021 .word 0x00001021 df4: 00001021 .word 0x00001021 df8: 00001021 .word 0x00001021 dfc: 00001021 .word 0x00001021 e00: 00001021 .word 0x00001021 e04: 00001021 .word 0x00001021 e08: 00001021 .word 0x00001021 e0c: 00001021 .word 0x00001021 e10: 00001021 .word 0x00001021 e14: 00001021 .word 0x00001021 e18: 00001021 .word 0x00001021 e1c: 00001021 .word 0x00001021 e20: 00001021 .word 0x00001021 e24: 00001021 .word 0x00001021 e28: 00001021 .word 0x00001021 e2c: 00001021 .word 0x00001021 e30: 00001021 .word 0x00001021 e34: 00001021 .word 0x00001021 e38: 00001009 .word 0x00001009 e3c: 00001021 .word 0x00001021 e40: 00001021 .word 0x00001021 e44: 00001021 .word 0x00001021 e48: 00001021 .word 0x00001021 e4c: 00001021 .word 0x00001021 e50: 00001021 .word 0x00001021 e54: 00001021 .word 0x00001021 e58: 00001021 .word 0x00001021 e5c: 00001021 .word 0x00001021 e60: 00001021 .word 0x00001021 e64: 00000ebd .word 0x00000ebd e68: 00001017 .word 0x00001017 e6c: 00001021 .word 0x00001021 e70: 00001021 .word 0x00001021 e74: 00001021 .word 0x00001021 e78: 00001021 .word 0x00001021 e7c: 00001017 .word 0x00001017 e80: 00001021 .word 0x00001021 e84: 00001021 .word 0x00001021 e88: 00001021 .word 0x00001021 e8c: 00001021 .word 0x00001021 e90: 00000fc5 .word 0x00000fc5 e94: 00001003 .word 0x00001003 e98: 00000f91 .word 0x00000f91 e9c: 00001021 .word 0x00001021 ea0: 00001021 .word 0x00001021 ea4: 00000f0b .word 0x00000f0b ea8: 00001021 .word 0x00001021 eac: 00001049 .word 0x00001049 eb0: 00001021 .word 0x00001021 eb4: 00001021 .word 0x00001021 eb8: 00001011 .word 0x00001011 case 'c': { if (0 == (flags & LEFT)) { ebc: 6bbb ldr r3, [r7, #56] ; 0x38 ebe: f003 0310 and.w r3, r3, #16 ec2: 2b00 cmp r3, #0 ec4: d10b bne.n ede while (--field_width > 0) { ec6: e004 b.n ed2 *str++ = ' '; ec8: 6a7b ldr r3, [r7, #36] ; 0x24 eca: 1c5a adds r2, r3, #1 ecc: 627a str r2, [r7, #36] ; 0x24 ece: 2220 movs r2, #32 ed0: 701a strb r2, [r3, #0] while (--field_width > 0) { ed2: 6b3b ldr r3, [r7, #48] ; 0x30 ed4: 3b01 subs r3, #1 ed6: 633b str r3, [r7, #48] ; 0x30 ed8: 6b3b ldr r3, [r7, #48] ; 0x30 eda: 2b00 cmp r3, #0 edc: dcf4 bgt.n ec8 } } *str++ = (unsigned char) va_arg(args, int); ede: 687b ldr r3, [r7, #4] ee0: 1d1a adds r2, r3, #4 ee2: 607a str r2, [r7, #4] ee4: 6819 ldr r1, [r3, #0] ee6: 6a7b ldr r3, [r7, #36] ; 0x24 ee8: 1c5a adds r2, r3, #1 eea: 627a str r2, [r7, #36] ; 0x24 eec: b2ca uxtb r2, r1 eee: 701a strb r2, [r3, #0] while (--field_width > 0) { ef0: e004 b.n efc *str++ = ' '; ef2: 6a7b ldr r3, [r7, #36] ; 0x24 ef4: 1c5a adds r2, r3, #1 ef6: 627a str r2, [r7, #36] ; 0x24 ef8: 2220 movs r2, #32 efa: 701a strb r2, [r3, #0] while (--field_width > 0) { efc: 6b3b ldr r3, [r7, #48] ; 0x30 efe: 3b01 subs r3, #1 f00: 633b str r3, [r7, #48] ; 0x30 f02: 6b3b ldr r3, [r7, #48] ; 0x30 f04: 2b00 cmp r3, #0 f06: dcf4 bgt.n ef2 } continue; f08: e0d5 b.n 10b6 } case 's': { s = va_arg(args, char *); f0a: 687b ldr r3, [r7, #4] f0c: 1d1a adds r2, r3, #4 f0e: 607a str r2, [r7, #4] f10: 681b ldr r3, [r3, #0] f12: 623b str r3, [r7, #32] if (!s) { f14: 6a3b ldr r3, [r7, #32] f16: 2b00 cmp r3, #0 f18: d101 bne.n f1e s = ""; f1a: 4b16 ldr r3, [pc, #88] ; (f74 ) f1c: 623b str r3, [r7, #32] } len = mystrnlen(s, precision); f1e: 6af9 ldr r1, [r7, #44] ; 0x2c f20: 6a38 ldr r0, [r7, #32] f22: f7ff fce1 bl 8e8 f26: 61b8 str r0, [r7, #24] if (0 == (flags & LEFT)) { f28: 6bbb ldr r3, [r7, #56] ; 0x38 f2a: f003 0310 and.w r3, r3, #16 f2e: 2b00 cmp r3, #0 f30: d10b bne.n f4a while (len < field_width--) { f32: e004 b.n f3e *str++ = ' '; f34: 6a7b ldr r3, [r7, #36] ; 0x24 f36: 1c5a adds r2, r3, #1 f38: 627a str r2, [r7, #36] ; 0x24 f3a: 2220 movs r2, #32 f3c: 701a strb r2, [r3, #0] while (len < field_width--) { f3e: 6b3b ldr r3, [r7, #48] ; 0x30 f40: 1e5a subs r2, r3, #1 f42: 633a str r2, [r7, #48] ; 0x30 f44: 69ba ldr r2, [r7, #24] f46: 429a cmp r2, r3 f48: dbf4 blt.n f34 } } for (i = 0; i < len; ++i) { f4a: 2300 movs r3, #0 f4c: 63fb str r3, [r7, #60] ; 0x3c f4e: e00a b.n f66 *str++ = *s++; f50: 6a3a ldr r2, [r7, #32] f52: 1c53 adds r3, r2, #1 f54: 623b str r3, [r7, #32] f56: 6a7b ldr r3, [r7, #36] ; 0x24 f58: 1c59 adds r1, r3, #1 f5a: 6279 str r1, [r7, #36] ; 0x24 f5c: 7812 ldrb r2, [r2, #0] f5e: 701a strb r2, [r3, #0] for (i = 0; i < len; ++i) { f60: 6bfb ldr r3, [r7, #60] ; 0x3c f62: 3301 adds r3, #1 f64: 63fb str r3, [r7, #60] ; 0x3c f66: 6bfa ldr r2, [r7, #60] ; 0x3c f68: 69bb ldr r3, [r7, #24] f6a: 429a cmp r2, r3 f6c: dbf0 blt.n f50 } while (len < field_width--) { f6e: e008 b.n f82 f70: 00005aac .word 0x00005aac f74: 00005a7c .word 0x00005a7c *str++ = ' '; f78: 6a7b ldr r3, [r7, #36] ; 0x24 f7a: 1c5a adds r2, r3, #1 f7c: 627a str r2, [r7, #36] ; 0x24 f7e: 2220 movs r2, #32 f80: 701a strb r2, [r3, #0] while (len < field_width--) { f82: 6b3b ldr r3, [r7, #48] ; 0x30 f84: 1e5a subs r2, r3, #1 f86: 633a str r2, [r7, #48] ; 0x30 f88: 69ba ldr r2, [r7, #24] f8a: 429a cmp r2, r3 f8c: dbf4 blt.n f78 } continue; f8e: e092 b.n 10b6 } case 'p': { if (-1 == field_width) { f90: 6b3b ldr r3, [r7, #48] ; 0x30 f92: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff f96: d105 bne.n fa4 field_width = 2 * sizeof(void *); f98: 2308 movs r3, #8 f9a: 633b str r3, [r7, #48] ; 0x30 flags |= ZEROPAD; f9c: 6bbb ldr r3, [r7, #56] ; 0x38 f9e: f043 0301 orr.w r3, r3, #1 fa2: 63bb str r3, [r7, #56] ; 0x38 } str = mynumber(str, (unsigned long)va_arg(args, void *), 16, field_width, precision, flags); fa4: 687b ldr r3, [r7, #4] fa6: 1d1a adds r2, r3, #4 fa8: 607a str r2, [r7, #4] faa: 681b ldr r3, [r3, #0] fac: 4619 mov r1, r3 fae: 6bbb ldr r3, [r7, #56] ; 0x38 fb0: 9301 str r3, [sp, #4] fb2: 6afb ldr r3, [r7, #44] ; 0x2c fb4: 9300 str r3, [sp, #0] fb6: 6b3b ldr r3, [r7, #48] ; 0x30 fb8: 2210 movs r2, #16 fba: 6a78 ldr r0, [r7, #36] ; 0x24 fbc: f7ff fcda bl 974 fc0: 6278 str r0, [r7, #36] ; 0x24 continue; fc2: e078 b.n 10b6 } case 'n': { if ('l' == qualifier) { fc4: 6abb ldr r3, [r7, #40] ; 0x28 fc6: 2b6c cmp r3, #108 ; 0x6c fc8: d10a bne.n fe0 long * ip = va_arg(args, long *); fca: 687b ldr r3, [r7, #4] fcc: 1d1a adds r2, r3, #4 fce: 607a str r2, [r7, #4] fd0: 681b ldr r3, [r3, #0] fd2: 613b str r3, [r7, #16] *ip = (str - buf); fd4: 6a7a ldr r2, [r7, #36] ; 0x24 fd6: 68fb ldr r3, [r7, #12] fd8: 1ad2 subs r2, r2, r3 fda: 693b ldr r3, [r7, #16] fdc: 601a str r2, [r3, #0] } else { int * ip = va_arg(args, int *); *ip = (str - buf); } continue; fde: e06a b.n 10b6 int * ip = va_arg(args, int *); fe0: 687b ldr r3, [r7, #4] fe2: 1d1a adds r2, r3, #4 fe4: 607a str r2, [r7, #4] fe6: 681b ldr r3, [r3, #0] fe8: 617b str r3, [r7, #20] *ip = (str - buf); fea: 6a7a ldr r2, [r7, #36] ; 0x24 fec: 68fb ldr r3, [r7, #12] fee: 1ad2 subs r2, r2, r3 ff0: 697b ldr r3, [r7, #20] ff2: 601a str r2, [r3, #0] continue; ff4: e05f b.n 10b6 } case '%': { *str++ = '%'; ff6: 6a7b ldr r3, [r7, #36] ; 0x24 ff8: 1c5a adds r2, r3, #1 ffa: 627a str r2, [r7, #36] ; 0x24 ffc: 2225 movs r2, #37 ; 0x25 ffe: 701a strb r2, [r3, #0] continue; 1000: e059 b.n 10b6 } case 'o': { //integer number formats - set up the flags and "break" base = 8; 1002: 2308 movs r3, #8 1004: 637b str r3, [r7, #52] ; 0x34 break; 1006: e020 b.n 104a } case 'X': { flags |= LARGE; 1008: 6bbb ldr r3, [r7, #56] ; 0x38 100a: f043 0340 orr.w r3, r3, #64 ; 0x40 100e: 63bb str r3, [r7, #56] ; 0x38 } case 'x': { base = 16; 1010: 2310 movs r3, #16 1012: 637b str r3, [r7, #52] ; 0x34 break; 1014: e019 b.n 104a } case 'd': case 'i': { flags |= SIGN; 1016: 6bbb ldr r3, [r7, #56] ; 0x38 1018: f043 0302 orr.w r3, r3, #2 101c: 63bb str r3, [r7, #56] ; 0x38 } case 'u': { break; 101e: e013 b.n 1048 } default: { *str++ = '%'; 1020: 6a7b ldr r3, [r7, #36] ; 0x24 1022: 1c5a adds r2, r3, #1 1024: 627a str r2, [r7, #36] ; 0x24 1026: 2225 movs r2, #37 ; 0x25 1028: 701a strb r2, [r3, #0] if (0 == *fmt) { 102a: 68bb ldr r3, [r7, #8] 102c: 781b ldrb r3, [r3, #0] 102e: 2b00 cmp r3, #0 1030: d106 bne.n 1040 *str++ = *fmt; 1032: 68ba ldr r2, [r7, #8] 1034: 6a7b ldr r3, [r7, #36] ; 0x24 1036: 1c59 adds r1, r3, #1 1038: 6279 str r1, [r7, #36] ; 0x24 103a: 7812 ldrb r2, [r2, #0] 103c: 701a strb r2, [r3, #0] } else { --fmt; } continue; 103e: e03a b.n 10b6 --fmt; 1040: 68bb ldr r3, [r7, #8] 1042: 3b01 subs r3, #1 1044: 60bb str r3, [r7, #8] continue; 1046: e036 b.n 10b6 break; 1048: bf00 nop } } if ('l' == qualifier) { 104a: 6abb ldr r3, [r7, #40] ; 0x28 104c: 2b6c cmp r3, #108 ; 0x6c 104e: d105 bne.n 105c num = va_arg(args, unsigned long); 1050: 687b ldr r3, [r7, #4] 1052: 1d1a adds r2, r3, #4 1054: 607a str r2, [r7, #4] 1056: 681b ldr r3, [r3, #0] 1058: 61fb str r3, [r7, #28] 105a: e021 b.n 10a0 } else if ('h' == qualifier) { 105c: 6abb ldr r3, [r7, #40] ; 0x28 105e: 2b68 cmp r3, #104 ; 0x68 1060: d10e bne.n 1080 num = (unsigned short) va_arg(args, int); 1062: 687b ldr r3, [r7, #4] 1064: 1d1a adds r2, r3, #4 1066: 607a str r2, [r7, #4] 1068: 681b ldr r3, [r3, #0] 106a: b29b uxth r3, r3 106c: 61fb str r3, [r7, #28] if (0 == (flags & SIGN)) { 106e: 6bbb ldr r3, [r7, #56] ; 0x38 1070: f003 0302 and.w r3, r3, #2 1074: 2b00 cmp r3, #0 1076: d113 bne.n 10a0 num = (short) num; 1078: 69fb ldr r3, [r7, #28] 107a: b21b sxth r3, r3 107c: 61fb str r3, [r7, #28] 107e: e00f b.n 10a0 } } else if (0 == (flags & SIGN)) { 1080: 6bbb ldr r3, [r7, #56] ; 0x38 1082: f003 0302 and.w r3, r3, #2 1086: 2b00 cmp r3, #0 1088: d105 bne.n 1096 num = va_arg(args, int); 108a: 687b ldr r3, [r7, #4] 108c: 1d1a adds r2, r3, #4 108e: 607a str r2, [r7, #4] 1090: 681b ldr r3, [r3, #0] 1092: 61fb str r3, [r7, #28] 1094: e004 b.n 10a0 } else { num = va_arg(args, unsigned int); 1096: 687b ldr r3, [r7, #4] 1098: 1d1a adds r2, r3, #4 109a: 607a str r2, [r7, #4] 109c: 681b ldr r3, [r3, #0] 109e: 61fb str r3, [r7, #28] } str = mynumber(str, num, base, field_width, precision, flags); 10a0: 69f9 ldr r1, [r7, #28] 10a2: 6bbb ldr r3, [r7, #56] ; 0x38 10a4: 9301 str r3, [sp, #4] 10a6: 6afb ldr r3, [r7, #44] ; 0x2c 10a8: 9300 str r3, [sp, #0] 10aa: 6b3b ldr r3, [r7, #48] ; 0x30 10ac: 6b7a ldr r2, [r7, #52] ; 0x34 10ae: 6a78 ldr r0, [r7, #36] ; 0x24 10b0: f7ff fc60 bl 974 10b4: 6278 str r0, [r7, #36] ; 0x24 for (str = buf; *fmt; ++fmt) { 10b6: 68bb ldr r3, [r7, #8] 10b8: 3301 adds r3, #1 10ba: 60bb str r3, [r7, #8] 10bc: 68bb ldr r3, [r7, #8] 10be: 781b ldrb r3, [r3, #0] 10c0: 2b00 cmp r3, #0 10c2: f47f ad88 bne.w bd6 } *str = '\0'; 10c6: 6a7b ldr r3, [r7, #36] ; 0x24 10c8: 2200 movs r2, #0 10ca: 701a strb r2, [r3, #0] return str-buf; 10cc: 6a7a ldr r2, [r7, #36] ; 0x24 10ce: 68fb ldr r3, [r7, #12] 10d0: 1ad3 subs r3, r2, r3 } 10d2: 4618 mov r0, r3 10d4: 3740 adds r7, #64 ; 0x40 10d6: 46bd mov sp, r7 10d8: bd80 pop {r7, pc} 000010da : void myputc (const char c) { 10da: b580 push {r7, lr} 10dc: b082 sub sp, #8 10de: af00 add r7, sp, #0 10e0: 4603 mov r3, r0 10e2: 71fb strb r3, [r7, #7] if (c == '\n') 10e4: 79fb ldrb r3, [r7, #7] 10e6: 2b0a cmp r3, #10 10e8: d102 bne.n 10f0 usart_send_bytes('\r'); 10ea: 200d movs r0, #13 10ec: f7ff fbe2 bl 8b4 usart_send_bytes(c); 10f0: 79fb ldrb r3, [r7, #7] 10f2: 4618 mov r0, r3 10f4: f7ff fbde bl 8b4 } 10f8: bf00 nop 10fa: 3708 adds r7, #8 10fc: 46bd mov sp, r7 10fe: bd80 pop {r7, pc} 00001100 : void myputs (const unsigned char *s) { 1100: b580 push {r7, lr} 1102: b082 sub sp, #8 1104: af00 add r7, sp, #0 1106: 6078 str r0, [r7, #4] while (*s) { 1108: e006 b.n 1118 myputc (*s++); 110a: 687b ldr r3, [r7, #4] 110c: 1c5a adds r2, r3, #1 110e: 607a str r2, [r7, #4] 1110: 781b ldrb r3, [r3, #0] 1112: 4618 mov r0, r3 1114: f7ff ffe1 bl 10da while (*s) { 1118: 687b ldr r3, [r7, #4] 111a: 781b ldrb r3, [r3, #0] 111c: 2b00 cmp r3, #0 111e: d1f4 bne.n 110a } } 1120: bf00 nop 1122: bf00 nop 1124: 3708 adds r7, #8 1126: 46bd mov sp, r7 1128: bd80 pop {r7, pc} 0000112a : void myprintf (const char *fmt,...) { 112a: b40f push {r0, r1, r2, r3} 112c: b580 push {r7, lr} 112e: b0a2 sub sp, #136 ; 0x88 1130: af00 add r7, sp, #0 va_list args; char printbuffer[PBSIZE]; va_start(args, fmt); 1132: f107 0394 add.w r3, r7, #148 ; 0x94 1136: f8c7 3084 str.w r3, [r7, #132] ; 0x84 myvsprintf(printbuffer, fmt, args); 113a: 1d3b adds r3, r7, #4 113c: f8d7 2084 ldr.w r2, [r7, #132] ; 0x84 1140: f8d7 1090 ldr.w r1, [r7, #144] ; 0x90 1144: 4618 mov r0, r3 1146: f7ff fd3d bl bc4 va_end(args); myputs((const unsigned char *)printbuffer); // Print the string 114a: 1d3b adds r3, r7, #4 114c: 4618 mov r0, r3 114e: f7ff ffd7 bl 1100 } 1152: bf00 nop 1154: 3788 adds r7, #136 ; 0x88 1156: 46bd mov sp, r7 1158: e8bd 4080 ldmia.w sp!, {r7, lr} 115c: b004 add sp, #16 115e: 4770 bx lr 00001160 : * @brief Resets the RCC clock configuration to the default reset state. * @param None * @retval None */ void RCC_DeInit(void) { 1160: b480 push {r7} 1162: af00 add r7, sp, #0 /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; 1164: 4b13 ldr r3, [pc, #76] ; (11b4 ) 1166: 681b ldr r3, [r3, #0] 1168: 4a12 ldr r2, [pc, #72] ; (11b4 ) 116a: f043 0301 orr.w r3, r3, #1 116e: 6013 str r3, [r2, #0] /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; 1170: 4b10 ldr r3, [pc, #64] ; (11b4 ) 1172: 685a ldr r2, [r3, #4] 1174: 490f ldr r1, [pc, #60] ; (11b4 ) 1176: 4b10 ldr r3, [pc, #64] ; (11b8 ) 1178: 4013 ands r3, r2 117a: 604b str r3, [r1, #4] #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; 117c: 4b0d ldr r3, [pc, #52] ; (11b4 ) 117e: 681b ldr r3, [r3, #0] 1180: 4a0c ldr r2, [pc, #48] ; (11b4 ) 1182: f023 7384 bic.w r3, r3, #17301504 ; 0x1080000 1186: f423 3380 bic.w r3, r3, #65536 ; 0x10000 118a: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; 118c: 4b09 ldr r3, [pc, #36] ; (11b4 ) 118e: 681b ldr r3, [r3, #0] 1190: 4a08 ldr r2, [pc, #32] ; (11b4 ) 1192: f423 2380 bic.w r3, r3, #262144 ; 0x40000 1196: 6013 str r3, [r2, #0] /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; 1198: 4b06 ldr r3, [pc, #24] ; (11b4 ) 119a: 685b ldr r3, [r3, #4] 119c: 4a05 ldr r2, [pc, #20] ; (11b4 ) 119e: f423 03fe bic.w r3, r3, #8323072 ; 0x7f0000 11a2: 6053 str r3, [r2, #4] /* Reset CFGR2 register */ RCC->CFGR2 = 0x00000000; #else /* Disable all interrupts and clear pending bits */ RCC->CIR = 0x009F0000; 11a4: 4b03 ldr r3, [pc, #12] ; (11b4 ) 11a6: f44f 021f mov.w r2, #10420224 ; 0x9f0000 11aa: 609a str r2, [r3, #8] #endif /* STM32F10X_CL */ } 11ac: bf00 nop 11ae: 46bd mov sp, r7 11b0: bc80 pop {r7} 11b2: 4770 bx lr 11b4: 40021000 .word 0x40021000 11b8: f8ff0000 .word 0xf8ff0000 000011bc : * @arg RCC_HSE_ON: HSE oscillator ON * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock * @retval None */ void RCC_HSEConfig(uint32_t RCC_HSE) { 11bc: b480 push {r7} 11be: b083 sub sp, #12 11c0: af00 add r7, sp, #0 11c2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_HSE)); /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ /* Reset HSEON bit */ RCC->CR &= CR_HSEON_Reset; 11c4: 4b13 ldr r3, [pc, #76] ; (1214 ) 11c6: 681b ldr r3, [r3, #0] 11c8: 4a12 ldr r2, [pc, #72] ; (1214 ) 11ca: f423 3380 bic.w r3, r3, #65536 ; 0x10000 11ce: 6013 str r3, [r2, #0] /* Reset HSEBYP bit */ RCC->CR &= CR_HSEBYP_Reset; 11d0: 4b10 ldr r3, [pc, #64] ; (1214 ) 11d2: 681b ldr r3, [r3, #0] 11d4: 4a0f ldr r2, [pc, #60] ; (1214 ) 11d6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 11da: 6013 str r3, [r2, #0] /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ switch(RCC_HSE) 11dc: 687b ldr r3, [r7, #4] 11de: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 11e2: d004 beq.n 11ee 11e4: 687b ldr r3, [r7, #4] 11e6: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 11ea: d007 beq.n 11fc /* Set HSEBYP and HSEON bits */ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; break; default: break; 11ec: e00d b.n 120a RCC->CR |= CR_HSEON_Set; 11ee: 4b09 ldr r3, [pc, #36] ; (1214 ) 11f0: 681b ldr r3, [r3, #0] 11f2: 4a08 ldr r2, [pc, #32] ; (1214 ) 11f4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 11f8: 6013 str r3, [r2, #0] break; 11fa: e006 b.n 120a RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; 11fc: 4b05 ldr r3, [pc, #20] ; (1214 ) 11fe: 681b ldr r3, [r3, #0] 1200: 4a04 ldr r2, [pc, #16] ; (1214 ) 1202: f443 23a0 orr.w r3, r3, #327680 ; 0x50000 1206: 6013 str r3, [r2, #0] break; 1208: bf00 nop } } 120a: bf00 nop 120c: 370c adds r7, #12 120e: 46bd mov sp, r7 1210: bc80 pop {r7} 1212: 4770 bx lr 1214: 40021000 .word 0x40021000 00001218 : * @retval An ErrorStatus enumuration value: * - SUCCESS: HSE oscillator is stable and ready to use * - ERROR: HSE oscillator not yet ready */ ErrorStatus RCC_WaitForHSEStartUp(void) { 1218: b580 push {r7, lr} 121a: b082 sub sp, #8 121c: af00 add r7, sp, #0 __IO uint32_t StartUpCounter = 0; 121e: 2300 movs r3, #0 1220: 603b str r3, [r7, #0] ErrorStatus status = ERROR; 1222: 2300 movs r3, #0 1224: 71fb strb r3, [r7, #7] FlagStatus HSEStatus = RESET; 1226: 2300 movs r3, #0 1228: 71bb strb r3, [r7, #6] /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); 122a: 2031 movs r0, #49 ; 0x31 122c: f000 fb14 bl 1858 1230: 4603 mov r3, r0 1232: 71bb strb r3, [r7, #6] StartUpCounter++; 1234: 683b ldr r3, [r7, #0] 1236: 3301 adds r3, #1 1238: 603b str r3, [r7, #0] } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); 123a: 683b ldr r3, [r7, #0] 123c: f5b3 6fa0 cmp.w r3, #1280 ; 0x500 1240: d002 beq.n 1248 1242: 79bb ldrb r3, [r7, #6] 1244: 2b00 cmp r3, #0 1246: d0f0 beq.n 122a if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) 1248: 2031 movs r0, #49 ; 0x31 124a: f000 fb05 bl 1858 124e: 4603 mov r3, r0 1250: 2b00 cmp r3, #0 1252: d002 beq.n 125a { status = SUCCESS; 1254: 2301 movs r3, #1 1256: 71fb strb r3, [r7, #7] 1258: e001 b.n 125e } else { status = ERROR; 125a: 2300 movs r3, #0 125c: 71fb strb r3, [r7, #7] } return (status); 125e: 79fb ldrb r3, [r7, #7] } 1260: 4618 mov r0, r3 1262: 3708 adds r7, #8 1264: 46bd mov sp, r7 1266: bd80 pop {r7, pc} 00001268 : * @param HSICalibrationValue: specifies the calibration trimming value. * This parameter must be a number between 0 and 0x1F. * @retval None */ void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) { 1268: b480 push {r7} 126a: b085 sub sp, #20 126c: af00 add r7, sp, #0 126e: 4603 mov r3, r0 1270: 71fb strb r3, [r7, #7] uint32_t tmpreg = 0; 1272: 2300 movs r3, #0 1274: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); tmpreg = RCC->CR; 1276: 4b0a ldr r3, [pc, #40] ; (12a0 ) 1278: 681b ldr r3, [r3, #0] 127a: 60fb str r3, [r7, #12] /* Clear HSITRIM[4:0] bits */ tmpreg &= CR_HSITRIM_Mask; 127c: 68fb ldr r3, [r7, #12] 127e: f023 03f8 bic.w r3, r3, #248 ; 0xf8 1282: 60fb str r3, [r7, #12] /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ tmpreg |= (uint32_t)HSICalibrationValue << 3; 1284: 79fb ldrb r3, [r7, #7] 1286: 00db lsls r3, r3, #3 1288: 68fa ldr r2, [r7, #12] 128a: 4313 orrs r3, r2 128c: 60fb str r3, [r7, #12] /* Store the new value */ RCC->CR = tmpreg; 128e: 4a04 ldr r2, [pc, #16] ; (12a0 ) 1290: 68fb ldr r3, [r7, #12] 1292: 6013 str r3, [r2, #0] } 1294: bf00 nop 1296: 3714 adds r7, #20 1298: 46bd mov sp, r7 129a: bc80 pop {r7} 129c: 4770 bx lr 129e: bf00 nop 12a0: 40021000 .word 0x40021000 000012a4 : * @note HSI can not be stopped if it is used directly or through the PLL as system clock. * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_HSICmd(FunctionalState NewState) { 12a4: b480 push {r7} 12a6: b083 sub sp, #12 12a8: af00 add r7, sp, #0 12aa: 4603 mov r3, r0 12ac: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; 12ae: 4a04 ldr r2, [pc, #16] ; (12c0 ) 12b0: 79fb ldrb r3, [r7, #7] 12b2: 6013 str r3, [r2, #0] } 12b4: bf00 nop 12b6: 370c adds r7, #12 12b8: 46bd mov sp, r7 12ba: bc80 pop {r7} 12bc: 4770 bx lr 12be: bf00 nop 12c0: 42420000 .word 0x42420000 000012c4 : * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] * @retval None */ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) { 12c4: b480 push {r7} 12c6: b085 sub sp, #20 12c8: af00 add r7, sp, #0 12ca: 6078 str r0, [r7, #4] 12cc: 6039 str r1, [r7, #0] uint32_t tmpreg = 0; 12ce: 2300 movs r3, #0 12d0: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); tmpreg = RCC->CFGR; 12d2: 4b0a ldr r3, [pc, #40] ; (12fc ) 12d4: 685b ldr r3, [r3, #4] 12d6: 60fb str r3, [r7, #12] /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ tmpreg &= CFGR_PLL_Mask; 12d8: 68fb ldr r3, [r7, #12] 12da: f423 137c bic.w r3, r3, #4128768 ; 0x3f0000 12de: 60fb str r3, [r7, #12] /* Set the PLL configuration bits */ tmpreg |= RCC_PLLSource | RCC_PLLMul; 12e0: 687a ldr r2, [r7, #4] 12e2: 683b ldr r3, [r7, #0] 12e4: 4313 orrs r3, r2 12e6: 68fa ldr r2, [r7, #12] 12e8: 4313 orrs r3, r2 12ea: 60fb str r3, [r7, #12] /* Store the new value */ RCC->CFGR = tmpreg; 12ec: 4a03 ldr r2, [pc, #12] ; (12fc ) 12ee: 68fb ldr r3, [r7, #12] 12f0: 6053 str r3, [r2, #4] } 12f2: bf00 nop 12f4: 3714 adds r7, #20 12f6: 46bd mov sp, r7 12f8: bc80 pop {r7} 12fa: 4770 bx lr 12fc: 40021000 .word 0x40021000 00001300 : * @note The PLL can not be disabled if it is used as system clock. * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_PLLCmd(FunctionalState NewState) { 1300: b480 push {r7} 1302: b083 sub sp, #12 1304: af00 add r7, sp, #0 1306: 4603 mov r3, r0 1308: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; 130a: 4a04 ldr r2, [pc, #16] ; (131c ) 130c: 79fb ldrb r3, [r7, #7] 130e: 6013 str r3, [r2, #0] } 1310: bf00 nop 1312: 370c adds r7, #12 1314: 46bd mov sp, r7 1316: bc80 pop {r7} 1318: 4770 bx lr 131a: bf00 nop 131c: 42420060 .word 0x42420060 00001320 : * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock * @retval None */ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) { 1320: b480 push {r7} 1322: b085 sub sp, #20 1324: af00 add r7, sp, #0 1326: 6078 str r0, [r7, #4] uint32_t tmpreg = 0; 1328: 2300 movs r3, #0 132a: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); tmpreg = RCC->CFGR; 132c: 4b09 ldr r3, [pc, #36] ; (1354 ) 132e: 685b ldr r3, [r3, #4] 1330: 60fb str r3, [r7, #12] /* Clear SW[1:0] bits */ tmpreg &= CFGR_SW_Mask; 1332: 68fb ldr r3, [r7, #12] 1334: f023 0303 bic.w r3, r3, #3 1338: 60fb str r3, [r7, #12] /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ tmpreg |= RCC_SYSCLKSource; 133a: 68fa ldr r2, [r7, #12] 133c: 687b ldr r3, [r7, #4] 133e: 4313 orrs r3, r2 1340: 60fb str r3, [r7, #12] /* Store the new value */ RCC->CFGR = tmpreg; 1342: 4a04 ldr r2, [pc, #16] ; (1354 ) 1344: 68fb ldr r3, [r7, #12] 1346: 6053 str r3, [r2, #4] } 1348: bf00 nop 134a: 3714 adds r7, #20 134c: 46bd mov sp, r7 134e: bc80 pop {r7} 1350: 4770 bx lr 1352: bf00 nop 1354: 40021000 .word 0x40021000 00001358 : * - 0x00: HSI used as system clock * - 0x04: HSE used as system clock * - 0x08: PLL used as system clock */ uint8_t RCC_GetSYSCLKSource(void) { 1358: b480 push {r7} 135a: af00 add r7, sp, #0 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); 135c: 4b04 ldr r3, [pc, #16] ; (1370 ) 135e: 685b ldr r3, [r3, #4] 1360: b2db uxtb r3, r3 1362: f003 030c and.w r3, r3, #12 1366: b2db uxtb r3, r3 } 1368: 4618 mov r0, r3 136a: 46bd mov sp, r7 136c: bc80 pop {r7} 136e: 4770 bx lr 1370: 40021000 .word 0x40021000 00001374 : * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 * @retval None */ void RCC_HCLKConfig(uint32_t RCC_SYSCLK) { 1374: b480 push {r7} 1376: b085 sub sp, #20 1378: af00 add r7, sp, #0 137a: 6078 str r0, [r7, #4] uint32_t tmpreg = 0; 137c: 2300 movs r3, #0 137e: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_HCLK(RCC_SYSCLK)); tmpreg = RCC->CFGR; 1380: 4b09 ldr r3, [pc, #36] ; (13a8 ) 1382: 685b ldr r3, [r3, #4] 1384: 60fb str r3, [r7, #12] /* Clear HPRE[3:0] bits */ tmpreg &= CFGR_HPRE_Reset_Mask; 1386: 68fb ldr r3, [r7, #12] 1388: f023 03f0 bic.w r3, r3, #240 ; 0xf0 138c: 60fb str r3, [r7, #12] /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ tmpreg |= RCC_SYSCLK; 138e: 68fa ldr r2, [r7, #12] 1390: 687b ldr r3, [r7, #4] 1392: 4313 orrs r3, r2 1394: 60fb str r3, [r7, #12] /* Store the new value */ RCC->CFGR = tmpreg; 1396: 4a04 ldr r2, [pc, #16] ; (13a8 ) 1398: 68fb ldr r3, [r7, #12] 139a: 6053 str r3, [r2, #4] } 139c: bf00 nop 139e: 3714 adds r7, #20 13a0: 46bd mov sp, r7 13a2: bc80 pop {r7} 13a4: 4770 bx lr 13a6: bf00 nop 13a8: 40021000 .word 0x40021000 000013ac : * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 * @retval None */ void RCC_PCLK1Config(uint32_t RCC_HCLK) { 13ac: b480 push {r7} 13ae: b085 sub sp, #20 13b0: af00 add r7, sp, #0 13b2: 6078 str r0, [r7, #4] uint32_t tmpreg = 0; 13b4: 2300 movs r3, #0 13b6: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PCLK(RCC_HCLK)); tmpreg = RCC->CFGR; 13b8: 4b09 ldr r3, [pc, #36] ; (13e0 ) 13ba: 685b ldr r3, [r3, #4] 13bc: 60fb str r3, [r7, #12] /* Clear PPRE1[2:0] bits */ tmpreg &= CFGR_PPRE1_Reset_Mask; 13be: 68fb ldr r3, [r7, #12] 13c0: f423 63e0 bic.w r3, r3, #1792 ; 0x700 13c4: 60fb str r3, [r7, #12] /* Set PPRE1[2:0] bits according to RCC_HCLK value */ tmpreg |= RCC_HCLK; 13c6: 68fa ldr r2, [r7, #12] 13c8: 687b ldr r3, [r7, #4] 13ca: 4313 orrs r3, r2 13cc: 60fb str r3, [r7, #12] /* Store the new value */ RCC->CFGR = tmpreg; 13ce: 4a04 ldr r2, [pc, #16] ; (13e0 ) 13d0: 68fb ldr r3, [r7, #12] 13d2: 6053 str r3, [r2, #4] } 13d4: bf00 nop 13d6: 3714 adds r7, #20 13d8: 46bd mov sp, r7 13da: bc80 pop {r7} 13dc: 4770 bx lr 13de: bf00 nop 13e0: 40021000 .word 0x40021000 000013e4 : * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 * @retval None */ void RCC_PCLK2Config(uint32_t RCC_HCLK) { 13e4: b480 push {r7} 13e6: b085 sub sp, #20 13e8: af00 add r7, sp, #0 13ea: 6078 str r0, [r7, #4] uint32_t tmpreg = 0; 13ec: 2300 movs r3, #0 13ee: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_PCLK(RCC_HCLK)); tmpreg = RCC->CFGR; 13f0: 4b09 ldr r3, [pc, #36] ; (1418 ) 13f2: 685b ldr r3, [r3, #4] 13f4: 60fb str r3, [r7, #12] /* Clear PPRE2[2:0] bits */ tmpreg &= CFGR_PPRE2_Reset_Mask; 13f6: 68fb ldr r3, [r7, #12] 13f8: f423 5360 bic.w r3, r3, #14336 ; 0x3800 13fc: 60fb str r3, [r7, #12] /* Set PPRE2[2:0] bits according to RCC_HCLK value */ tmpreg |= RCC_HCLK << 3; 13fe: 687b ldr r3, [r7, #4] 1400: 00db lsls r3, r3, #3 1402: 68fa ldr r2, [r7, #12] 1404: 4313 orrs r3, r2 1406: 60fb str r3, [r7, #12] /* Store the new value */ RCC->CFGR = tmpreg; 1408: 4a03 ldr r2, [pc, #12] ; (1418 ) 140a: 68fb ldr r3, [r7, #12] 140c: 6053 str r3, [r2, #4] } 140e: bf00 nop 1410: 3714 adds r7, #20 1412: 46bd mov sp, r7 1414: bc80 pop {r7} 1416: 4770 bx lr 1418: 40021000 .word 0x40021000 0000141c : * @param NewState: new state of the specified RCC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) { 141c: b480 push {r7} 141e: b083 sub sp, #12 1420: af00 add r7, sp, #0 1422: 4603 mov r3, r0 1424: 460a mov r2, r1 1426: 71fb strb r3, [r7, #7] 1428: 4613 mov r3, r2 142a: 71bb strb r3, [r7, #6] /* Check the parameters */ assert_param(IS_RCC_IT(RCC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 142c: 79bb ldrb r3, [r7, #6] 142e: 2b00 cmp r3, #0 1430: d008 beq.n 1444 { /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; 1432: 4b0c ldr r3, [pc, #48] ; (1464 ) 1434: 781b ldrb r3, [r3, #0] 1436: b2da uxtb r2, r3 1438: 490a ldr r1, [pc, #40] ; (1464 ) 143a: 79fb ldrb r3, [r7, #7] 143c: 4313 orrs r3, r2 143e: b2db uxtb r3, r3 1440: 700b strb r3, [r1, #0] else { /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; } } 1442: e009 b.n 1458 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; 1444: 4b07 ldr r3, [pc, #28] ; (1464 ) 1446: 781b ldrb r3, [r3, #0] 1448: b2da uxtb r2, r3 144a: 79fb ldrb r3, [r7, #7] 144c: 43db mvns r3, r3 144e: b2db uxtb r3, r3 1450: 4904 ldr r1, [pc, #16] ; (1464 ) 1452: 4013 ands r3, r2 1454: b2db uxtb r3, r3 1456: 700b strb r3, [r1, #0] } 1458: bf00 nop 145a: 370c adds r7, #12 145c: 46bd mov sp, r7 145e: bc80 pop {r7} 1460: 4770 bx lr 1462: bf00 nop 1464: 40021009 .word 0x40021009 00001468 : * clock source * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source * @retval None */ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) { 1468: b480 push {r7} 146a: b083 sub sp, #12 146c: af00 add r7, sp, #0 146e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; 1470: 4a03 ldr r2, [pc, #12] ; (1480 ) 1472: 687b ldr r3, [r7, #4] 1474: 6013 str r3, [r2, #0] } 1476: bf00 nop 1478: 370c adds r7, #12 147a: 46bd mov sp, r7 147c: bc80 pop {r7} 147e: 4770 bx lr 1480: 424200d8 .word 0x424200d8 00001484 : * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 * @retval None */ void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) { 1484: b480 push {r7} 1486: b085 sub sp, #20 1488: af00 add r7, sp, #0 148a: 6078 str r0, [r7, #4] uint32_t tmpreg = 0; 148c: 2300 movs r3, #0 148e: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); tmpreg = RCC->CFGR; 1490: 4b09 ldr r3, [pc, #36] ; (14b8 ) 1492: 685b ldr r3, [r3, #4] 1494: 60fb str r3, [r7, #12] /* Clear ADCPRE[1:0] bits */ tmpreg &= CFGR_ADCPRE_Reset_Mask; 1496: 68fb ldr r3, [r7, #12] 1498: f423 4340 bic.w r3, r3, #49152 ; 0xc000 149c: 60fb str r3, [r7, #12] /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ tmpreg |= RCC_PCLK2; 149e: 68fa ldr r2, [r7, #12] 14a0: 687b ldr r3, [r7, #4] 14a2: 4313 orrs r3, r2 14a4: 60fb str r3, [r7, #12] /* Store the new value */ RCC->CFGR = tmpreg; 14a6: 4a04 ldr r2, [pc, #16] ; (14b8 ) 14a8: 68fb ldr r3, [r7, #12] 14aa: 6053 str r3, [r2, #4] } 14ac: bf00 nop 14ae: 3714 adds r7, #20 14b0: 46bd mov sp, r7 14b2: bc80 pop {r7} 14b4: 4770 bx lr 14b6: bf00 nop 14b8: 40021000 .word 0x40021000 000014bc : * @arg RCC_LSE_ON: LSE oscillator ON * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock * @retval None */ void RCC_LSEConfig(uint8_t RCC_LSE) { 14bc: b480 push {r7} 14be: b083 sub sp, #12 14c0: af00 add r7, sp, #0 14c2: 4603 mov r3, r0 14c4: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_LSE)); /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ /* Reset LSEON bit */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; 14c6: 4b0c ldr r3, [pc, #48] ; (14f8 ) 14c8: 2200 movs r2, #0 14ca: 701a strb r2, [r3, #0] /* Reset LSEBYP bit */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; 14cc: 4b0a ldr r3, [pc, #40] ; (14f8 ) 14ce: 2200 movs r2, #0 14d0: 701a strb r2, [r3, #0] /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ switch(RCC_LSE) 14d2: 79fb ldrb r3, [r7, #7] 14d4: 2b01 cmp r3, #1 14d6: d002 beq.n 14de 14d8: 2b04 cmp r3, #4 14da: d004 beq.n 14e6 /* Set LSEBYP and LSEON bits */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; break; default: break; 14dc: e007 b.n 14ee *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; 14de: 4b06 ldr r3, [pc, #24] ; (14f8 ) 14e0: 2201 movs r2, #1 14e2: 701a strb r2, [r3, #0] break; 14e4: e003 b.n 14ee *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; 14e6: 4b04 ldr r3, [pc, #16] ; (14f8 ) 14e8: 2205 movs r2, #5 14ea: 701a strb r2, [r3, #0] break; 14ec: bf00 nop } } 14ee: bf00 nop 14f0: 370c adds r7, #12 14f2: 46bd mov sp, r7 14f4: bc80 pop {r7} 14f6: 4770 bx lr 14f8: 40021020 .word 0x40021020 000014fc : * @note LSI can not be disabled if the IWDG is running. * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_LSICmd(FunctionalState NewState) { 14fc: b480 push {r7} 14fe: b083 sub sp, #12 1500: af00 add r7, sp, #0 1502: 4603 mov r3, r0 1504: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; 1506: 4a04 ldr r2, [pc, #16] ; (1518 ) 1508: 79fb ldrb r3, [r7, #7] 150a: 6013 str r3, [r2, #0] } 150c: bf00 nop 150e: 370c adds r7, #12 1510: 46bd mov sp, r7 1512: bc80 pop {r7} 1514: 4770 bx lr 1516: bf00 nop 1518: 42420480 .word 0x42420480 0000151c : * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock * @retval None */ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) { 151c: b480 push {r7} 151e: b083 sub sp, #12 1520: af00 add r7, sp, #0 1522: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); /* Select the RTC clock source */ RCC->BDCR |= RCC_RTCCLKSource; 1524: 4b05 ldr r3, [pc, #20] ; (153c ) 1526: 6a1a ldr r2, [r3, #32] 1528: 4904 ldr r1, [pc, #16] ; (153c ) 152a: 687b ldr r3, [r7, #4] 152c: 4313 orrs r3, r2 152e: 620b str r3, [r1, #32] } 1530: bf00 nop 1532: 370c adds r7, #12 1534: 46bd mov sp, r7 1536: bc80 pop {r7} 1538: 4770 bx lr 153a: bf00 nop 153c: 40021000 .word 0x40021000 00001540 : * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_RTCCLKCmd(FunctionalState NewState) { 1540: b480 push {r7} 1542: b083 sub sp, #12 1544: af00 add r7, sp, #0 1546: 4603 mov r3, r0 1548: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; 154a: 4a04 ldr r2, [pc, #16] ; (155c ) 154c: 79fb ldrb r3, [r7, #7] 154e: 6013 str r3, [r2, #0] } 1550: bf00 nop 1552: 370c adds r7, #12 1554: 46bd mov sp, r7 1556: bc80 pop {r7} 1558: 4770 bx lr 155a: bf00 nop 155c: 4242043c .word 0x4242043c 00001560 : * @note The result of this function could be not correct when using * fractional value for HSE crystal. * @retval None */ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) { 1560: b480 push {r7} 1562: b087 sub sp, #28 1564: af00 add r7, sp, #0 1566: 6078 str r0, [r7, #4] uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; 1568: 2300 movs r3, #0 156a: 617b str r3, [r7, #20] 156c: 2300 movs r3, #0 156e: 613b str r3, [r7, #16] 1570: 2300 movs r3, #0 1572: 60fb str r3, [r7, #12] 1574: 2300 movs r3, #0 1576: 60bb str r3, [r7, #8] #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) uint32_t prediv1factor = 0; #endif /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & CFGR_SWS_Mask; 1578: 4b4f ldr r3, [pc, #316] ; (16b8 ) 157a: 685b ldr r3, [r3, #4] 157c: f003 030c and.w r3, r3, #12 1580: 617b str r3, [r7, #20] switch (tmp) 1582: 697b ldr r3, [r7, #20] 1584: 2b08 cmp r3, #8 1586: d011 beq.n 15ac 1588: 697b ldr r3, [r7, #20] 158a: 2b08 cmp r3, #8 158c: d83a bhi.n 1604 158e: 697b ldr r3, [r7, #20] 1590: 2b00 cmp r3, #0 1592: d003 beq.n 159c 1594: 697b ldr r3, [r7, #20] 1596: 2b04 cmp r3, #4 1598: d004 beq.n 15a4 159a: e033 b.n 1604 { case 0x00: /* HSI used as system clock */ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; 159c: 687b ldr r3, [r7, #4] 159e: 4a47 ldr r2, [pc, #284] ; (16bc ) 15a0: 601a str r2, [r3, #0] break; 15a2: e033 b.n 160c case 0x04: /* HSE used as system clock */ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; 15a4: 687b ldr r3, [r7, #4] 15a6: 4a45 ldr r2, [pc, #276] ; (16bc ) 15a8: 601a str r2, [r3, #0] break; 15aa: e02f b.n 160c case 0x08: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & CFGR_PLLMull_Mask; 15ac: 4b42 ldr r3, [pc, #264] ; (16b8 ) 15ae: 685b ldr r3, [r3, #4] 15b0: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 15b4: 613b str r3, [r7, #16] pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; 15b6: 4b40 ldr r3, [pc, #256] ; (16b8 ) 15b8: 685b ldr r3, [r3, #4] 15ba: f403 3380 and.w r3, r3, #65536 ; 0x10000 15be: 60fb str r3, [r7, #12] #ifndef STM32F10X_CL pllmull = ( pllmull >> 18) + 2; 15c0: 693b ldr r3, [r7, #16] 15c2: 0c9b lsrs r3, r3, #18 15c4: 3302 adds r3, #2 15c6: 613b str r3, [r7, #16] if (pllsource == 0x00) 15c8: 68fb ldr r3, [r7, #12] 15ca: 2b00 cmp r3, #0 15cc: d106 bne.n 15dc {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; 15ce: 693b ldr r3, [r7, #16] 15d0: 4a3b ldr r2, [pc, #236] ; (16c0 ) 15d2: fb02 f203 mul.w r2, r2, r3 15d6: 687b ldr r3, [r7, #4] 15d8: 601a str r2, [r3, #0] pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } #endif /* STM32F10X_CL */ break; 15da: e017 b.n 160c if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) 15dc: 4b36 ldr r3, [pc, #216] ; (16b8 ) 15de: 685b ldr r3, [r3, #4] 15e0: f403 3300 and.w r3, r3, #131072 ; 0x20000 15e4: 2b00 cmp r3, #0 15e6: d006 beq.n 15f6 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; 15e8: 693b ldr r3, [r7, #16] 15ea: 4a35 ldr r2, [pc, #212] ; (16c0 ) 15ec: fb02 f203 mul.w r2, r2, r3 15f0: 687b ldr r3, [r7, #4] 15f2: 601a str r2, [r3, #0] break; 15f4: e00a b.n 160c RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; 15f6: 693b ldr r3, [r7, #16] 15f8: 4a30 ldr r2, [pc, #192] ; (16bc ) 15fa: fb02 f203 mul.w r2, r2, r3 15fe: 687b ldr r3, [r7, #4] 1600: 601a str r2, [r3, #0] break; 1602: e003 b.n 160c default: RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; 1604: 687b ldr r3, [r7, #4] 1606: 4a2d ldr r2, [pc, #180] ; (16bc ) 1608: 601a str r2, [r3, #0] break; 160a: bf00 nop } /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ /* Get HCLK prescaler */ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; 160c: 4b2a ldr r3, [pc, #168] ; (16b8 ) 160e: 685b ldr r3, [r3, #4] 1610: f003 03f0 and.w r3, r3, #240 ; 0xf0 1614: 617b str r3, [r7, #20] tmp = tmp >> 4; 1616: 697b ldr r3, [r7, #20] 1618: 091b lsrs r3, r3, #4 161a: 617b str r3, [r7, #20] presc = APBAHBPrescTable[tmp]; 161c: 4a29 ldr r2, [pc, #164] ; (16c4 ) 161e: 697b ldr r3, [r7, #20] 1620: 4413 add r3, r2 1622: 781b ldrb r3, [r3, #0] 1624: b2db uxtb r3, r3 1626: 60bb str r3, [r7, #8] /* HCLK clock frequency */ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; 1628: 687b ldr r3, [r7, #4] 162a: 681a ldr r2, [r3, #0] 162c: 68bb ldr r3, [r7, #8] 162e: 40da lsrs r2, r3 1630: 687b ldr r3, [r7, #4] 1632: 605a str r2, [r3, #4] /* Get PCLK1 prescaler */ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; 1634: 4b20 ldr r3, [pc, #128] ; (16b8 ) 1636: 685b ldr r3, [r3, #4] 1638: f403 63e0 and.w r3, r3, #1792 ; 0x700 163c: 617b str r3, [r7, #20] tmp = tmp >> 8; 163e: 697b ldr r3, [r7, #20] 1640: 0a1b lsrs r3, r3, #8 1642: 617b str r3, [r7, #20] presc = APBAHBPrescTable[tmp]; 1644: 4a1f ldr r2, [pc, #124] ; (16c4 ) 1646: 697b ldr r3, [r7, #20] 1648: 4413 add r3, r2 164a: 781b ldrb r3, [r3, #0] 164c: b2db uxtb r3, r3 164e: 60bb str r3, [r7, #8] /* PCLK1 clock frequency */ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; 1650: 687b ldr r3, [r7, #4] 1652: 685a ldr r2, [r3, #4] 1654: 68bb ldr r3, [r7, #8] 1656: 40da lsrs r2, r3 1658: 687b ldr r3, [r7, #4] 165a: 609a str r2, [r3, #8] /* Get PCLK2 prescaler */ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; 165c: 4b16 ldr r3, [pc, #88] ; (16b8 ) 165e: 685b ldr r3, [r3, #4] 1660: f403 5360 and.w r3, r3, #14336 ; 0x3800 1664: 617b str r3, [r7, #20] tmp = tmp >> 11; 1666: 697b ldr r3, [r7, #20] 1668: 0adb lsrs r3, r3, #11 166a: 617b str r3, [r7, #20] presc = APBAHBPrescTable[tmp]; 166c: 4a15 ldr r2, [pc, #84] ; (16c4 ) 166e: 697b ldr r3, [r7, #20] 1670: 4413 add r3, r2 1672: 781b ldrb r3, [r3, #0] 1674: b2db uxtb r3, r3 1676: 60bb str r3, [r7, #8] /* PCLK2 clock frequency */ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; 1678: 687b ldr r3, [r7, #4] 167a: 685a ldr r2, [r3, #4] 167c: 68bb ldr r3, [r7, #8] 167e: 40da lsrs r2, r3 1680: 687b ldr r3, [r7, #4] 1682: 60da str r2, [r3, #12] /* Get ADCCLK prescaler */ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; 1684: 4b0c ldr r3, [pc, #48] ; (16b8 ) 1686: 685b ldr r3, [r3, #4] 1688: f403 4340 and.w r3, r3, #49152 ; 0xc000 168c: 617b str r3, [r7, #20] tmp = tmp >> 14; 168e: 697b ldr r3, [r7, #20] 1690: 0b9b lsrs r3, r3, #14 1692: 617b str r3, [r7, #20] presc = ADCPrescTable[tmp]; 1694: 4a0c ldr r2, [pc, #48] ; (16c8 ) 1696: 697b ldr r3, [r7, #20] 1698: 4413 add r3, r2 169a: 781b ldrb r3, [r3, #0] 169c: b2db uxtb r3, r3 169e: 60bb str r3, [r7, #8] /* ADCCLK clock frequency */ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; 16a0: 687b ldr r3, [r7, #4] 16a2: 68da ldr r2, [r3, #12] 16a4: 68bb ldr r3, [r7, #8] 16a6: fbb2 f2f3 udiv r2, r2, r3 16aa: 687b ldr r3, [r7, #4] 16ac: 611a str r2, [r3, #16] } 16ae: bf00 nop 16b0: 371c adds r7, #28 16b2: 46bd mov sp, r7 16b4: bc80 pop {r7} 16b6: 4770 bx lr 16b8: 40021000 .word 0x40021000 16bc: 007a1200 .word 0x007a1200 16c0: 003d0900 .word 0x003d0900 16c4: 20000014 .word 0x20000014 16c8: 20000024 .word 0x20000024 000016cc : * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) { 16cc: b480 push {r7} 16ce: b083 sub sp, #12 16d0: af00 add r7, sp, #0 16d2: 6078 str r0, [r7, #4] 16d4: 460b mov r3, r1 16d6: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 16d8: 78fb ldrb r3, [r7, #3] 16da: 2b00 cmp r3, #0 16dc: d006 beq.n 16ec { RCC->AHBENR |= RCC_AHBPeriph; 16de: 4b09 ldr r3, [pc, #36] ; (1704 ) 16e0: 695a ldr r2, [r3, #20] 16e2: 4908 ldr r1, [pc, #32] ; (1704 ) 16e4: 687b ldr r3, [r7, #4] 16e6: 4313 orrs r3, r2 16e8: 614b str r3, [r1, #20] } else { RCC->AHBENR &= ~RCC_AHBPeriph; } } 16ea: e006 b.n 16fa RCC->AHBENR &= ~RCC_AHBPeriph; 16ec: 4b05 ldr r3, [pc, #20] ; (1704 ) 16ee: 695a ldr r2, [r3, #20] 16f0: 687b ldr r3, [r7, #4] 16f2: 43db mvns r3, r3 16f4: 4903 ldr r1, [pc, #12] ; (1704 ) 16f6: 4013 ands r3, r2 16f8: 614b str r3, [r1, #20] } 16fa: bf00 nop 16fc: 370c adds r7, #12 16fe: 46bd mov sp, r7 1700: bc80 pop {r7} 1702: 4770 bx lr 1704: 40021000 .word 0x40021000 00001708 : * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { 1708: b480 push {r7} 170a: b083 sub sp, #12 170c: af00 add r7, sp, #0 170e: 6078 str r0, [r7, #4] 1710: 460b mov r3, r1 1712: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 1714: 78fb ldrb r3, [r7, #3] 1716: 2b00 cmp r3, #0 1718: d006 beq.n 1728 { RCC->APB2ENR |= RCC_APB2Periph; 171a: 4b09 ldr r3, [pc, #36] ; (1740 ) 171c: 699a ldr r2, [r3, #24] 171e: 4908 ldr r1, [pc, #32] ; (1740 ) 1720: 687b ldr r3, [r7, #4] 1722: 4313 orrs r3, r2 1724: 618b str r3, [r1, #24] } else { RCC->APB2ENR &= ~RCC_APB2Periph; } } 1726: e006 b.n 1736 RCC->APB2ENR &= ~RCC_APB2Periph; 1728: 4b05 ldr r3, [pc, #20] ; (1740 ) 172a: 699a ldr r2, [r3, #24] 172c: 687b ldr r3, [r7, #4] 172e: 43db mvns r3, r3 1730: 4903 ldr r1, [pc, #12] ; (1740 ) 1732: 4013 ands r3, r2 1734: 618b str r3, [r1, #24] } 1736: bf00 nop 1738: 370c adds r7, #12 173a: 46bd mov sp, r7 173c: bc80 pop {r7} 173e: 4770 bx lr 1740: 40021000 .word 0x40021000 00001744 : * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { 1744: b480 push {r7} 1746: b083 sub sp, #12 1748: af00 add r7, sp, #0 174a: 6078 str r0, [r7, #4] 174c: 460b mov r3, r1 174e: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 1750: 78fb ldrb r3, [r7, #3] 1752: 2b00 cmp r3, #0 1754: d006 beq.n 1764 { RCC->APB1ENR |= RCC_APB1Periph; 1756: 4b09 ldr r3, [pc, #36] ; (177c ) 1758: 69da ldr r2, [r3, #28] 175a: 4908 ldr r1, [pc, #32] ; (177c ) 175c: 687b ldr r3, [r7, #4] 175e: 4313 orrs r3, r2 1760: 61cb str r3, [r1, #28] } else { RCC->APB1ENR &= ~RCC_APB1Periph; } } 1762: e006 b.n 1772 RCC->APB1ENR &= ~RCC_APB1Periph; 1764: 4b05 ldr r3, [pc, #20] ; (177c ) 1766: 69da ldr r2, [r3, #28] 1768: 687b ldr r3, [r7, #4] 176a: 43db mvns r3, r3 176c: 4903 ldr r1, [pc, #12] ; (177c ) 176e: 4013 ands r3, r2 1770: 61cb str r3, [r1, #28] } 1772: bf00 nop 1774: 370c adds r7, #12 1776: 46bd mov sp, r7 1778: bc80 pop {r7} 177a: 4770 bx lr 177c: 40021000 .word 0x40021000 00001780 : * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { 1780: b480 push {r7} 1782: b083 sub sp, #12 1784: af00 add r7, sp, #0 1786: 6078 str r0, [r7, #4] 1788: 460b mov r3, r1 178a: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 178c: 78fb ldrb r3, [r7, #3] 178e: 2b00 cmp r3, #0 1790: d006 beq.n 17a0 { RCC->APB2RSTR |= RCC_APB2Periph; 1792: 4b09 ldr r3, [pc, #36] ; (17b8 ) 1794: 68da ldr r2, [r3, #12] 1796: 4908 ldr r1, [pc, #32] ; (17b8 ) 1798: 687b ldr r3, [r7, #4] 179a: 4313 orrs r3, r2 179c: 60cb str r3, [r1, #12] } else { RCC->APB2RSTR &= ~RCC_APB2Periph; } } 179e: e006 b.n 17ae RCC->APB2RSTR &= ~RCC_APB2Periph; 17a0: 4b05 ldr r3, [pc, #20] ; (17b8 ) 17a2: 68da ldr r2, [r3, #12] 17a4: 687b ldr r3, [r7, #4] 17a6: 43db mvns r3, r3 17a8: 4903 ldr r1, [pc, #12] ; (17b8 ) 17aa: 4013 ands r3, r2 17ac: 60cb str r3, [r1, #12] } 17ae: bf00 nop 17b0: 370c adds r7, #12 17b2: 46bd mov sp, r7 17b4: bc80 pop {r7} 17b6: 4770 bx lr 17b8: 40021000 .word 0x40021000 000017bc : * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { 17bc: b480 push {r7} 17be: b083 sub sp, #12 17c0: af00 add r7, sp, #0 17c2: 6078 str r0, [r7, #4] 17c4: 460b mov r3, r1 17c6: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 17c8: 78fb ldrb r3, [r7, #3] 17ca: 2b00 cmp r3, #0 17cc: d006 beq.n 17dc { RCC->APB1RSTR |= RCC_APB1Periph; 17ce: 4b09 ldr r3, [pc, #36] ; (17f4 ) 17d0: 691a ldr r2, [r3, #16] 17d2: 4908 ldr r1, [pc, #32] ; (17f4 ) 17d4: 687b ldr r3, [r7, #4] 17d6: 4313 orrs r3, r2 17d8: 610b str r3, [r1, #16] } else { RCC->APB1RSTR &= ~RCC_APB1Periph; } } 17da: e006 b.n 17ea RCC->APB1RSTR &= ~RCC_APB1Periph; 17dc: 4b05 ldr r3, [pc, #20] ; (17f4 ) 17de: 691a ldr r2, [r3, #16] 17e0: 687b ldr r3, [r7, #4] 17e2: 43db mvns r3, r3 17e4: 4903 ldr r1, [pc, #12] ; (17f4 ) 17e6: 4013 ands r3, r2 17e8: 610b str r3, [r1, #16] } 17ea: bf00 nop 17ec: 370c adds r7, #12 17ee: 46bd mov sp, r7 17f0: bc80 pop {r7} 17f2: 4770 bx lr 17f4: 40021000 .word 0x40021000 000017f8 : * @param NewState: new state of the Backup domain reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_BackupResetCmd(FunctionalState NewState) { 17f8: b480 push {r7} 17fa: b083 sub sp, #12 17fc: af00 add r7, sp, #0 17fe: 4603 mov r3, r0 1800: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; 1802: 4a04 ldr r2, [pc, #16] ; (1814 ) 1804: 79fb ldrb r3, [r7, #7] 1806: 6013 str r3, [r2, #0] } 1808: bf00 nop 180a: 370c adds r7, #12 180c: 46bd mov sp, r7 180e: bc80 pop {r7} 1810: 4770 bx lr 1812: bf00 nop 1814: 42420440 .word 0x42420440 00001818 : * @param NewState: new state of the Clock Security System.. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_ClockSecuritySystemCmd(FunctionalState NewState) { 1818: b480 push {r7} 181a: b083 sub sp, #12 181c: af00 add r7, sp, #0 181e: 4603 mov r3, r0 1820: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; 1822: 4a04 ldr r2, [pc, #16] ; (1834 ) 1824: 79fb ldrb r3, [r7, #7] 1826: 6013 str r3, [r2, #0] } 1828: bf00 nop 182a: 370c adds r7, #12 182c: 46bd mov sp, r7 182e: bc80 pop {r7} 1830: 4770 bx lr 1832: bf00 nop 1834: 4242004c .word 0x4242004c 00001838 : * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected * * @retval None */ void RCC_MCOConfig(uint8_t RCC_MCO) { 1838: b480 push {r7} 183a: b083 sub sp, #12 183c: af00 add r7, sp, #0 183e: 4603 mov r3, r0 1840: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCO)); /* Perform Byte access to MCO bits to select the MCO source */ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; 1842: 4a04 ldr r2, [pc, #16] ; (1854 ) 1844: 79fb ldrb r3, [r7, #7] 1846: 7013 strb r3, [r2, #0] } 1848: bf00 nop 184a: 370c adds r7, #12 184c: 46bd mov sp, r7 184e: bc80 pop {r7} 1850: 4770 bx lr 1852: bf00 nop 1854: 40021007 .word 0x40021007 00001858 : * @arg RCC_FLAG_LPWRRST: Low Power reset * * @retval The new state of RCC_FLAG (SET or RESET). */ FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) { 1858: b480 push {r7} 185a: b087 sub sp, #28 185c: af00 add r7, sp, #0 185e: 4603 mov r3, r0 1860: 71fb strb r3, [r7, #7] uint32_t tmp = 0; 1862: 2300 movs r3, #0 1864: 60fb str r3, [r7, #12] uint32_t statusreg = 0; 1866: 2300 movs r3, #0 1868: 617b str r3, [r7, #20] FlagStatus bitstatus = RESET; 186a: 2300 movs r3, #0 186c: 74fb strb r3, [r7, #19] /* Check the parameters */ assert_param(IS_RCC_FLAG(RCC_FLAG)); /* Get the RCC register index */ tmp = RCC_FLAG >> 5; 186e: 79fb ldrb r3, [r7, #7] 1870: 095b lsrs r3, r3, #5 1872: b2db uxtb r3, r3 1874: 60fb str r3, [r7, #12] if (tmp == 1) /* The flag to check is in CR register */ 1876: 68fb ldr r3, [r7, #12] 1878: 2b01 cmp r3, #1 187a: d103 bne.n 1884 { statusreg = RCC->CR; 187c: 4b12 ldr r3, [pc, #72] ; (18c8 ) 187e: 681b ldr r3, [r3, #0] 1880: 617b str r3, [r7, #20] 1882: e009 b.n 1898 } else if (tmp == 2) /* The flag to check is in BDCR register */ 1884: 68fb ldr r3, [r7, #12] 1886: 2b02 cmp r3, #2 1888: d103 bne.n 1892 { statusreg = RCC->BDCR; 188a: 4b0f ldr r3, [pc, #60] ; (18c8 ) 188c: 6a1b ldr r3, [r3, #32] 188e: 617b str r3, [r7, #20] 1890: e002 b.n 1898 } else /* The flag to check is in CSR register */ { statusreg = RCC->CSR; 1892: 4b0d ldr r3, [pc, #52] ; (18c8 ) 1894: 6a5b ldr r3, [r3, #36] ; 0x24 1896: 617b str r3, [r7, #20] } /* Get the flag position */ tmp = RCC_FLAG & FLAG_Mask; 1898: 79fb ldrb r3, [r7, #7] 189a: f003 031f and.w r3, r3, #31 189e: 60fb str r3, [r7, #12] if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) 18a0: 697a ldr r2, [r7, #20] 18a2: 68fb ldr r3, [r7, #12] 18a4: fa22 f303 lsr.w r3, r2, r3 18a8: f003 0301 and.w r3, r3, #1 18ac: 2b00 cmp r3, #0 18ae: d002 beq.n 18b6 { bitstatus = SET; 18b0: 2301 movs r3, #1 18b2: 74fb strb r3, [r7, #19] 18b4: e001 b.n 18ba } else { bitstatus = RESET; 18b6: 2300 movs r3, #0 18b8: 74fb strb r3, [r7, #19] } /* Return the flag status */ return bitstatus; 18ba: 7cfb ldrb r3, [r7, #19] } 18bc: 4618 mov r0, r3 18be: 371c adds r7, #28 18c0: 46bd mov sp, r7 18c2: bc80 pop {r7} 18c4: 4770 bx lr 18c6: bf00 nop 18c8: 40021000 .word 0x40021000 000018cc : * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST * @param None * @retval None */ void RCC_ClearFlag(void) { 18cc: b480 push {r7} 18ce: af00 add r7, sp, #0 /* Set RMVF bit to clear the reset flags */ RCC->CSR |= CSR_RMVF_Set; 18d0: 4b04 ldr r3, [pc, #16] ; (18e4 ) 18d2: 6a5b ldr r3, [r3, #36] ; 0x24 18d4: 4a03 ldr r2, [pc, #12] ; (18e4 ) 18d6: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 18da: 6253 str r3, [r2, #36] ; 0x24 } 18dc: bf00 nop 18de: 46bd mov sp, r7 18e0: bc80 pop {r7} 18e2: 4770 bx lr 18e4: 40021000 .word 0x40021000 000018e8 : * @arg RCC_IT_CSS: Clock Security System interrupt * * @retval The new state of RCC_IT (SET or RESET). */ ITStatus RCC_GetITStatus(uint8_t RCC_IT) { 18e8: b480 push {r7} 18ea: b085 sub sp, #20 18ec: af00 add r7, sp, #0 18ee: 4603 mov r3, r0 18f0: 71fb strb r3, [r7, #7] ITStatus bitstatus = RESET; 18f2: 2300 movs r3, #0 18f4: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_RCC_GET_IT(RCC_IT)); /* Check the status of the specified RCC interrupt */ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) 18f6: 4b08 ldr r3, [pc, #32] ; (1918 ) 18f8: 689a ldr r2, [r3, #8] 18fa: 79fb ldrb r3, [r7, #7] 18fc: 4013 ands r3, r2 18fe: 2b00 cmp r3, #0 1900: d002 beq.n 1908 { bitstatus = SET; 1902: 2301 movs r3, #1 1904: 73fb strb r3, [r7, #15] 1906: e001 b.n 190c } else { bitstatus = RESET; 1908: 2300 movs r3, #0 190a: 73fb strb r3, [r7, #15] } /* Return the RCC_IT status */ return bitstatus; 190c: 7bfb ldrb r3, [r7, #15] } 190e: 4618 mov r0, r3 1910: 3714 adds r7, #20 1912: 46bd mov sp, r7 1914: bc80 pop {r7} 1916: 4770 bx lr 1918: 40021000 .word 0x40021000 0000191c : * * @arg RCC_IT_CSS: Clock Security System interrupt * @retval None */ void RCC_ClearITPendingBit(uint8_t RCC_IT) { 191c: b480 push {r7} 191e: b083 sub sp, #12 1920: af00 add r7, sp, #0 1922: 4603 mov r3, r0 1924: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_RCC_CLEAR_IT(RCC_IT)); /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits */ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; 1926: 4a04 ldr r2, [pc, #16] ; (1938 ) 1928: 79fb ldrb r3, [r7, #7] 192a: 7013 strb r3, [r2, #0] } 192c: bf00 nop 192e: 370c adds r7, #12 1930: 46bd mov sp, r7 1932: bc80 pop {r7} 1934: 4770 bx lr 1936: bf00 nop 1938: 4002100a .word 0x4002100a 0000193c : * @brief Deinitializes the GPIOx peripheral registers to their default reset values. * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. * @retval None */ void GPIO_DeInit(GPIO_TypeDef* GPIOx) { 193c: b580 push {r7, lr} 193e: b082 sub sp, #8 1940: af00 add r7, sp, #0 1942: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); if (GPIOx == GPIOA) 1944: 687b ldr r3, [r7, #4] 1946: 4a2f ldr r2, [pc, #188] ; (1a04 ) 1948: 4293 cmp r3, r2 194a: d108 bne.n 195e { RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); 194c: 2101 movs r1, #1 194e: 2004 movs r0, #4 1950: f7ff ff16 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); 1954: 2100 movs r1, #0 1956: 2004 movs r0, #4 1958: f7ff ff12 bl 1780 { RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); } } } 195c: e04e b.n 19fc else if (GPIOx == GPIOB) 195e: 687b ldr r3, [r7, #4] 1960: 4a29 ldr r2, [pc, #164] ; (1a08 ) 1962: 4293 cmp r3, r2 1964: d108 bne.n 1978 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); 1966: 2101 movs r1, #1 1968: 2008 movs r0, #8 196a: f7ff ff09 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); 196e: 2100 movs r1, #0 1970: 2008 movs r0, #8 1972: f7ff ff05 bl 1780 } 1976: e041 b.n 19fc else if (GPIOx == GPIOC) 1978: 687b ldr r3, [r7, #4] 197a: 4a24 ldr r2, [pc, #144] ; (1a0c ) 197c: 4293 cmp r3, r2 197e: d108 bne.n 1992 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); 1980: 2101 movs r1, #1 1982: 2010 movs r0, #16 1984: f7ff fefc bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); 1988: 2100 movs r1, #0 198a: 2010 movs r0, #16 198c: f7ff fef8 bl 1780 } 1990: e034 b.n 19fc else if (GPIOx == GPIOD) 1992: 687b ldr r3, [r7, #4] 1994: 4a1e ldr r2, [pc, #120] ; (1a10 ) 1996: 4293 cmp r3, r2 1998: d108 bne.n 19ac RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); 199a: 2101 movs r1, #1 199c: 2020 movs r0, #32 199e: f7ff feef bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); 19a2: 2100 movs r1, #0 19a4: 2020 movs r0, #32 19a6: f7ff feeb bl 1780 } 19aa: e027 b.n 19fc else if (GPIOx == GPIOE) 19ac: 687b ldr r3, [r7, #4] 19ae: 4a19 ldr r2, [pc, #100] ; (1a14 ) 19b0: 4293 cmp r3, r2 19b2: d108 bne.n 19c6 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); 19b4: 2101 movs r1, #1 19b6: 2040 movs r0, #64 ; 0x40 19b8: f7ff fee2 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); 19bc: 2100 movs r1, #0 19be: 2040 movs r0, #64 ; 0x40 19c0: f7ff fede bl 1780 } 19c4: e01a b.n 19fc else if (GPIOx == GPIOF) 19c6: 687b ldr r3, [r7, #4] 19c8: 4a13 ldr r2, [pc, #76] ; (1a18 ) 19ca: 4293 cmp r3, r2 19cc: d108 bne.n 19e0 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); 19ce: 2101 movs r1, #1 19d0: 2080 movs r0, #128 ; 0x80 19d2: f7ff fed5 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); 19d6: 2100 movs r1, #0 19d8: 2080 movs r0, #128 ; 0x80 19da: f7ff fed1 bl 1780 } 19de: e00d b.n 19fc if (GPIOx == GPIOG) 19e0: 687b ldr r3, [r7, #4] 19e2: 4a0e ldr r2, [pc, #56] ; (1a1c ) 19e4: 4293 cmp r3, r2 19e6: d109 bne.n 19fc RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); 19e8: 2101 movs r1, #1 19ea: f44f 7080 mov.w r0, #256 ; 0x100 19ee: f7ff fec7 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); 19f2: 2100 movs r1, #0 19f4: f44f 7080 mov.w r0, #256 ; 0x100 19f8: f7ff fec2 bl 1780 } 19fc: bf00 nop 19fe: 3708 adds r7, #8 1a00: 46bd mov sp, r7 1a02: bd80 pop {r7, pc} 1a04: 40010800 .word 0x40010800 1a08: 40010c00 .word 0x40010c00 1a0c: 40011000 .word 0x40011000 1a10: 40011400 .word 0x40011400 1a14: 40011800 .word 0x40011800 1a18: 40011c00 .word 0x40011c00 1a1c: 40012000 .word 0x40012000 00001a20 : * and EXTI configuration) registers to their default reset values. * @param None * @retval None */ void GPIO_AFIODeInit(void) { 1a20: b580 push {r7, lr} 1a22: af00 add r7, sp, #0 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); 1a24: 2101 movs r1, #1 1a26: 2001 movs r0, #1 1a28: f7ff feaa bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); 1a2c: 2100 movs r1, #0 1a2e: 2001 movs r0, #1 1a30: f7ff fea6 bl 1780 } 1a34: bf00 nop 1a36: bd80 pop {r7, pc} 00001a38 : * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that * contains the configuration information for the specified GPIO peripheral. * @retval None */ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) { 1a38: b480 push {r7} 1a3a: b089 sub sp, #36 ; 0x24 1a3c: af00 add r7, sp, #0 1a3e: 6078 str r0, [r7, #4] 1a40: 6039 str r1, [r7, #0] uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; 1a42: 2300 movs r3, #0 1a44: 61fb str r3, [r7, #28] 1a46: 2300 movs r3, #0 1a48: 613b str r3, [r7, #16] 1a4a: 2300 movs r3, #0 1a4c: 61bb str r3, [r7, #24] 1a4e: 2300 movs r3, #0 1a50: 60fb str r3, [r7, #12] uint32_t tmpreg = 0x00, pinmask = 0x00; 1a52: 2300 movs r3, #0 1a54: 617b str r3, [r7, #20] 1a56: 2300 movs r3, #0 1a58: 60bb str r3, [r7, #8] assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); /*---------------------------- GPIO Mode Configuration -----------------------*/ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); 1a5a: 683b ldr r3, [r7, #0] 1a5c: 78db ldrb r3, [r3, #3] 1a5e: f003 030f and.w r3, r3, #15 1a62: 61fb str r3, [r7, #28] if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) 1a64: 683b ldr r3, [r7, #0] 1a66: 78db ldrb r3, [r3, #3] 1a68: f003 0310 and.w r3, r3, #16 1a6c: 2b00 cmp r3, #0 1a6e: d005 beq.n 1a7c { /* Check the parameters */ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); /* Output mode */ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; 1a70: 683b ldr r3, [r7, #0] 1a72: 789b ldrb r3, [r3, #2] 1a74: 461a mov r2, r3 1a76: 69fb ldr r3, [r7, #28] 1a78: 4313 orrs r3, r2 1a7a: 61fb str r3, [r7, #28] } /*---------------------------- GPIO CRL Configuration ------------------------*/ /* Configure the eight low port pins */ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) 1a7c: 683b ldr r3, [r7, #0] 1a7e: 881b ldrh r3, [r3, #0] 1a80: b2db uxtb r3, r3 1a82: 2b00 cmp r3, #0 1a84: d044 beq.n 1b10 { tmpreg = GPIOx->CRL; 1a86: 687b ldr r3, [r7, #4] 1a88: 681b ldr r3, [r3, #0] 1a8a: 617b str r3, [r7, #20] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 1a8c: 2300 movs r3, #0 1a8e: 61bb str r3, [r7, #24] 1a90: e038 b.n 1b04 { pos = ((uint32_t)0x01) << pinpos; 1a92: 2201 movs r2, #1 1a94: 69bb ldr r3, [r7, #24] 1a96: fa02 f303 lsl.w r3, r2, r3 1a9a: 60fb str r3, [r7, #12] /* Get the port pins position */ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; 1a9c: 683b ldr r3, [r7, #0] 1a9e: 881b ldrh r3, [r3, #0] 1aa0: 461a mov r2, r3 1aa2: 68fb ldr r3, [r7, #12] 1aa4: 4013 ands r3, r2 1aa6: 613b str r3, [r7, #16] if (currentpin == pos) 1aa8: 693a ldr r2, [r7, #16] 1aaa: 68fb ldr r3, [r7, #12] 1aac: 429a cmp r2, r3 1aae: d126 bne.n 1afe { pos = pinpos << 2; 1ab0: 69bb ldr r3, [r7, #24] 1ab2: 009b lsls r3, r3, #2 1ab4: 60fb str r3, [r7, #12] /* Clear the corresponding low control register bits */ pinmask = ((uint32_t)0x0F) << pos; 1ab6: 220f movs r2, #15 1ab8: 68fb ldr r3, [r7, #12] 1aba: fa02 f303 lsl.w r3, r2, r3 1abe: 60bb str r3, [r7, #8] tmpreg &= ~pinmask; 1ac0: 68bb ldr r3, [r7, #8] 1ac2: 43db mvns r3, r3 1ac4: 697a ldr r2, [r7, #20] 1ac6: 4013 ands r3, r2 1ac8: 617b str r3, [r7, #20] /* Write the mode configuration in the corresponding bits */ tmpreg |= (currentmode << pos); 1aca: 69fa ldr r2, [r7, #28] 1acc: 68fb ldr r3, [r7, #12] 1ace: fa02 f303 lsl.w r3, r2, r3 1ad2: 697a ldr r2, [r7, #20] 1ad4: 4313 orrs r3, r2 1ad6: 617b str r3, [r7, #20] /* Reset the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 1ad8: 683b ldr r3, [r7, #0] 1ada: 78db ldrb r3, [r3, #3] 1adc: 2b28 cmp r3, #40 ; 0x28 1ade: d105 bne.n 1aec { GPIOx->BRR = (((uint32_t)0x01) << pinpos); 1ae0: 2201 movs r2, #1 1ae2: 69bb ldr r3, [r7, #24] 1ae4: 409a lsls r2, r3 1ae6: 687b ldr r3, [r7, #4] 1ae8: 615a str r2, [r3, #20] 1aea: e008 b.n 1afe } else { /* Set the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 1aec: 683b ldr r3, [r7, #0] 1aee: 78db ldrb r3, [r3, #3] 1af0: 2b48 cmp r3, #72 ; 0x48 1af2: d104 bne.n 1afe { GPIOx->BSRR = (((uint32_t)0x01) << pinpos); 1af4: 2201 movs r2, #1 1af6: 69bb ldr r3, [r7, #24] 1af8: 409a lsls r2, r3 1afa: 687b ldr r3, [r7, #4] 1afc: 611a str r2, [r3, #16] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 1afe: 69bb ldr r3, [r7, #24] 1b00: 3301 adds r3, #1 1b02: 61bb str r3, [r7, #24] 1b04: 69bb ldr r3, [r7, #24] 1b06: 2b07 cmp r3, #7 1b08: d9c3 bls.n 1a92 } } } } GPIOx->CRL = tmpreg; 1b0a: 687b ldr r3, [r7, #4] 1b0c: 697a ldr r2, [r7, #20] 1b0e: 601a str r2, [r3, #0] } /*---------------------------- GPIO CRH Configuration ------------------------*/ /* Configure the eight high port pins */ if (GPIO_InitStruct->GPIO_Pin > 0x00FF) 1b10: 683b ldr r3, [r7, #0] 1b12: 881b ldrh r3, [r3, #0] 1b14: 2bff cmp r3, #255 ; 0xff 1b16: d946 bls.n 1ba6 { tmpreg = GPIOx->CRH; 1b18: 687b ldr r3, [r7, #4] 1b1a: 685b ldr r3, [r3, #4] 1b1c: 617b str r3, [r7, #20] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 1b1e: 2300 movs r3, #0 1b20: 61bb str r3, [r7, #24] 1b22: e03a b.n 1b9a { pos = (((uint32_t)0x01) << (pinpos + 0x08)); 1b24: 69bb ldr r3, [r7, #24] 1b26: 3308 adds r3, #8 1b28: 2201 movs r2, #1 1b2a: fa02 f303 lsl.w r3, r2, r3 1b2e: 60fb str r3, [r7, #12] /* Get the port pins position */ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); 1b30: 683b ldr r3, [r7, #0] 1b32: 881b ldrh r3, [r3, #0] 1b34: 461a mov r2, r3 1b36: 68fb ldr r3, [r7, #12] 1b38: 4013 ands r3, r2 1b3a: 613b str r3, [r7, #16] if (currentpin == pos) 1b3c: 693a ldr r2, [r7, #16] 1b3e: 68fb ldr r3, [r7, #12] 1b40: 429a cmp r2, r3 1b42: d127 bne.n 1b94 { pos = pinpos << 2; 1b44: 69bb ldr r3, [r7, #24] 1b46: 009b lsls r3, r3, #2 1b48: 60fb str r3, [r7, #12] /* Clear the corresponding high control register bits */ pinmask = ((uint32_t)0x0F) << pos; 1b4a: 220f movs r2, #15 1b4c: 68fb ldr r3, [r7, #12] 1b4e: fa02 f303 lsl.w r3, r2, r3 1b52: 60bb str r3, [r7, #8] tmpreg &= ~pinmask; 1b54: 68bb ldr r3, [r7, #8] 1b56: 43db mvns r3, r3 1b58: 697a ldr r2, [r7, #20] 1b5a: 4013 ands r3, r2 1b5c: 617b str r3, [r7, #20] /* Write the mode configuration in the corresponding bits */ tmpreg |= (currentmode << pos); 1b5e: 69fa ldr r2, [r7, #28] 1b60: 68fb ldr r3, [r7, #12] 1b62: fa02 f303 lsl.w r3, r2, r3 1b66: 697a ldr r2, [r7, #20] 1b68: 4313 orrs r3, r2 1b6a: 617b str r3, [r7, #20] /* Reset the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) 1b6c: 683b ldr r3, [r7, #0] 1b6e: 78db ldrb r3, [r3, #3] 1b70: 2b28 cmp r3, #40 ; 0x28 1b72: d105 bne.n 1b80 { GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); 1b74: 69bb ldr r3, [r7, #24] 1b76: 3308 adds r3, #8 1b78: 2201 movs r2, #1 1b7a: 409a lsls r2, r3 1b7c: 687b ldr r3, [r7, #4] 1b7e: 615a str r2, [r3, #20] } /* Set the corresponding ODR bit */ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) 1b80: 683b ldr r3, [r7, #0] 1b82: 78db ldrb r3, [r3, #3] 1b84: 2b48 cmp r3, #72 ; 0x48 1b86: d105 bne.n 1b94 { GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); 1b88: 69bb ldr r3, [r7, #24] 1b8a: 3308 adds r3, #8 1b8c: 2201 movs r2, #1 1b8e: 409a lsls r2, r3 1b90: 687b ldr r3, [r7, #4] 1b92: 611a str r2, [r3, #16] for (pinpos = 0x00; pinpos < 0x08; pinpos++) 1b94: 69bb ldr r3, [r7, #24] 1b96: 3301 adds r3, #1 1b98: 61bb str r3, [r7, #24] 1b9a: 69bb ldr r3, [r7, #24] 1b9c: 2b07 cmp r3, #7 1b9e: d9c1 bls.n 1b24 } } } GPIOx->CRH = tmpreg; 1ba0: 687b ldr r3, [r7, #4] 1ba2: 697a ldr r2, [r7, #20] 1ba4: 605a str r2, [r3, #4] } } 1ba6: bf00 nop 1ba8: 3724 adds r7, #36 ; 0x24 1baa: 46bd mov sp, r7 1bac: bc80 pop {r7} 1bae: 4770 bx lr 00001bb0 : * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will * be initialized. * @retval None */ void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) { 1bb0: b480 push {r7} 1bb2: b083 sub sp, #12 1bb4: af00 add r7, sp, #0 1bb6: 6078 str r0, [r7, #4] /* Reset GPIO init structure parameters values */ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; 1bb8: 687b ldr r3, [r7, #4] 1bba: f64f 72ff movw r2, #65535 ; 0xffff 1bbe: 801a strh r2, [r3, #0] GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; 1bc0: 687b ldr r3, [r7, #4] 1bc2: 2202 movs r2, #2 1bc4: 709a strb r2, [r3, #2] GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; 1bc6: 687b ldr r3, [r7, #4] 1bc8: 2204 movs r2, #4 1bca: 70da strb r2, [r3, #3] } 1bcc: bf00 nop 1bce: 370c adds r7, #12 1bd0: 46bd mov sp, r7 1bd2: bc80 pop {r7} 1bd4: 4770 bx lr 00001bd6 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. */ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 1bd6: b480 push {r7} 1bd8: b085 sub sp, #20 1bda: af00 add r7, sp, #0 1bdc: 6078 str r0, [r7, #4] 1bde: 460b mov r3, r1 1be0: 807b strh r3, [r7, #2] uint8_t bitstatus = 0x00; 1be2: 2300 movs r3, #0 1be4: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) 1be6: 687b ldr r3, [r7, #4] 1be8: 689a ldr r2, [r3, #8] 1bea: 887b ldrh r3, [r7, #2] 1bec: 4013 ands r3, r2 1bee: 2b00 cmp r3, #0 1bf0: d002 beq.n 1bf8 { bitstatus = (uint8_t)Bit_SET; 1bf2: 2301 movs r3, #1 1bf4: 73fb strb r3, [r7, #15] 1bf6: e001 b.n 1bfc } else { bitstatus = (uint8_t)Bit_RESET; 1bf8: 2300 movs r3, #0 1bfa: 73fb strb r3, [r7, #15] } return bitstatus; 1bfc: 7bfb ldrb r3, [r7, #15] } 1bfe: 4618 mov r0, r3 1c00: 3714 adds r7, #20 1c02: 46bd mov sp, r7 1c04: bc80 pop {r7} 1c06: 4770 bx lr 00001c08 : * @brief Reads the specified GPIO input data port. * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. * @retval GPIO input data port value. */ uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) { 1c08: b480 push {r7} 1c0a: b083 sub sp, #12 1c0c: af00 add r7, sp, #0 1c0e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); return ((uint16_t)GPIOx->IDR); 1c10: 687b ldr r3, [r7, #4] 1c12: 689b ldr r3, [r3, #8] 1c14: b29b uxth r3, r3 } 1c16: 4618 mov r0, r3 1c18: 370c adds r7, #12 1c1a: 46bd mov sp, r7 1c1c: bc80 pop {r7} 1c1e: 4770 bx lr 00001c20 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_Pin_x where x can be (0..15). * @retval The output port pin value. */ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 1c20: b480 push {r7} 1c22: b085 sub sp, #20 1c24: af00 add r7, sp, #0 1c26: 6078 str r0, [r7, #4] 1c28: 460b mov r3, r1 1c2a: 807b strh r3, [r7, #2] uint8_t bitstatus = 0x00; 1c2c: 2300 movs r3, #0 1c2e: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) 1c30: 687b ldr r3, [r7, #4] 1c32: 68da ldr r2, [r3, #12] 1c34: 887b ldrh r3, [r7, #2] 1c36: 4013 ands r3, r2 1c38: 2b00 cmp r3, #0 1c3a: d002 beq.n 1c42 { bitstatus = (uint8_t)Bit_SET; 1c3c: 2301 movs r3, #1 1c3e: 73fb strb r3, [r7, #15] 1c40: e001 b.n 1c46 } else { bitstatus = (uint8_t)Bit_RESET; 1c42: 2300 movs r3, #0 1c44: 73fb strb r3, [r7, #15] } return bitstatus; 1c46: 7bfb ldrb r3, [r7, #15] } 1c48: 4618 mov r0, r3 1c4a: 3714 adds r7, #20 1c4c: 46bd mov sp, r7 1c4e: bc80 pop {r7} 1c50: 4770 bx lr 00001c52 : * @brief Reads the specified GPIO output data port. * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. * @retval GPIO output data port value. */ uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) { 1c52: b480 push {r7} 1c54: b083 sub sp, #12 1c56: af00 add r7, sp, #0 1c58: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); return ((uint16_t)GPIOx->ODR); 1c5a: 687b ldr r3, [r7, #4] 1c5c: 68db ldr r3, [r3, #12] 1c5e: b29b uxth r3, r3 } 1c60: 4618 mov r0, r3 1c62: 370c adds r7, #12 1c64: 46bd mov sp, r7 1c66: bc80 pop {r7} 1c68: 4770 bx lr 00001c6a : * @param GPIO_Pin: specifies the port bits to be written. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 1c6a: b480 push {r7} 1c6c: b083 sub sp, #12 1c6e: af00 add r7, sp, #0 1c70: 6078 str r0, [r7, #4] 1c72: 460b mov r3, r1 1c74: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BSRR = GPIO_Pin; 1c76: 887a ldrh r2, [r7, #2] 1c78: 687b ldr r3, [r7, #4] 1c7a: 611a str r2, [r3, #16] } 1c7c: bf00 nop 1c7e: 370c adds r7, #12 1c80: 46bd mov sp, r7 1c82: bc80 pop {r7} 1c84: 4770 bx lr 00001c86 : * @param GPIO_Pin: specifies the port bits to be written. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 1c86: b480 push {r7} 1c88: b083 sub sp, #12 1c8a: af00 add r7, sp, #0 1c8c: 6078 str r0, [r7, #4] 1c8e: 460b mov r3, r1 1c90: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BRR = GPIO_Pin; 1c92: 887a ldrh r2, [r7, #2] 1c94: 687b ldr r3, [r7, #4] 1c96: 615a str r2, [r3, #20] } 1c98: bf00 nop 1c9a: 370c adds r7, #12 1c9c: 46bd mov sp, r7 1c9e: bc80 pop {r7} 1ca0: 4770 bx lr 00001ca2 : * @arg Bit_RESET: to clear the port pin * @arg Bit_SET: to set the port pin * @retval None */ void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) { 1ca2: b480 push {r7} 1ca4: b083 sub sp, #12 1ca6: af00 add r7, sp, #0 1ca8: 6078 str r0, [r7, #4] 1caa: 460b mov r3, r1 1cac: 807b strh r3, [r7, #2] 1cae: 4613 mov r3, r2 1cb0: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_BIT_ACTION(BitVal)); if (BitVal != Bit_RESET) 1cb2: 787b ldrb r3, [r7, #1] 1cb4: 2b00 cmp r3, #0 1cb6: d003 beq.n 1cc0 { GPIOx->BSRR = GPIO_Pin; 1cb8: 887a ldrh r2, [r7, #2] 1cba: 687b ldr r3, [r7, #4] 1cbc: 611a str r2, [r3, #16] } else { GPIOx->BRR = GPIO_Pin; } } 1cbe: e002 b.n 1cc6 GPIOx->BRR = GPIO_Pin; 1cc0: 887a ldrh r2, [r7, #2] 1cc2: 687b ldr r3, [r7, #4] 1cc4: 615a str r2, [r3, #20] } 1cc6: bf00 nop 1cc8: 370c adds r7, #12 1cca: 46bd mov sp, r7 1ccc: bc80 pop {r7} 1cce: 4770 bx lr 00001cd0 : * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. * @param PortVal: specifies the value to be written to the port output data register. * @retval None */ void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) { 1cd0: b480 push {r7} 1cd2: b083 sub sp, #12 1cd4: af00 add r7, sp, #0 1cd6: 6078 str r0, [r7, #4] 1cd8: 460b mov r3, r1 1cda: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); GPIOx->ODR = PortVal; 1cdc: 887a ldrh r2, [r7, #2] 1cde: 687b ldr r3, [r7, #4] 1ce0: 60da str r2, [r3, #12] } 1ce2: bf00 nop 1ce4: 370c adds r7, #12 1ce6: 46bd mov sp, r7 1ce8: bc80 pop {r7} 1cea: 4770 bx lr 00001cec : * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 1cec: b480 push {r7} 1cee: b085 sub sp, #20 1cf0: af00 add r7, sp, #0 1cf2: 6078 str r0, [r7, #4] 1cf4: 460b mov r3, r1 1cf6: 807b strh r3, [r7, #2] uint32_t tmp = 0x00010000; 1cf8: f44f 3380 mov.w r3, #65536 ; 0x10000 1cfc: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); tmp |= GPIO_Pin; 1cfe: 887b ldrh r3, [r7, #2] 1d00: 68fa ldr r2, [r7, #12] 1d02: 4313 orrs r3, r2 1d04: 60fb str r3, [r7, #12] /* Set LCKK bit */ GPIOx->LCKR = tmp; 1d06: 687b ldr r3, [r7, #4] 1d08: 68fa ldr r2, [r7, #12] 1d0a: 619a str r2, [r3, #24] /* Reset LCKK bit */ GPIOx->LCKR = GPIO_Pin; 1d0c: 887a ldrh r2, [r7, #2] 1d0e: 687b ldr r3, [r7, #4] 1d10: 619a str r2, [r3, #24] /* Set LCKK bit */ GPIOx->LCKR = tmp; 1d12: 687b ldr r3, [r7, #4] 1d14: 68fa ldr r2, [r7, #12] 1d16: 619a str r2, [r3, #24] /* Read LCKK bit*/ tmp = GPIOx->LCKR; 1d18: 687b ldr r3, [r7, #4] 1d1a: 699b ldr r3, [r3, #24] 1d1c: 60fb str r3, [r7, #12] /* Read LCKK bit*/ tmp = GPIOx->LCKR; 1d1e: 687b ldr r3, [r7, #4] 1d20: 699b ldr r3, [r3, #24] 1d22: 60fb str r3, [r7, #12] } 1d24: bf00 nop 1d26: 3714 adds r7, #20 1d28: 46bd mov sp, r7 1d2a: bc80 pop {r7} 1d2c: 4770 bx lr 00001d2e : * @param GPIO_PinSource: specifies the pin for the Event output. * This parameter can be GPIO_PinSourcex where x can be (0..15). * @retval None */ void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) { 1d2e: b480 push {r7} 1d30: b085 sub sp, #20 1d32: af00 add r7, sp, #0 1d34: 4603 mov r3, r0 1d36: 460a mov r2, r1 1d38: 71fb strb r3, [r7, #7] 1d3a: 4613 mov r3, r2 1d3c: 71bb strb r3, [r7, #6] uint32_t tmpreg = 0x00; 1d3e: 2300 movs r3, #0 1d40: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); tmpreg = AFIO->EVCR; 1d42: 4b0c ldr r3, [pc, #48] ; (1d74 ) 1d44: 681b ldr r3, [r3, #0] 1d46: 60fb str r3, [r7, #12] /* Clear the PORT[6:4] and PIN[3:0] bits */ tmpreg &= EVCR_PORTPINCONFIG_MASK; 1d48: 68fa ldr r2, [r7, #12] 1d4a: f64f 7380 movw r3, #65408 ; 0xff80 1d4e: 4013 ands r3, r2 1d50: 60fb str r3, [r7, #12] tmpreg |= (uint32_t)GPIO_PortSource << 0x04; 1d52: 79fb ldrb r3, [r7, #7] 1d54: 011b lsls r3, r3, #4 1d56: 68fa ldr r2, [r7, #12] 1d58: 4313 orrs r3, r2 1d5a: 60fb str r3, [r7, #12] tmpreg |= GPIO_PinSource; 1d5c: 79bb ldrb r3, [r7, #6] 1d5e: 68fa ldr r2, [r7, #12] 1d60: 4313 orrs r3, r2 1d62: 60fb str r3, [r7, #12] AFIO->EVCR = tmpreg; 1d64: 4a03 ldr r2, [pc, #12] ; (1d74 ) 1d66: 68fb ldr r3, [r7, #12] 1d68: 6013 str r3, [r2, #0] } 1d6a: bf00 nop 1d6c: 3714 adds r7, #20 1d6e: 46bd mov sp, r7 1d70: bc80 pop {r7} 1d72: 4770 bx lr 1d74: 40010000 .word 0x40010000 00001d78 : * @param NewState: new state of the Event output. * This parameter can be: ENABLE or DISABLE. * @retval None */ void GPIO_EventOutputCmd(FunctionalState NewState) { 1d78: b480 push {r7} 1d7a: b083 sub sp, #12 1d7c: af00 add r7, sp, #0 1d7e: 4603 mov r3, r0 1d80: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; 1d82: 4a04 ldr r2, [pc, #16] ; (1d94 ) 1d84: 79fb ldrb r3, [r7, #7] 1d86: 6013 str r3, [r2, #0] } 1d88: bf00 nop 1d8a: 370c adds r7, #12 1d8c: 46bd mov sp, r7 1d8e: bc80 pop {r7} 1d90: 4770 bx lr 1d92: bf00 nop 1d94: 4220001c .word 0x4220001c 00001d98 : * @param NewState: new state of the port pin remapping. * This parameter can be: ENABLE or DISABLE. * @retval None */ void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) { 1d98: b480 push {r7} 1d9a: b087 sub sp, #28 1d9c: af00 add r7, sp, #0 1d9e: 6078 str r0, [r7, #4] 1da0: 460b mov r3, r1 1da2: 70fb strb r3, [r7, #3] uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; 1da4: 2300 movs r3, #0 1da6: 613b str r3, [r7, #16] 1da8: 2300 movs r3, #0 1daa: 60fb str r3, [r7, #12] 1dac: 2300 movs r3, #0 1dae: 617b str r3, [r7, #20] 1db0: 2300 movs r3, #0 1db2: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_GPIO_REMAP(GPIO_Remap)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if((GPIO_Remap & 0x80000000) == 0x80000000) 1db4: 687b ldr r3, [r7, #4] 1db6: 2b00 cmp r3, #0 1db8: da03 bge.n 1dc2 { tmpreg = AFIO->MAPR2; 1dba: 4b2e ldr r3, [pc, #184] ; (1e74 ) 1dbc: 69db ldr r3, [r3, #28] 1dbe: 617b str r3, [r7, #20] 1dc0: e002 b.n 1dc8 } else { tmpreg = AFIO->MAPR; 1dc2: 4b2c ldr r3, [pc, #176] ; (1e74 ) 1dc4: 685b ldr r3, [r3, #4] 1dc6: 617b str r3, [r7, #20] } tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; 1dc8: 687b ldr r3, [r7, #4] 1dca: 0c1b lsrs r3, r3, #16 1dcc: f003 030f and.w r3, r3, #15 1dd0: 60bb str r3, [r7, #8] tmp = GPIO_Remap & LSB_MASK; 1dd2: 687b ldr r3, [r7, #4] 1dd4: b29b uxth r3, r3 1dd6: 613b str r3, [r7, #16] if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) 1dd8: 687b ldr r3, [r7, #4] 1dda: f403 1340 and.w r3, r3, #3145728 ; 0x300000 1dde: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 1de2: d10a bne.n 1dfa { tmpreg &= DBGAFR_SWJCFG_MASK; 1de4: 697b ldr r3, [r7, #20] 1de6: f023 6370 bic.w r3, r3, #251658240 ; 0xf000000 1dea: 617b str r3, [r7, #20] AFIO->MAPR &= DBGAFR_SWJCFG_MASK; 1dec: 4b21 ldr r3, [pc, #132] ; (1e74 ) 1dee: 685b ldr r3, [r3, #4] 1df0: 4a20 ldr r2, [pc, #128] ; (1e74 ) 1df2: f023 6370 bic.w r3, r3, #251658240 ; 0xf000000 1df6: 6053 str r3, [r2, #4] 1df8: e021 b.n 1e3e } else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) 1dfa: 687b ldr r3, [r7, #4] 1dfc: f403 1380 and.w r3, r3, #1048576 ; 0x100000 1e00: 2b00 cmp r3, #0 1e02: d00e beq.n 1e22 { tmp1 = ((uint32_t)0x03) << tmpmask; 1e04: 2203 movs r2, #3 1e06: 68bb ldr r3, [r7, #8] 1e08: fa02 f303 lsl.w r3, r2, r3 1e0c: 60fb str r3, [r7, #12] tmpreg &= ~tmp1; 1e0e: 68fb ldr r3, [r7, #12] 1e10: 43db mvns r3, r3 1e12: 697a ldr r2, [r7, #20] 1e14: 4013 ands r3, r2 1e16: 617b str r3, [r7, #20] tmpreg |= ~DBGAFR_SWJCFG_MASK; 1e18: 697b ldr r3, [r7, #20] 1e1a: f043 6370 orr.w r3, r3, #251658240 ; 0xf000000 1e1e: 617b str r3, [r7, #20] 1e20: e00d b.n 1e3e } else { tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); 1e22: 687b ldr r3, [r7, #4] 1e24: 0d5b lsrs r3, r3, #21 1e26: 011b lsls r3, r3, #4 1e28: 693a ldr r2, [r7, #16] 1e2a: fa02 f303 lsl.w r3, r2, r3 1e2e: 43db mvns r3, r3 1e30: 697a ldr r2, [r7, #20] 1e32: 4013 ands r3, r2 1e34: 617b str r3, [r7, #20] tmpreg |= ~DBGAFR_SWJCFG_MASK; 1e36: 697b ldr r3, [r7, #20] 1e38: f043 6370 orr.w r3, r3, #251658240 ; 0xf000000 1e3c: 617b str r3, [r7, #20] } if (NewState != DISABLE) 1e3e: 78fb ldrb r3, [r7, #3] 1e40: 2b00 cmp r3, #0 1e42: d008 beq.n 1e56 { tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); 1e44: 687b ldr r3, [r7, #4] 1e46: 0d5b lsrs r3, r3, #21 1e48: 011b lsls r3, r3, #4 1e4a: 693a ldr r2, [r7, #16] 1e4c: fa02 f303 lsl.w r3, r2, r3 1e50: 697a ldr r2, [r7, #20] 1e52: 4313 orrs r3, r2 1e54: 617b str r3, [r7, #20] } if((GPIO_Remap & 0x80000000) == 0x80000000) 1e56: 687b ldr r3, [r7, #4] 1e58: 2b00 cmp r3, #0 1e5a: da03 bge.n 1e64 { AFIO->MAPR2 = tmpreg; 1e5c: 4a05 ldr r2, [pc, #20] ; (1e74 ) 1e5e: 697b ldr r3, [r7, #20] 1e60: 61d3 str r3, [r2, #28] } else { AFIO->MAPR = tmpreg; } } 1e62: e002 b.n 1e6a AFIO->MAPR = tmpreg; 1e64: 4a03 ldr r2, [pc, #12] ; (1e74 ) 1e66: 697b ldr r3, [r7, #20] 1e68: 6053 str r3, [r2, #4] } 1e6a: bf00 nop 1e6c: 371c adds r7, #28 1e6e: 46bd mov sp, r7 1e70: bc80 pop {r7} 1e72: 4770 bx lr 1e74: 40010000 .word 0x40010000 00001e78 : * @param GPIO_PinSource: specifies the EXTI line to be configured. * This parameter can be GPIO_PinSourcex where x can be (0..15). * @retval None */ void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) { 1e78: b480 push {r7} 1e7a: b085 sub sp, #20 1e7c: af00 add r7, sp, #0 1e7e: 4603 mov r3, r0 1e80: 460a mov r2, r1 1e82: 71fb strb r3, [r7, #7] 1e84: 4613 mov r3, r2 1e86: 71bb strb r3, [r7, #6] uint32_t tmp = 0x00; 1e88: 2300 movs r3, #0 1e8a: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); 1e8c: 79bb ldrb r3, [r7, #6] 1e8e: f003 0303 and.w r3, r3, #3 1e92: 009b lsls r3, r3, #2 1e94: 220f movs r2, #15 1e96: fa02 f303 lsl.w r3, r2, r3 1e9a: 60fb str r3, [r7, #12] AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; 1e9c: 4a15 ldr r2, [pc, #84] ; (1ef4 ) 1e9e: 79bb ldrb r3, [r7, #6] 1ea0: 089b lsrs r3, r3, #2 1ea2: b2db uxtb r3, r3 1ea4: 3302 adds r3, #2 1ea6: f852 2023 ldr.w r2, [r2, r3, lsl #2] 1eaa: 68fb ldr r3, [r7, #12] 1eac: 43db mvns r3, r3 1eae: 4811 ldr r0, [pc, #68] ; (1ef4 ) 1eb0: 79b9 ldrb r1, [r7, #6] 1eb2: 0889 lsrs r1, r1, #2 1eb4: b2c9 uxtb r1, r1 1eb6: 401a ands r2, r3 1eb8: 1c8b adds r3, r1, #2 1eba: f840 2023 str.w r2, [r0, r3, lsl #2] AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); 1ebe: 4a0d ldr r2, [pc, #52] ; (1ef4 ) 1ec0: 79bb ldrb r3, [r7, #6] 1ec2: 089b lsrs r3, r3, #2 1ec4: b2db uxtb r3, r3 1ec6: 3302 adds r3, #2 1ec8: f852 2023 ldr.w r2, [r2, r3, lsl #2] 1ecc: 79f9 ldrb r1, [r7, #7] 1ece: 79bb ldrb r3, [r7, #6] 1ed0: f003 0303 and.w r3, r3, #3 1ed4: 009b lsls r3, r3, #2 1ed6: fa01 f303 lsl.w r3, r1, r3 1eda: 4806 ldr r0, [pc, #24] ; (1ef4 ) 1edc: 79b9 ldrb r1, [r7, #6] 1ede: 0889 lsrs r1, r1, #2 1ee0: b2c9 uxtb r1, r1 1ee2: 431a orrs r2, r3 1ee4: 1c8b adds r3, r1, #2 1ee6: f840 2023 str.w r2, [r0, r3, lsl #2] } 1eea: bf00 nop 1eec: 3714 adds r7, #20 1eee: 46bd mov sp, r7 1ef0: bc80 pop {r7} 1ef2: 4770 bx lr 1ef4: 40010000 .word 0x40010000 00001ef8 : * @arg GPIO_ETH_MediaInterface_MII: MII mode * @arg GPIO_ETH_MediaInterface_RMII: RMII mode * @retval None */ void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) { 1ef8: b480 push {r7} 1efa: b083 sub sp, #12 1efc: af00 add r7, sp, #0 1efe: 6078 str r0, [r7, #4] assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); /* Configure MII_RMII selection bit */ *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; 1f00: 4a03 ldr r2, [pc, #12] ; (1f10 ) 1f02: 687b ldr r3, [r7, #4] 1f04: 6013 str r3, [r2, #0] } 1f06: bf00 nop 1f08: 370c adds r7, #12 1f0a: 46bd mov sp, r7 1f0c: bc80 pop {r7} 1f0e: 4770 bx lr 1f10: 422000dc .word 0x422000dc 00001f14 : * This parameter can be one of the following values: * USART1, USART2, USART3, UART4 or UART5. * @retval None */ void USART_DeInit(USART_TypeDef* USARTx) { 1f14: b580 push {r7, lr} 1f16: b082 sub sp, #8 1f18: af00 add r7, sp, #0 1f1a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); if (USARTx == USART1) 1f1c: 687b ldr r3, [r7, #4] 1f1e: 4a26 ldr r2, [pc, #152] ; (1fb8 ) 1f20: 4293 cmp r3, r2 1f22: d10a bne.n 1f3a { RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); 1f24: 2101 movs r1, #1 1f26: f44f 4080 mov.w r0, #16384 ; 0x4000 1f2a: f7ff fc29 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); 1f2e: 2100 movs r1, #0 1f30: f44f 4080 mov.w r0, #16384 ; 0x4000 1f34: f7ff fc24 bl 1780 { RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); } } } 1f38: e03a b.n 1fb0 else if (USARTx == USART2) 1f3a: 687b ldr r3, [r7, #4] 1f3c: 4a1f ldr r2, [pc, #124] ; (1fbc ) 1f3e: 4293 cmp r3, r2 1f40: d10a bne.n 1f58 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); 1f42: 2101 movs r1, #1 1f44: f44f 3000 mov.w r0, #131072 ; 0x20000 1f48: f7ff fc38 bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); 1f4c: 2100 movs r1, #0 1f4e: f44f 3000 mov.w r0, #131072 ; 0x20000 1f52: f7ff fc33 bl 17bc } 1f56: e02b b.n 1fb0 else if (USARTx == USART3) 1f58: 687b ldr r3, [r7, #4] 1f5a: 4a19 ldr r2, [pc, #100] ; (1fc0 ) 1f5c: 4293 cmp r3, r2 1f5e: d10a bne.n 1f76 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); 1f60: 2101 movs r1, #1 1f62: f44f 2080 mov.w r0, #262144 ; 0x40000 1f66: f7ff fc29 bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); 1f6a: 2100 movs r1, #0 1f6c: f44f 2080 mov.w r0, #262144 ; 0x40000 1f70: f7ff fc24 bl 17bc } 1f74: e01c b.n 1fb0 else if (USARTx == UART4) 1f76: 687b ldr r3, [r7, #4] 1f78: 4a12 ldr r2, [pc, #72] ; (1fc4 ) 1f7a: 4293 cmp r3, r2 1f7c: d10a bne.n 1f94 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); 1f7e: 2101 movs r1, #1 1f80: f44f 2000 mov.w r0, #524288 ; 0x80000 1f84: f7ff fc1a bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); 1f88: 2100 movs r1, #0 1f8a: f44f 2000 mov.w r0, #524288 ; 0x80000 1f8e: f7ff fc15 bl 17bc } 1f92: e00d b.n 1fb0 if (USARTx == UART5) 1f94: 687b ldr r3, [r7, #4] 1f96: 4a0c ldr r2, [pc, #48] ; (1fc8 ) 1f98: 4293 cmp r3, r2 1f9a: d109 bne.n 1fb0 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); 1f9c: 2101 movs r1, #1 1f9e: f44f 1080 mov.w r0, #1048576 ; 0x100000 1fa2: f7ff fc0b bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); 1fa6: 2100 movs r1, #0 1fa8: f44f 1080 mov.w r0, #1048576 ; 0x100000 1fac: f7ff fc06 bl 17bc } 1fb0: bf00 nop 1fb2: 3708 adds r7, #8 1fb4: 46bd mov sp, r7 1fb6: bd80 pop {r7, pc} 1fb8: 40013800 .word 0x40013800 1fbc: 40004400 .word 0x40004400 1fc0: 40004800 .word 0x40004800 1fc4: 40004c00 .word 0x40004c00 1fc8: 40005000 .word 0x40005000 00001fcc : * that contains the configuration information for the specified USART * peripheral. * @retval None */ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) { 1fcc: b580 push {r7, lr} 1fce: b08c sub sp, #48 ; 0x30 1fd0: af00 add r7, sp, #0 1fd2: 6078 str r0, [r7, #4] 1fd4: 6039 str r1, [r7, #0] uint32_t tmpreg = 0x00, apbclock = 0x00; 1fd6: 2300 movs r3, #0 1fd8: 62fb str r3, [r7, #44] ; 0x2c 1fda: 2300 movs r3, #0 1fdc: 62bb str r3, [r7, #40] ; 0x28 uint32_t integerdivider = 0x00; 1fde: 2300 movs r3, #0 1fe0: 627b str r3, [r7, #36] ; 0x24 uint32_t fractionaldivider = 0x00; 1fe2: 2300 movs r3, #0 1fe4: 623b str r3, [r7, #32] uint32_t usartxbase = 0; 1fe6: 2300 movs r3, #0 1fe8: 61fb str r3, [r7, #28] if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) { assert_param(IS_USART_123_PERIPH(USARTx)); } usartxbase = (uint32_t)USARTx; 1fea: 687b ldr r3, [r7, #4] 1fec: 61fb str r3, [r7, #28] /*---------------------------- USART CR2 Configuration -----------------------*/ tmpreg = USARTx->CR2; 1fee: 687b ldr r3, [r7, #4] 1ff0: 8a1b ldrh r3, [r3, #16] 1ff2: b29b uxth r3, r3 1ff4: 62fb str r3, [r7, #44] ; 0x2c /* Clear STOP[13:12] bits */ tmpreg &= CR2_STOP_CLEAR_Mask; 1ff6: 6afa ldr r2, [r7, #44] ; 0x2c 1ff8: f64c 73ff movw r3, #53247 ; 0xcfff 1ffc: 4013 ands r3, r2 1ffe: 62fb str r3, [r7, #44] ; 0x2c /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ /* Set STOP[13:12] bits according to USART_StopBits value */ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; 2000: 683b ldr r3, [r7, #0] 2002: 88db ldrh r3, [r3, #6] 2004: 461a mov r2, r3 2006: 6afb ldr r3, [r7, #44] ; 0x2c 2008: 4313 orrs r3, r2 200a: 62fb str r3, [r7, #44] ; 0x2c /* Write to USART CR2 */ USARTx->CR2 = (uint16_t)tmpreg; 200c: 6afb ldr r3, [r7, #44] ; 0x2c 200e: b29a uxth r2, r3 2010: 687b ldr r3, [r7, #4] 2012: 821a strh r2, [r3, #16] /*---------------------------- USART CR1 Configuration -----------------------*/ tmpreg = USARTx->CR1; 2014: 687b ldr r3, [r7, #4] 2016: 899b ldrh r3, [r3, #12] 2018: b29b uxth r3, r3 201a: 62fb str r3, [r7, #44] ; 0x2c /* Clear M, PCE, PS, TE and RE bits */ tmpreg &= CR1_CLEAR_Mask; 201c: 6afa ldr r2, [r7, #44] ; 0x2c 201e: f64e 13f3 movw r3, #59891 ; 0xe9f3 2022: 4013 ands r3, r2 2024: 62fb str r3, [r7, #44] ; 0x2c /* Configure the USART Word Length, Parity and mode ----------------------- */ /* Set the M bits according to USART_WordLength value */ /* Set PCE and PS bits according to USART_Parity value */ /* Set TE and RE bits according to USART_Mode value */ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | 2026: 683b ldr r3, [r7, #0] 2028: 889a ldrh r2, [r3, #4] 202a: 683b ldr r3, [r7, #0] 202c: 891b ldrh r3, [r3, #8] 202e: 4313 orrs r3, r2 2030: b29a uxth r2, r3 USART_InitStruct->USART_Mode; 2032: 683b ldr r3, [r7, #0] 2034: 895b ldrh r3, [r3, #10] tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | 2036: 4313 orrs r3, r2 2038: b29b uxth r3, r3 203a: 461a mov r2, r3 203c: 6afb ldr r3, [r7, #44] ; 0x2c 203e: 4313 orrs r3, r2 2040: 62fb str r3, [r7, #44] ; 0x2c /* Write to USART CR1 */ USARTx->CR1 = (uint16_t)tmpreg; 2042: 6afb ldr r3, [r7, #44] ; 0x2c 2044: b29a uxth r2, r3 2046: 687b ldr r3, [r7, #4] 2048: 819a strh r2, [r3, #12] /*---------------------------- USART CR3 Configuration -----------------------*/ tmpreg = USARTx->CR3; 204a: 687b ldr r3, [r7, #4] 204c: 8a9b ldrh r3, [r3, #20] 204e: b29b uxth r3, r3 2050: 62fb str r3, [r7, #44] ; 0x2c /* Clear CTSE and RTSE bits */ tmpreg &= CR3_CLEAR_Mask; 2052: 6afa ldr r2, [r7, #44] ; 0x2c 2054: f64f 43ff movw r3, #64767 ; 0xfcff 2058: 4013 ands r3, r2 205a: 62fb str r3, [r7, #44] ; 0x2c /* Configure the USART HFC -------------------------------------------------*/ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ tmpreg |= USART_InitStruct->USART_HardwareFlowControl; 205c: 683b ldr r3, [r7, #0] 205e: 899b ldrh r3, [r3, #12] 2060: 461a mov r2, r3 2062: 6afb ldr r3, [r7, #44] ; 0x2c 2064: 4313 orrs r3, r2 2066: 62fb str r3, [r7, #44] ; 0x2c /* Write to USART CR3 */ USARTx->CR3 = (uint16_t)tmpreg; 2068: 6afb ldr r3, [r7, #44] ; 0x2c 206a: b29a uxth r2, r3 206c: 687b ldr r3, [r7, #4] 206e: 829a strh r2, [r3, #20] /*---------------------------- USART BRR Configuration -----------------------*/ /* Configure the USART Baud Rate -------------------------------------------*/ RCC_GetClocksFreq(&RCC_ClocksStatus); 2070: f107 0308 add.w r3, r7, #8 2074: 4618 mov r0, r3 2076: f7ff fa73 bl 1560 if (usartxbase == USART1_BASE) 207a: 69fb ldr r3, [r7, #28] 207c: 4a2e ldr r2, [pc, #184] ; (2138 ) 207e: 4293 cmp r3, r2 2080: d102 bne.n 2088 { apbclock = RCC_ClocksStatus.PCLK2_Frequency; 2082: 697b ldr r3, [r7, #20] 2084: 62bb str r3, [r7, #40] ; 0x28 2086: e001 b.n 208c } else { apbclock = RCC_ClocksStatus.PCLK1_Frequency; 2088: 693b ldr r3, [r7, #16] 208a: 62bb str r3, [r7, #40] ; 0x28 } /* Determine the integer part */ if ((USARTx->CR1 & CR1_OVER8_Set) != 0) 208c: 687b ldr r3, [r7, #4] 208e: 899b ldrh r3, [r3, #12] 2090: b29b uxth r3, r3 2092: b21b sxth r3, r3 2094: 2b00 cmp r3, #0 2096: da0c bge.n 20b2 { /* Integer part computing in case Oversampling mode is 8 Samples */ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); 2098: 6aba ldr r2, [r7, #40] ; 0x28 209a: 4613 mov r3, r2 209c: 009b lsls r3, r3, #2 209e: 4413 add r3, r2 20a0: 009a lsls r2, r3, #2 20a2: 441a add r2, r3 20a4: 683b ldr r3, [r7, #0] 20a6: 681b ldr r3, [r3, #0] 20a8: 005b lsls r3, r3, #1 20aa: fbb2 f3f3 udiv r3, r2, r3 20ae: 627b str r3, [r7, #36] ; 0x24 20b0: e00b b.n 20ca } else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ { /* Integer part computing in case Oversampling mode is 16 Samples */ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); 20b2: 6aba ldr r2, [r7, #40] ; 0x28 20b4: 4613 mov r3, r2 20b6: 009b lsls r3, r3, #2 20b8: 4413 add r3, r2 20ba: 009a lsls r2, r3, #2 20bc: 441a add r2, r3 20be: 683b ldr r3, [r7, #0] 20c0: 681b ldr r3, [r3, #0] 20c2: 009b lsls r3, r3, #2 20c4: fbb2 f3f3 udiv r3, r2, r3 20c8: 627b str r3, [r7, #36] ; 0x24 } tmpreg = (integerdivider / 100) << 4; 20ca: 6a7b ldr r3, [r7, #36] ; 0x24 20cc: 4a1b ldr r2, [pc, #108] ; (213c ) 20ce: fba2 2303 umull r2, r3, r2, r3 20d2: 095b lsrs r3, r3, #5 20d4: 011b lsls r3, r3, #4 20d6: 62fb str r3, [r7, #44] ; 0x2c /* Determine the fractional part */ fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); 20d8: 6afb ldr r3, [r7, #44] ; 0x2c 20da: 091b lsrs r3, r3, #4 20dc: 2264 movs r2, #100 ; 0x64 20de: fb02 f303 mul.w r3, r2, r3 20e2: 6a7a ldr r2, [r7, #36] ; 0x24 20e4: 1ad3 subs r3, r2, r3 20e6: 623b str r3, [r7, #32] /* Implement the fractional part in the register */ if ((USARTx->CR1 & CR1_OVER8_Set) != 0) 20e8: 687b ldr r3, [r7, #4] 20ea: 899b ldrh r3, [r3, #12] 20ec: b29b uxth r3, r3 20ee: b21b sxth r3, r3 20f0: 2b00 cmp r3, #0 20f2: da0c bge.n 210e { tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); 20f4: 6a3b ldr r3, [r7, #32] 20f6: 00db lsls r3, r3, #3 20f8: 3332 adds r3, #50 ; 0x32 20fa: 4a10 ldr r2, [pc, #64] ; (213c ) 20fc: fba2 2303 umull r2, r3, r2, r3 2100: 095b lsrs r3, r3, #5 2102: f003 0307 and.w r3, r3, #7 2106: 6afa ldr r2, [r7, #44] ; 0x2c 2108: 4313 orrs r3, r2 210a: 62fb str r3, [r7, #44] ; 0x2c 210c: e00b b.n 2126 } else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ { tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); 210e: 6a3b ldr r3, [r7, #32] 2110: 011b lsls r3, r3, #4 2112: 3332 adds r3, #50 ; 0x32 2114: 4a09 ldr r2, [pc, #36] ; (213c ) 2116: fba2 2303 umull r2, r3, r2, r3 211a: 095b lsrs r3, r3, #5 211c: f003 030f and.w r3, r3, #15 2120: 6afa ldr r2, [r7, #44] ; 0x2c 2122: 4313 orrs r3, r2 2124: 62fb str r3, [r7, #44] ; 0x2c } /* Write to USART BRR */ USARTx->BRR = (uint16_t)tmpreg; 2126: 6afb ldr r3, [r7, #44] ; 0x2c 2128: b29a uxth r2, r3 212a: 687b ldr r3, [r7, #4] 212c: 811a strh r2, [r3, #8] } 212e: bf00 nop 2130: 3730 adds r7, #48 ; 0x30 2132: 46bd mov sp, r7 2134: bd80 pop {r7, pc} 2136: bf00 nop 2138: 40013800 .word 0x40013800 213c: 51eb851f .word 0x51eb851f 00002140 : * @param USART_InitStruct: pointer to a USART_InitTypeDef structure * which will be initialized. * @retval None */ void USART_StructInit(USART_InitTypeDef* USART_InitStruct) { 2140: b480 push {r7} 2142: b083 sub sp, #12 2144: af00 add r7, sp, #0 2146: 6078 str r0, [r7, #4] /* USART_InitStruct members default value */ USART_InitStruct->USART_BaudRate = 9600; 2148: 687b ldr r3, [r7, #4] 214a: f44f 5216 mov.w r2, #9600 ; 0x2580 214e: 601a str r2, [r3, #0] USART_InitStruct->USART_WordLength = USART_WordLength_8b; 2150: 687b ldr r3, [r7, #4] 2152: 2200 movs r2, #0 2154: 809a strh r2, [r3, #4] USART_InitStruct->USART_StopBits = USART_StopBits_1; 2156: 687b ldr r3, [r7, #4] 2158: 2200 movs r2, #0 215a: 80da strh r2, [r3, #6] USART_InitStruct->USART_Parity = USART_Parity_No ; 215c: 687b ldr r3, [r7, #4] 215e: 2200 movs r2, #0 2160: 811a strh r2, [r3, #8] USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 2162: 687b ldr r3, [r7, #4] 2164: 220c movs r2, #12 2166: 815a strh r2, [r3, #10] USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; 2168: 687b ldr r3, [r7, #4] 216a: 2200 movs r2, #0 216c: 819a strh r2, [r3, #12] } 216e: bf00 nop 2170: 370c adds r7, #12 2172: 46bd mov sp, r7 2174: bc80 pop {r7} 2176: 4770 bx lr 00002178 : * USART peripheral. * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. * @retval None */ void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) { 2178: b480 push {r7} 217a: b085 sub sp, #20 217c: af00 add r7, sp, #0 217e: 6078 str r0, [r7, #4] 2180: 6039 str r1, [r7, #0] uint32_t tmpreg = 0x00; 2182: 2300 movs r3, #0 2184: 60fb str r3, [r7, #12] assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); /*---------------------------- USART CR2 Configuration -----------------------*/ tmpreg = USARTx->CR2; 2186: 687b ldr r3, [r7, #4] 2188: 8a1b ldrh r3, [r3, #16] 218a: b29b uxth r3, r3 218c: 60fb str r3, [r7, #12] /* Clear CLKEN, CPOL, CPHA and LBCL bits */ tmpreg &= CR2_CLOCK_CLEAR_Mask; 218e: 68fa ldr r2, [r7, #12] 2190: f24f 03ff movw r3, #61695 ; 0xf0ff 2194: 4013 ands r3, r2 2196: 60fb str r3, [r7, #12] /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ /* Set CLKEN bit according to USART_Clock value */ /* Set CPOL bit according to USART_CPOL value */ /* Set CPHA bit according to USART_CPHA value */ /* Set LBCL bit according to USART_LastBit value */ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 2198: 683b ldr r3, [r7, #0] 219a: 881a ldrh r2, [r3, #0] 219c: 683b ldr r3, [r7, #0] 219e: 885b ldrh r3, [r3, #2] USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; 21a0: 4313 orrs r3, r2 21a2: b29a uxth r2, r3 21a4: 683b ldr r3, [r7, #0] 21a6: 889b ldrh r3, [r3, #4] 21a8: 4313 orrs r3, r2 21aa: b29a uxth r2, r3 21ac: 683b ldr r3, [r7, #0] 21ae: 88db ldrh r3, [r3, #6] 21b0: 4313 orrs r3, r2 21b2: b29b uxth r3, r3 21b4: 461a mov r2, r3 tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 21b6: 68fb ldr r3, [r7, #12] 21b8: 4313 orrs r3, r2 21ba: 60fb str r3, [r7, #12] /* Write to USART CR2 */ USARTx->CR2 = (uint16_t)tmpreg; 21bc: 68fb ldr r3, [r7, #12] 21be: b29a uxth r2, r3 21c0: 687b ldr r3, [r7, #4] 21c2: 821a strh r2, [r3, #16] } 21c4: bf00 nop 21c6: 3714 adds r7, #20 21c8: 46bd mov sp, r7 21ca: bc80 pop {r7} 21cc: 4770 bx lr 000021ce : * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef * structure which will be initialized. * @retval None */ void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) { 21ce: b480 push {r7} 21d0: b083 sub sp, #12 21d2: af00 add r7, sp, #0 21d4: 6078 str r0, [r7, #4] /* USART_ClockInitStruct members default value */ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; 21d6: 687b ldr r3, [r7, #4] 21d8: 2200 movs r2, #0 21da: 801a strh r2, [r3, #0] USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; 21dc: 687b ldr r3, [r7, #4] 21de: 2200 movs r2, #0 21e0: 805a strh r2, [r3, #2] USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; 21e2: 687b ldr r3, [r7, #4] 21e4: 2200 movs r2, #0 21e6: 809a strh r2, [r3, #4] USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; 21e8: 687b ldr r3, [r7, #4] 21ea: 2200 movs r2, #0 21ec: 80da strh r2, [r3, #6] } 21ee: bf00 nop 21f0: 370c adds r7, #12 21f2: 46bd mov sp, r7 21f4: bc80 pop {r7} 21f6: 4770 bx lr 000021f8 : * @param NewState: new state of the USARTx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) { 21f8: b480 push {r7} 21fa: b083 sub sp, #12 21fc: af00 add r7, sp, #0 21fe: 6078 str r0, [r7, #4] 2200: 460b mov r3, r1 2202: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2204: 78fb ldrb r3, [r7, #3] 2206: 2b00 cmp r3, #0 2208: d008 beq.n 221c { /* Enable the selected USART by setting the UE bit in the CR1 register */ USARTx->CR1 |= CR1_UE_Set; 220a: 687b ldr r3, [r7, #4] 220c: 899b ldrh r3, [r3, #12] 220e: b29b uxth r3, r3 2210: f443 5300 orr.w r3, r3, #8192 ; 0x2000 2214: b29a uxth r2, r3 2216: 687b ldr r3, [r7, #4] 2218: 819a strh r2, [r3, #12] else { /* Disable the selected USART by clearing the UE bit in the CR1 register */ USARTx->CR1 &= CR1_UE_Reset; } } 221a: e007 b.n 222c USARTx->CR1 &= CR1_UE_Reset; 221c: 687b ldr r3, [r7, #4] 221e: 899b ldrh r3, [r3, #12] 2220: b29b uxth r3, r3 2222: f423 5300 bic.w r3, r3, #8192 ; 0x2000 2226: b29a uxth r2, r3 2228: 687b ldr r3, [r7, #4] 222a: 819a strh r2, [r3, #12] } 222c: bf00 nop 222e: 370c adds r7, #12 2230: 46bd mov sp, r7 2232: bc80 pop {r7} 2234: 4770 bx lr 00002236 : * @param NewState: new state of the specified USARTx interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) { 2236: b480 push {r7} 2238: b087 sub sp, #28 223a: af00 add r7, sp, #0 223c: 6078 str r0, [r7, #4] 223e: 460b mov r3, r1 2240: 807b strh r3, [r7, #2] 2242: 4613 mov r3, r2 2244: 707b strb r3, [r7, #1] uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; 2246: 2300 movs r3, #0 2248: 613b str r3, [r7, #16] 224a: 2300 movs r3, #0 224c: 60fb str r3, [r7, #12] 224e: 2300 movs r3, #0 2250: 60bb str r3, [r7, #8] uint32_t usartxbase = 0x00; 2252: 2300 movs r3, #0 2254: 617b str r3, [r7, #20] if (USART_IT == USART_IT_CTS) { assert_param(IS_USART_123_PERIPH(USARTx)); } usartxbase = (uint32_t)USARTx; 2256: 687b ldr r3, [r7, #4] 2258: 617b str r3, [r7, #20] /* Get the USART register index */ usartreg = (((uint8_t)USART_IT) >> 0x05); 225a: 887b ldrh r3, [r7, #2] 225c: b2db uxtb r3, r3 225e: 095b lsrs r3, r3, #5 2260: b2db uxtb r3, r3 2262: 613b str r3, [r7, #16] /* Get the interrupt position */ itpos = USART_IT & IT_Mask; 2264: 887b ldrh r3, [r7, #2] 2266: f003 031f and.w r3, r3, #31 226a: 60fb str r3, [r7, #12] itmask = (((uint32_t)0x01) << itpos); 226c: 2201 movs r2, #1 226e: 68fb ldr r3, [r7, #12] 2270: fa02 f303 lsl.w r3, r2, r3 2274: 60bb str r3, [r7, #8] if (usartreg == 0x01) /* The IT is in CR1 register */ 2276: 693b ldr r3, [r7, #16] 2278: 2b01 cmp r3, #1 227a: d103 bne.n 2284 { usartxbase += 0x0C; 227c: 697b ldr r3, [r7, #20] 227e: 330c adds r3, #12 2280: 617b str r3, [r7, #20] 2282: e009 b.n 2298 } else if (usartreg == 0x02) /* The IT is in CR2 register */ 2284: 693b ldr r3, [r7, #16] 2286: 2b02 cmp r3, #2 2288: d103 bne.n 2292 { usartxbase += 0x10; 228a: 697b ldr r3, [r7, #20] 228c: 3310 adds r3, #16 228e: 617b str r3, [r7, #20] 2290: e002 b.n 2298 } else /* The IT is in CR3 register */ { usartxbase += 0x14; 2292: 697b ldr r3, [r7, #20] 2294: 3314 adds r3, #20 2296: 617b str r3, [r7, #20] } if (NewState != DISABLE) 2298: 787b ldrb r3, [r7, #1] 229a: 2b00 cmp r3, #0 229c: d006 beq.n 22ac { *(__IO uint32_t*)usartxbase |= itmask; 229e: 697b ldr r3, [r7, #20] 22a0: 6819 ldr r1, [r3, #0] 22a2: 697b ldr r3, [r7, #20] 22a4: 68ba ldr r2, [r7, #8] 22a6: 430a orrs r2, r1 22a8: 601a str r2, [r3, #0] } else { *(__IO uint32_t*)usartxbase &= ~itmask; } } 22aa: e006 b.n 22ba *(__IO uint32_t*)usartxbase &= ~itmask; 22ac: 697b ldr r3, [r7, #20] 22ae: 6819 ldr r1, [r3, #0] 22b0: 68bb ldr r3, [r7, #8] 22b2: 43da mvns r2, r3 22b4: 697b ldr r3, [r7, #20] 22b6: 400a ands r2, r1 22b8: 601a str r2, [r3, #0] } 22ba: bf00 nop 22bc: 371c adds r7, #28 22be: 46bd mov sp, r7 22c0: bc80 pop {r7} 22c2: 4770 bx lr 000022c4 : * @note The DMA mode is not available for UART5 except in the STM32 * High density value line devices(STM32F10X_HD_VL). * @retval None */ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) { 22c4: b480 push {r7} 22c6: b083 sub sp, #12 22c8: af00 add r7, sp, #0 22ca: 6078 str r0, [r7, #4] 22cc: 460b mov r3, r1 22ce: 807b strh r3, [r7, #2] 22d0: 4613 mov r3, r2 22d2: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_DMAREQ(USART_DMAReq)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 22d4: 787b ldrb r3, [r7, #1] 22d6: 2b00 cmp r3, #0 22d8: d008 beq.n 22ec { /* Enable the DMA transfer for selected requests by setting the DMAT and/or DMAR bits in the USART CR3 register */ USARTx->CR3 |= USART_DMAReq; 22da: 687b ldr r3, [r7, #4] 22dc: 8a9b ldrh r3, [r3, #20] 22de: b29a uxth r2, r3 22e0: 887b ldrh r3, [r7, #2] 22e2: 4313 orrs r3, r2 22e4: b29a uxth r2, r3 22e6: 687b ldr r3, [r7, #4] 22e8: 829a strh r2, [r3, #20] { /* Disable the DMA transfer for selected requests by clearing the DMAT and/or DMAR bits in the USART CR3 register */ USARTx->CR3 &= (uint16_t)~USART_DMAReq; } } 22ea: e009 b.n 2300 USARTx->CR3 &= (uint16_t)~USART_DMAReq; 22ec: 687b ldr r3, [r7, #4] 22ee: 8a9b ldrh r3, [r3, #20] 22f0: b29a uxth r2, r3 22f2: 887b ldrh r3, [r7, #2] 22f4: 43db mvns r3, r3 22f6: b29b uxth r3, r3 22f8: 4013 ands r3, r2 22fa: b29a uxth r2, r3 22fc: 687b ldr r3, [r7, #4] 22fe: 829a strh r2, [r3, #20] } 2300: bf00 nop 2302: 370c adds r7, #12 2304: 46bd mov sp, r7 2306: bc80 pop {r7} 2308: 4770 bx lr 0000230a : * USART1, USART2, USART3, UART4 or UART5. * @param USART_Address: Indicates the address of the USART node. * @retval None */ void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) { 230a: b480 push {r7} 230c: b083 sub sp, #12 230e: af00 add r7, sp, #0 2310: 6078 str r0, [r7, #4] 2312: 460b mov r3, r1 2314: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_ADDRESS(USART_Address)); /* Clear the USART address */ USARTx->CR2 &= CR2_Address_Mask; 2316: 687b ldr r3, [r7, #4] 2318: 8a1b ldrh r3, [r3, #16] 231a: b29b uxth r3, r3 231c: f023 030f bic.w r3, r3, #15 2320: b29a uxth r2, r3 2322: 687b ldr r3, [r7, #4] 2324: 821a strh r2, [r3, #16] /* Set the USART address node */ USARTx->CR2 |= USART_Address; 2326: 687b ldr r3, [r7, #4] 2328: 8a1b ldrh r3, [r3, #16] 232a: b29a uxth r2, r3 232c: 78fb ldrb r3, [r7, #3] 232e: b29b uxth r3, r3 2330: 4313 orrs r3, r2 2332: b29a uxth r2, r3 2334: 687b ldr r3, [r7, #4] 2336: 821a strh r2, [r3, #16] } 2338: bf00 nop 233a: 370c adds r7, #12 233c: 46bd mov sp, r7 233e: bc80 pop {r7} 2340: 4770 bx lr 00002342 : * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection * @arg USART_WakeUp_AddressMark: WakeUp by an address mark * @retval None */ void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) { 2342: b480 push {r7} 2344: b083 sub sp, #12 2346: af00 add r7, sp, #0 2348: 6078 str r0, [r7, #4] 234a: 460b mov r3, r1 234c: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_WAKEUP(USART_WakeUp)); USARTx->CR1 &= CR1_WAKE_Mask; 234e: 687b ldr r3, [r7, #4] 2350: 899b ldrh r3, [r3, #12] 2352: b29b uxth r3, r3 2354: f423 6300 bic.w r3, r3, #2048 ; 0x800 2358: b29a uxth r2, r3 235a: 687b ldr r3, [r7, #4] 235c: 819a strh r2, [r3, #12] USARTx->CR1 |= USART_WakeUp; 235e: 687b ldr r3, [r7, #4] 2360: 899b ldrh r3, [r3, #12] 2362: b29a uxth r2, r3 2364: 887b ldrh r3, [r7, #2] 2366: 4313 orrs r3, r2 2368: b29a uxth r2, r3 236a: 687b ldr r3, [r7, #4] 236c: 819a strh r2, [r3, #12] } 236e: bf00 nop 2370: 370c adds r7, #12 2372: 46bd mov sp, r7 2374: bc80 pop {r7} 2376: 4770 bx lr 00002378 : * @param NewState: new state of the USART mute mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) { 2378: b480 push {r7} 237a: b083 sub sp, #12 237c: af00 add r7, sp, #0 237e: 6078 str r0, [r7, #4] 2380: 460b mov r3, r1 2382: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2384: 78fb ldrb r3, [r7, #3] 2386: 2b00 cmp r3, #0 2388: d008 beq.n 239c { /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ USARTx->CR1 |= CR1_RWU_Set; 238a: 687b ldr r3, [r7, #4] 238c: 899b ldrh r3, [r3, #12] 238e: b29b uxth r3, r3 2390: f043 0302 orr.w r3, r3, #2 2394: b29a uxth r2, r3 2396: 687b ldr r3, [r7, #4] 2398: 819a strh r2, [r3, #12] else { /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ USARTx->CR1 &= CR1_RWU_Reset; } } 239a: e007 b.n 23ac USARTx->CR1 &= CR1_RWU_Reset; 239c: 687b ldr r3, [r7, #4] 239e: 899b ldrh r3, [r3, #12] 23a0: b29b uxth r3, r3 23a2: f023 0302 bic.w r3, r3, #2 23a6: b29a uxth r2, r3 23a8: 687b ldr r3, [r7, #4] 23aa: 819a strh r2, [r3, #12] } 23ac: bf00 nop 23ae: 370c adds r7, #12 23b0: 46bd mov sp, r7 23b2: bc80 pop {r7} 23b4: 4770 bx lr 000023b6 : * @arg USART_LINBreakDetectLength_10b: 10-bit break detection * @arg USART_LINBreakDetectLength_11b: 11-bit break detection * @retval None */ void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) { 23b6: b480 push {r7} 23b8: b083 sub sp, #12 23ba: af00 add r7, sp, #0 23bc: 6078 str r0, [r7, #4] 23be: 460b mov r3, r1 23c0: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); USARTx->CR2 &= CR2_LBDL_Mask; 23c2: 687b ldr r3, [r7, #4] 23c4: 8a1b ldrh r3, [r3, #16] 23c6: b29b uxth r3, r3 23c8: f023 0320 bic.w r3, r3, #32 23cc: b29a uxth r2, r3 23ce: 687b ldr r3, [r7, #4] 23d0: 821a strh r2, [r3, #16] USARTx->CR2 |= USART_LINBreakDetectLength; 23d2: 687b ldr r3, [r7, #4] 23d4: 8a1b ldrh r3, [r3, #16] 23d6: b29a uxth r2, r3 23d8: 887b ldrh r3, [r7, #2] 23da: 4313 orrs r3, r2 23dc: b29a uxth r2, r3 23de: 687b ldr r3, [r7, #4] 23e0: 821a strh r2, [r3, #16] } 23e2: bf00 nop 23e4: 370c adds r7, #12 23e6: 46bd mov sp, r7 23e8: bc80 pop {r7} 23ea: 4770 bx lr 000023ec : * @param NewState: new state of the USART LIN mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) { 23ec: b480 push {r7} 23ee: b083 sub sp, #12 23f0: af00 add r7, sp, #0 23f2: 6078 str r0, [r7, #4] 23f4: 460b mov r3, r1 23f6: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 23f8: 78fb ldrb r3, [r7, #3] 23fa: 2b00 cmp r3, #0 23fc: d008 beq.n 2410 { /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ USARTx->CR2 |= CR2_LINEN_Set; 23fe: 687b ldr r3, [r7, #4] 2400: 8a1b ldrh r3, [r3, #16] 2402: b29b uxth r3, r3 2404: f443 4380 orr.w r3, r3, #16384 ; 0x4000 2408: b29a uxth r2, r3 240a: 687b ldr r3, [r7, #4] 240c: 821a strh r2, [r3, #16] else { /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ USARTx->CR2 &= CR2_LINEN_Reset; } } 240e: e007 b.n 2420 USARTx->CR2 &= CR2_LINEN_Reset; 2410: 687b ldr r3, [r7, #4] 2412: 8a1b ldrh r3, [r3, #16] 2414: b29b uxth r3, r3 2416: f423 4380 bic.w r3, r3, #16384 ; 0x4000 241a: b29a uxth r2, r3 241c: 687b ldr r3, [r7, #4] 241e: 821a strh r2, [r3, #16] } 2420: bf00 nop 2422: 370c adds r7, #12 2424: 46bd mov sp, r7 2426: bc80 pop {r7} 2428: 4770 bx lr 0000242a : * USART1, USART2, USART3, UART4 or UART5. * @param Data: the data to transmit. * @retval None */ void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) { 242a: b480 push {r7} 242c: b083 sub sp, #12 242e: af00 add r7, sp, #0 2430: 6078 str r0, [r7, #4] 2432: 460b mov r3, r1 2434: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_DATA(Data)); /* Transmit Data */ USARTx->DR = (Data & (uint16_t)0x01FF); 2436: 887b ldrh r3, [r7, #2] 2438: f3c3 0308 ubfx r3, r3, #0, #9 243c: b29a uxth r2, r3 243e: 687b ldr r3, [r7, #4] 2440: 809a strh r2, [r3, #4] } 2442: bf00 nop 2444: 370c adds r7, #12 2446: 46bd mov sp, r7 2448: bc80 pop {r7} 244a: 4770 bx lr 0000244c : * This parameter can be one of the following values: * USART1, USART2, USART3, UART4 or UART5. * @retval The received data. */ uint16_t USART_ReceiveData(USART_TypeDef* USARTx) { 244c: b480 push {r7} 244e: b083 sub sp, #12 2450: af00 add r7, sp, #0 2452: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Receive Data */ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); 2454: 687b ldr r3, [r7, #4] 2456: 889b ldrh r3, [r3, #4] 2458: b29b uxth r3, r3 245a: f3c3 0308 ubfx r3, r3, #0, #9 245e: b29b uxth r3, r3 } 2460: 4618 mov r0, r3 2462: 370c adds r7, #12 2464: 46bd mov sp, r7 2466: bc80 pop {r7} 2468: 4770 bx lr 0000246a : * This parameter can be one of the following values: * USART1, USART2, USART3, UART4 or UART5. * @retval None */ void USART_SendBreak(USART_TypeDef* USARTx) { 246a: b480 push {r7} 246c: b083 sub sp, #12 246e: af00 add r7, sp, #0 2470: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Send break characters */ USARTx->CR1 |= CR1_SBK_Set; 2472: 687b ldr r3, [r7, #4] 2474: 899b ldrh r3, [r3, #12] 2476: b29b uxth r3, r3 2478: f043 0301 orr.w r3, r3, #1 247c: b29a uxth r2, r3 247e: 687b ldr r3, [r7, #4] 2480: 819a strh r2, [r3, #12] } 2482: bf00 nop 2484: 370c adds r7, #12 2486: 46bd mov sp, r7 2488: bc80 pop {r7} 248a: 4770 bx lr 0000248c : * @param USART_GuardTime: specifies the guard time. * @note The guard time bits are not available for UART4 and UART5. * @retval None */ void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) { 248c: b480 push {r7} 248e: b083 sub sp, #12 2490: af00 add r7, sp, #0 2492: 6078 str r0, [r7, #4] 2494: 460b mov r3, r1 2496: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_123_PERIPH(USARTx)); /* Clear the USART Guard time */ USARTx->GTPR &= GTPR_LSB_Mask; 2498: 687b ldr r3, [r7, #4] 249a: 8b1b ldrh r3, [r3, #24] 249c: b29b uxth r3, r3 249e: b2db uxtb r3, r3 24a0: b29a uxth r2, r3 24a2: 687b ldr r3, [r7, #4] 24a4: 831a strh r2, [r3, #24] /* Set the USART guard time */ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); 24a6: 687b ldr r3, [r7, #4] 24a8: 8b1b ldrh r3, [r3, #24] 24aa: b29a uxth r2, r3 24ac: 78fb ldrb r3, [r7, #3] 24ae: b29b uxth r3, r3 24b0: 021b lsls r3, r3, #8 24b2: b29b uxth r3, r3 24b4: 4313 orrs r3, r2 24b6: b29a uxth r2, r3 24b8: 687b ldr r3, [r7, #4] 24ba: 831a strh r2, [r3, #24] } 24bc: bf00 nop 24be: 370c adds r7, #12 24c0: 46bd mov sp, r7 24c2: bc80 pop {r7} 24c4: 4770 bx lr 000024c6 : * @param USART_Prescaler: specifies the prescaler clock. * @note The function is used for IrDA mode with UART4 and UART5. * @retval None */ void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) { 24c6: b480 push {r7} 24c8: b083 sub sp, #12 24ca: af00 add r7, sp, #0 24cc: 6078 str r0, [r7, #4] 24ce: 460b mov r3, r1 24d0: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Clear the USART prescaler */ USARTx->GTPR &= GTPR_MSB_Mask; 24d2: 687b ldr r3, [r7, #4] 24d4: 8b1b ldrh r3, [r3, #24] 24d6: b29b uxth r3, r3 24d8: f023 03ff bic.w r3, r3, #255 ; 0xff 24dc: b29a uxth r2, r3 24de: 687b ldr r3, [r7, #4] 24e0: 831a strh r2, [r3, #24] /* Set the USART prescaler */ USARTx->GTPR |= USART_Prescaler; 24e2: 687b ldr r3, [r7, #4] 24e4: 8b1b ldrh r3, [r3, #24] 24e6: b29a uxth r2, r3 24e8: 78fb ldrb r3, [r7, #3] 24ea: b29b uxth r3, r3 24ec: 4313 orrs r3, r2 24ee: b29a uxth r2, r3 24f0: 687b ldr r3, [r7, #4] 24f2: 831a strh r2, [r3, #24] } 24f4: bf00 nop 24f6: 370c adds r7, #12 24f8: 46bd mov sp, r7 24fa: bc80 pop {r7} 24fc: 4770 bx lr 000024fe : * This parameter can be: ENABLE or DISABLE. * @note The Smart Card mode is not available for UART4 and UART5. * @retval None */ void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) { 24fe: b480 push {r7} 2500: b083 sub sp, #12 2502: af00 add r7, sp, #0 2504: 6078 str r0, [r7, #4] 2506: 460b mov r3, r1 2508: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_123_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 250a: 78fb ldrb r3, [r7, #3] 250c: 2b00 cmp r3, #0 250e: d008 beq.n 2522 { /* Enable the SC mode by setting the SCEN bit in the CR3 register */ USARTx->CR3 |= CR3_SCEN_Set; 2510: 687b ldr r3, [r7, #4] 2512: 8a9b ldrh r3, [r3, #20] 2514: b29b uxth r3, r3 2516: f043 0320 orr.w r3, r3, #32 251a: b29a uxth r2, r3 251c: 687b ldr r3, [r7, #4] 251e: 829a strh r2, [r3, #20] else { /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ USARTx->CR3 &= CR3_SCEN_Reset; } } 2520: e007 b.n 2532 USARTx->CR3 &= CR3_SCEN_Reset; 2522: 687b ldr r3, [r7, #4] 2524: 8a9b ldrh r3, [r3, #20] 2526: b29b uxth r3, r3 2528: f023 0320 bic.w r3, r3, #32 252c: b29a uxth r2, r3 252e: 687b ldr r3, [r7, #4] 2530: 829a strh r2, [r3, #20] } 2532: bf00 nop 2534: 370c adds r7, #12 2536: 46bd mov sp, r7 2538: bc80 pop {r7} 253a: 4770 bx lr 0000253c : * This parameter can be: ENABLE or DISABLE. * @note The Smart Card mode is not available for UART4 and UART5. * @retval None */ void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) { 253c: b480 push {r7} 253e: b083 sub sp, #12 2540: af00 add r7, sp, #0 2542: 6078 str r0, [r7, #4] 2544: 460b mov r3, r1 2546: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_123_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2548: 78fb ldrb r3, [r7, #3] 254a: 2b00 cmp r3, #0 254c: d008 beq.n 2560 { /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ USARTx->CR3 |= CR3_NACK_Set; 254e: 687b ldr r3, [r7, #4] 2550: 8a9b ldrh r3, [r3, #20] 2552: b29b uxth r3, r3 2554: f043 0310 orr.w r3, r3, #16 2558: b29a uxth r2, r3 255a: 687b ldr r3, [r7, #4] 255c: 829a strh r2, [r3, #20] else { /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ USARTx->CR3 &= CR3_NACK_Reset; } } 255e: e007 b.n 2570 USARTx->CR3 &= CR3_NACK_Reset; 2560: 687b ldr r3, [r7, #4] 2562: 8a9b ldrh r3, [r3, #20] 2564: b29b uxth r3, r3 2566: f023 0310 bic.w r3, r3, #16 256a: b29a uxth r2, r3 256c: 687b ldr r3, [r7, #4] 256e: 829a strh r2, [r3, #20] } 2570: bf00 nop 2572: 370c adds r7, #12 2574: 46bd mov sp, r7 2576: bc80 pop {r7} 2578: 4770 bx lr 0000257a : * @param NewState: new state of the USART Communication. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) { 257a: b480 push {r7} 257c: b083 sub sp, #12 257e: af00 add r7, sp, #0 2580: 6078 str r0, [r7, #4] 2582: 460b mov r3, r1 2584: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2586: 78fb ldrb r3, [r7, #3] 2588: 2b00 cmp r3, #0 258a: d008 beq.n 259e { /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ USARTx->CR3 |= CR3_HDSEL_Set; 258c: 687b ldr r3, [r7, #4] 258e: 8a9b ldrh r3, [r3, #20] 2590: b29b uxth r3, r3 2592: f043 0308 orr.w r3, r3, #8 2596: b29a uxth r2, r3 2598: 687b ldr r3, [r7, #4] 259a: 829a strh r2, [r3, #20] else { /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ USARTx->CR3 &= CR3_HDSEL_Reset; } } 259c: e007 b.n 25ae USARTx->CR3 &= CR3_HDSEL_Reset; 259e: 687b ldr r3, [r7, #4] 25a0: 8a9b ldrh r3, [r3, #20] 25a2: b29b uxth r3, r3 25a4: f023 0308 bic.w r3, r3, #8 25a8: b29a uxth r2, r3 25aa: 687b ldr r3, [r7, #4] 25ac: 829a strh r2, [r3, #20] } 25ae: bf00 nop 25b0: 370c adds r7, #12 25b2: 46bd mov sp, r7 25b4: bc80 pop {r7} 25b6: 4770 bx lr 000025b8 : * This function has to be called before calling USART_Init() * function in order to have correct baudrate Divider value. * @retval None */ void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) { 25b8: b480 push {r7} 25ba: b083 sub sp, #12 25bc: af00 add r7, sp, #0 25be: 6078 str r0, [r7, #4] 25c0: 460b mov r3, r1 25c2: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 25c4: 78fb ldrb r3, [r7, #3] 25c6: 2b00 cmp r3, #0 25c8: d00a beq.n 25e0 { /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ USARTx->CR1 |= CR1_OVER8_Set; 25ca: 687b ldr r3, [r7, #4] 25cc: 899b ldrh r3, [r3, #12] 25ce: b29b uxth r3, r3 25d0: ea6f 4343 mvn.w r3, r3, lsl #17 25d4: ea6f 4353 mvn.w r3, r3, lsr #17 25d8: b29a uxth r2, r3 25da: 687b ldr r3, [r7, #4] 25dc: 819a strh r2, [r3, #12] else { /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ USARTx->CR1 &= CR1_OVER8_Reset; } } 25de: e007 b.n 25f0 USARTx->CR1 &= CR1_OVER8_Reset; 25e0: 687b ldr r3, [r7, #4] 25e2: 899b ldrh r3, [r3, #12] 25e4: b29b uxth r3, r3 25e6: f3c3 030e ubfx r3, r3, #0, #15 25ea: b29a uxth r2, r3 25ec: 687b ldr r3, [r7, #4] 25ee: 819a strh r2, [r3, #12] } 25f0: bf00 nop 25f2: 370c adds r7, #12 25f4: 46bd mov sp, r7 25f6: bc80 pop {r7} 25f8: 4770 bx lr 000025fa : * @param NewState: new state of the USART one bit sampling method. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) { 25fa: b480 push {r7} 25fc: b083 sub sp, #12 25fe: af00 add r7, sp, #0 2600: 6078 str r0, [r7, #4] 2602: 460b mov r3, r1 2604: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2606: 78fb ldrb r3, [r7, #3] 2608: 2b00 cmp r3, #0 260a: d008 beq.n 261e { /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ USARTx->CR3 |= CR3_ONEBITE_Set; 260c: 687b ldr r3, [r7, #4] 260e: 8a9b ldrh r3, [r3, #20] 2610: b29b uxth r3, r3 2612: f443 6300 orr.w r3, r3, #2048 ; 0x800 2616: b29a uxth r2, r3 2618: 687b ldr r3, [r7, #4] 261a: 829a strh r2, [r3, #20] else { /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ USARTx->CR3 &= CR3_ONEBITE_Reset; } } 261c: e007 b.n 262e USARTx->CR3 &= CR3_ONEBITE_Reset; 261e: 687b ldr r3, [r7, #4] 2620: 8a9b ldrh r3, [r3, #20] 2622: b29b uxth r3, r3 2624: f423 6300 bic.w r3, r3, #2048 ; 0x800 2628: b29a uxth r2, r3 262a: 687b ldr r3, [r7, #4] 262c: 829a strh r2, [r3, #20] } 262e: bf00 nop 2630: 370c adds r7, #12 2632: 46bd mov sp, r7 2634: bc80 pop {r7} 2636: 4770 bx lr 00002638 : * @arg USART_IrDAMode_LowPower * @arg USART_IrDAMode_Normal * @retval None */ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) { 2638: b480 push {r7} 263a: b083 sub sp, #12 263c: af00 add r7, sp, #0 263e: 6078 str r0, [r7, #4] 2640: 460b mov r3, r1 2642: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); USARTx->CR3 &= CR3_IRLP_Mask; 2644: 687b ldr r3, [r7, #4] 2646: 8a9b ldrh r3, [r3, #20] 2648: b29b uxth r3, r3 264a: f023 0304 bic.w r3, r3, #4 264e: b29a uxth r2, r3 2650: 687b ldr r3, [r7, #4] 2652: 829a strh r2, [r3, #20] USARTx->CR3 |= USART_IrDAMode; 2654: 687b ldr r3, [r7, #4] 2656: 8a9b ldrh r3, [r3, #20] 2658: b29a uxth r2, r3 265a: 887b ldrh r3, [r7, #2] 265c: 4313 orrs r3, r2 265e: b29a uxth r2, r3 2660: 687b ldr r3, [r7, #4] 2662: 829a strh r2, [r3, #20] } 2664: bf00 nop 2666: 370c adds r7, #12 2668: 46bd mov sp, r7 266a: bc80 pop {r7} 266c: 4770 bx lr 0000266e : * @param NewState: new state of the IrDA mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) { 266e: b480 push {r7} 2670: b083 sub sp, #12 2672: af00 add r7, sp, #0 2674: 6078 str r0, [r7, #4] 2676: 460b mov r3, r1 2678: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 267a: 78fb ldrb r3, [r7, #3] 267c: 2b00 cmp r3, #0 267e: d008 beq.n 2692 { /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ USARTx->CR3 |= CR3_IREN_Set; 2680: 687b ldr r3, [r7, #4] 2682: 8a9b ldrh r3, [r3, #20] 2684: b29b uxth r3, r3 2686: f043 0302 orr.w r3, r3, #2 268a: b29a uxth r2, r3 268c: 687b ldr r3, [r7, #4] 268e: 829a strh r2, [r3, #20] else { /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ USARTx->CR3 &= CR3_IREN_Reset; } } 2690: e007 b.n 26a2 USARTx->CR3 &= CR3_IREN_Reset; 2692: 687b ldr r3, [r7, #4] 2694: 8a9b ldrh r3, [r3, #20] 2696: b29b uxth r3, r3 2698: f023 0302 bic.w r3, r3, #2 269c: b29a uxth r2, r3 269e: 687b ldr r3, [r7, #4] 26a0: 829a strh r2, [r3, #20] } 26a2: bf00 nop 26a4: 370c adds r7, #12 26a6: 46bd mov sp, r7 26a8: bc80 pop {r7} 26aa: 4770 bx lr 000026ac : * @arg USART_FLAG_FE: Framing Error flag * @arg USART_FLAG_PE: Parity Error flag * @retval The new state of USART_FLAG (SET or RESET). */ FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) { 26ac: b480 push {r7} 26ae: b085 sub sp, #20 26b0: af00 add r7, sp, #0 26b2: 6078 str r0, [r7, #4] 26b4: 460b mov r3, r1 26b6: 807b strh r3, [r7, #2] FlagStatus bitstatus = RESET; 26b8: 2300 movs r3, #0 26ba: 73fb strb r3, [r7, #15] if (USART_FLAG == USART_FLAG_CTS) { assert_param(IS_USART_123_PERIPH(USARTx)); } if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) 26bc: 687b ldr r3, [r7, #4] 26be: 881b ldrh r3, [r3, #0] 26c0: b29a uxth r2, r3 26c2: 887b ldrh r3, [r7, #2] 26c4: 4013 ands r3, r2 26c6: b29b uxth r3, r3 26c8: 2b00 cmp r3, #0 26ca: d002 beq.n 26d2 { bitstatus = SET; 26cc: 2301 movs r3, #1 26ce: 73fb strb r3, [r7, #15] 26d0: e001 b.n 26d6 } else { bitstatus = RESET; 26d2: 2300 movs r3, #0 26d4: 73fb strb r3, [r7, #15] } return bitstatus; 26d6: 7bfb ldrb r3, [r7, #15] } 26d8: 4618 mov r0, r3 26da: 3714 adds r7, #20 26dc: 46bd mov sp, r7 26de: bc80 pop {r7} 26e0: 4770 bx lr 000026e2 : * - TXE flag is cleared only by a write to the USART_DR register * (USART_SendData()). * @retval None */ void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) { 26e2: b480 push {r7} 26e4: b083 sub sp, #12 26e6: af00 add r7, sp, #0 26e8: 6078 str r0, [r7, #4] 26ea: 460b mov r3, r1 26ec: 807b strh r3, [r7, #2] if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) { assert_param(IS_USART_123_PERIPH(USARTx)); } USARTx->SR = (uint16_t)~USART_FLAG; 26ee: 887b ldrh r3, [r7, #2] 26f0: 43db mvns r3, r3 26f2: b29a uxth r2, r3 26f4: 687b ldr r3, [r7, #4] 26f6: 801a strh r2, [r3, #0] } 26f8: bf00 nop 26fa: 370c adds r7, #12 26fc: 46bd mov sp, r7 26fe: bc80 pop {r7} 2700: 4770 bx lr 00002702 : * @arg USART_IT_FE: Framing Error interrupt * @arg USART_IT_PE: Parity Error interrupt * @retval The new state of USART_IT (SET or RESET). */ ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) { 2702: b480 push {r7} 2704: b087 sub sp, #28 2706: af00 add r7, sp, #0 2708: 6078 str r0, [r7, #4] 270a: 460b mov r3, r1 270c: 807b strh r3, [r7, #2] uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; 270e: 2300 movs r3, #0 2710: 60fb str r3, [r7, #12] 2712: 2300 movs r3, #0 2714: 617b str r3, [r7, #20] 2716: 2300 movs r3, #0 2718: 60bb str r3, [r7, #8] ITStatus bitstatus = RESET; 271a: 2300 movs r3, #0 271c: 74fb strb r3, [r7, #19] { assert_param(IS_USART_123_PERIPH(USARTx)); } /* Get the USART register index */ usartreg = (((uint8_t)USART_IT) >> 0x05); 271e: 887b ldrh r3, [r7, #2] 2720: b2db uxtb r3, r3 2722: 095b lsrs r3, r3, #5 2724: b2db uxtb r3, r3 2726: 60bb str r3, [r7, #8] /* Get the interrupt position */ itmask = USART_IT & IT_Mask; 2728: 887b ldrh r3, [r7, #2] 272a: f003 031f and.w r3, r3, #31 272e: 617b str r3, [r7, #20] itmask = (uint32_t)0x01 << itmask; 2730: 2201 movs r2, #1 2732: 697b ldr r3, [r7, #20] 2734: fa02 f303 lsl.w r3, r2, r3 2738: 617b str r3, [r7, #20] if (usartreg == 0x01) /* The IT is in CR1 register */ 273a: 68bb ldr r3, [r7, #8] 273c: 2b01 cmp r3, #1 273e: d107 bne.n 2750 { itmask &= USARTx->CR1; 2740: 687b ldr r3, [r7, #4] 2742: 899b ldrh r3, [r3, #12] 2744: b29b uxth r3, r3 2746: 461a mov r2, r3 2748: 697b ldr r3, [r7, #20] 274a: 4013 ands r3, r2 274c: 617b str r3, [r7, #20] 274e: e011 b.n 2774 } else if (usartreg == 0x02) /* The IT is in CR2 register */ 2750: 68bb ldr r3, [r7, #8] 2752: 2b02 cmp r3, #2 2754: d107 bne.n 2766 { itmask &= USARTx->CR2; 2756: 687b ldr r3, [r7, #4] 2758: 8a1b ldrh r3, [r3, #16] 275a: b29b uxth r3, r3 275c: 461a mov r2, r3 275e: 697b ldr r3, [r7, #20] 2760: 4013 ands r3, r2 2762: 617b str r3, [r7, #20] 2764: e006 b.n 2774 } else /* The IT is in CR3 register */ { itmask &= USARTx->CR3; 2766: 687b ldr r3, [r7, #4] 2768: 8a9b ldrh r3, [r3, #20] 276a: b29b uxth r3, r3 276c: 461a mov r2, r3 276e: 697b ldr r3, [r7, #20] 2770: 4013 ands r3, r2 2772: 617b str r3, [r7, #20] } bitpos = USART_IT >> 0x08; 2774: 887b ldrh r3, [r7, #2] 2776: 0a1b lsrs r3, r3, #8 2778: b29b uxth r3, r3 277a: 60fb str r3, [r7, #12] bitpos = (uint32_t)0x01 << bitpos; 277c: 2201 movs r2, #1 277e: 68fb ldr r3, [r7, #12] 2780: fa02 f303 lsl.w r3, r2, r3 2784: 60fb str r3, [r7, #12] bitpos &= USARTx->SR; 2786: 687b ldr r3, [r7, #4] 2788: 881b ldrh r3, [r3, #0] 278a: b29b uxth r3, r3 278c: 461a mov r2, r3 278e: 68fb ldr r3, [r7, #12] 2790: 4013 ands r3, r2 2792: 60fb str r3, [r7, #12] if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) 2794: 697b ldr r3, [r7, #20] 2796: 2b00 cmp r3, #0 2798: d005 beq.n 27a6 279a: 68fb ldr r3, [r7, #12] 279c: 2b00 cmp r3, #0 279e: d002 beq.n 27a6 { bitstatus = SET; 27a0: 2301 movs r3, #1 27a2: 74fb strb r3, [r7, #19] 27a4: e001 b.n 27aa } else { bitstatus = RESET; 27a6: 2300 movs r3, #0 27a8: 74fb strb r3, [r7, #19] } return bitstatus; 27aa: 7cfb ldrb r3, [r7, #19] } 27ac: 4618 mov r0, r3 27ae: 371c adds r7, #28 27b0: 46bd mov sp, r7 27b2: bc80 pop {r7} 27b4: 4770 bx lr 000027b6 : * - TXE pending bit is cleared only by a write to the USART_DR register * (USART_SendData()). * @retval None */ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) { 27b6: b480 push {r7} 27b8: b085 sub sp, #20 27ba: af00 add r7, sp, #0 27bc: 6078 str r0, [r7, #4] 27be: 460b mov r3, r1 27c0: 807b strh r3, [r7, #2] uint16_t bitpos = 0x00, itmask = 0x00; 27c2: 2300 movs r3, #0 27c4: 81fb strh r3, [r7, #14] 27c6: 2300 movs r3, #0 27c8: 81bb strh r3, [r7, #12] if (USART_IT == USART_IT_CTS) { assert_param(IS_USART_123_PERIPH(USARTx)); } bitpos = USART_IT >> 0x08; 27ca: 887b ldrh r3, [r7, #2] 27cc: 0a1b lsrs r3, r3, #8 27ce: 81fb strh r3, [r7, #14] itmask = ((uint16_t)0x01 << (uint16_t)bitpos); 27d0: 89fb ldrh r3, [r7, #14] 27d2: 2201 movs r2, #1 27d4: fa02 f303 lsl.w r3, r2, r3 27d8: 81bb strh r3, [r7, #12] USARTx->SR = (uint16_t)~itmask; 27da: 89bb ldrh r3, [r7, #12] 27dc: 43db mvns r3, r3 27de: b29a uxth r2, r3 27e0: 687b ldr r3, [r7, #4] 27e2: 801a strh r2, [r3, #0] } 27e4: bf00 nop 27e6: 3714 adds r7, #20 27e8: 46bd mov sp, r7 27ea: bc80 pop {r7} 27ec: 4770 bx lr 27ee: bf00 nop 000027f0 : * @brief Deinitializes the EXTI peripheral registers to their default reset values. * @param None * @retval None */ void EXTI_DeInit(void) { 27f0: b480 push {r7} 27f2: af00 add r7, sp, #0 EXTI->IMR = 0x00000000; 27f4: 4b09 ldr r3, [pc, #36] ; (281c ) 27f6: 2200 movs r2, #0 27f8: 601a str r2, [r3, #0] EXTI->EMR = 0x00000000; 27fa: 4b08 ldr r3, [pc, #32] ; (281c ) 27fc: 2200 movs r2, #0 27fe: 605a str r2, [r3, #4] EXTI->RTSR = 0x00000000; 2800: 4b06 ldr r3, [pc, #24] ; (281c ) 2802: 2200 movs r2, #0 2804: 609a str r2, [r3, #8] EXTI->FTSR = 0x00000000; 2806: 4b05 ldr r3, [pc, #20] ; (281c ) 2808: 2200 movs r2, #0 280a: 60da str r2, [r3, #12] EXTI->PR = 0x000FFFFF; 280c: 4b03 ldr r3, [pc, #12] ; (281c ) 280e: 4a04 ldr r2, [pc, #16] ; (2820 ) 2810: 615a str r2, [r3, #20] } 2812: bf00 nop 2814: 46bd mov sp, r7 2816: bc80 pop {r7} 2818: 4770 bx lr 281a: bf00 nop 281c: 40010400 .word 0x40010400 2820: 000fffff .word 0x000fffff 00002824 : * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure * that contains the configuration information for the EXTI peripheral. * @retval None */ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) { 2824: b480 push {r7} 2826: b085 sub sp, #20 2828: af00 add r7, sp, #0 282a: 6078 str r0, [r7, #4] uint32_t tmp = 0; 282c: 2300 movs r3, #0 282e: 60fb str r3, [r7, #12] assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); tmp = (uint32_t)EXTI_BASE; 2830: 4b34 ldr r3, [pc, #208] ; (2904 ) 2832: 60fb str r3, [r7, #12] if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) 2834: 687b ldr r3, [r7, #4] 2836: 799b ldrb r3, [r3, #6] 2838: 2b00 cmp r3, #0 283a: d04f beq.n 28dc { /* Clear EXTI line configuration */ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; 283c: 4b31 ldr r3, [pc, #196] ; (2904 ) 283e: 681a ldr r2, [r3, #0] 2840: 687b ldr r3, [r7, #4] 2842: 681b ldr r3, [r3, #0] 2844: 43db mvns r3, r3 2846: 492f ldr r1, [pc, #188] ; (2904 ) 2848: 4013 ands r3, r2 284a: 600b str r3, [r1, #0] EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; 284c: 4b2d ldr r3, [pc, #180] ; (2904 ) 284e: 685a ldr r2, [r3, #4] 2850: 687b ldr r3, [r7, #4] 2852: 681b ldr r3, [r3, #0] 2854: 43db mvns r3, r3 2856: 492b ldr r1, [pc, #172] ; (2904 ) 2858: 4013 ands r3, r2 285a: 604b str r3, [r1, #4] tmp += EXTI_InitStruct->EXTI_Mode; 285c: 687b ldr r3, [r7, #4] 285e: 791b ldrb r3, [r3, #4] 2860: 461a mov r2, r3 2862: 68fb ldr r3, [r7, #12] 2864: 4413 add r3, r2 2866: 60fb str r3, [r7, #12] *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 2868: 68fb ldr r3, [r7, #12] 286a: 6819 ldr r1, [r3, #0] 286c: 687b ldr r3, [r7, #4] 286e: 681a ldr r2, [r3, #0] 2870: 68fb ldr r3, [r7, #12] 2872: 430a orrs r2, r1 2874: 601a str r2, [r3, #0] /* Clear Rising Falling edge configuration */ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; 2876: 4b23 ldr r3, [pc, #140] ; (2904 ) 2878: 689a ldr r2, [r3, #8] 287a: 687b ldr r3, [r7, #4] 287c: 681b ldr r3, [r3, #0] 287e: 43db mvns r3, r3 2880: 4920 ldr r1, [pc, #128] ; (2904 ) 2882: 4013 ands r3, r2 2884: 608b str r3, [r1, #8] EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; 2886: 4b1f ldr r3, [pc, #124] ; (2904 ) 2888: 68da ldr r2, [r3, #12] 288a: 687b ldr r3, [r7, #4] 288c: 681b ldr r3, [r3, #0] 288e: 43db mvns r3, r3 2890: 491c ldr r1, [pc, #112] ; (2904 ) 2892: 4013 ands r3, r2 2894: 60cb str r3, [r1, #12] /* Select the trigger for the selected external interrupts */ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 2896: 687b ldr r3, [r7, #4] 2898: 795b ldrb r3, [r3, #5] 289a: 2b10 cmp r3, #16 289c: d10e bne.n 28bc { /* Rising Falling edge */ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; 289e: 4b19 ldr r3, [pc, #100] ; (2904 ) 28a0: 689a ldr r2, [r3, #8] 28a2: 687b ldr r3, [r7, #4] 28a4: 681b ldr r3, [r3, #0] 28a6: 4917 ldr r1, [pc, #92] ; (2904 ) 28a8: 4313 orrs r3, r2 28aa: 608b str r3, [r1, #8] EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; 28ac: 4b15 ldr r3, [pc, #84] ; (2904 ) 28ae: 68da ldr r2, [r3, #12] 28b0: 687b ldr r3, [r7, #4] 28b2: 681b ldr r3, [r3, #0] 28b4: 4913 ldr r1, [pc, #76] ; (2904 ) 28b6: 4313 orrs r3, r2 28b8: 60cb str r3, [r1, #12] tmp += EXTI_InitStruct->EXTI_Mode; /* Disable the selected external lines */ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; } } 28ba: e01d b.n 28f8 tmp = (uint32_t)EXTI_BASE; 28bc: 4b11 ldr r3, [pc, #68] ; (2904 ) 28be: 60fb str r3, [r7, #12] tmp += EXTI_InitStruct->EXTI_Trigger; 28c0: 687b ldr r3, [r7, #4] 28c2: 795b ldrb r3, [r3, #5] 28c4: 461a mov r2, r3 28c6: 68fb ldr r3, [r7, #12] 28c8: 4413 add r3, r2 28ca: 60fb str r3, [r7, #12] *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 28cc: 68fb ldr r3, [r7, #12] 28ce: 6819 ldr r1, [r3, #0] 28d0: 687b ldr r3, [r7, #4] 28d2: 681a ldr r2, [r3, #0] 28d4: 68fb ldr r3, [r7, #12] 28d6: 430a orrs r2, r1 28d8: 601a str r2, [r3, #0] } 28da: e00d b.n 28f8 tmp += EXTI_InitStruct->EXTI_Mode; 28dc: 687b ldr r3, [r7, #4] 28de: 791b ldrb r3, [r3, #4] 28e0: 461a mov r2, r3 28e2: 68fb ldr r3, [r7, #12] 28e4: 4413 add r3, r2 28e6: 60fb str r3, [r7, #12] *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; 28e8: 68fb ldr r3, [r7, #12] 28ea: 6819 ldr r1, [r3, #0] 28ec: 687b ldr r3, [r7, #4] 28ee: 681b ldr r3, [r3, #0] 28f0: 43da mvns r2, r3 28f2: 68fb ldr r3, [r7, #12] 28f4: 400a ands r2, r1 28f6: 601a str r2, [r3, #0] } 28f8: bf00 nop 28fa: 3714 adds r7, #20 28fc: 46bd mov sp, r7 28fe: bc80 pop {r7} 2900: 4770 bx lr 2902: bf00 nop 2904: 40010400 .word 0x40010400 00002908 : * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will * be initialized. * @retval None */ void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) { 2908: b480 push {r7} 290a: b083 sub sp, #12 290c: af00 add r7, sp, #0 290e: 6078 str r0, [r7, #4] EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 2910: 687b ldr r3, [r7, #4] 2912: 2200 movs r2, #0 2914: 601a str r2, [r3, #0] EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 2916: 687b ldr r3, [r7, #4] 2918: 2200 movs r2, #0 291a: 711a strb r2, [r3, #4] EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 291c: 687b ldr r3, [r7, #4] 291e: 220c movs r2, #12 2920: 715a strb r2, [r3, #5] EXTI_InitStruct->EXTI_LineCmd = DISABLE; 2922: 687b ldr r3, [r7, #4] 2924: 2200 movs r2, #0 2926: 719a strb r2, [r3, #6] } 2928: bf00 nop 292a: 370c adds r7, #12 292c: 46bd mov sp, r7 292e: bc80 pop {r7} 2930: 4770 bx lr 00002932 : * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. * This parameter can be any combination of EXTI_Linex where x can be (0..19). * @retval None */ void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) { 2932: b480 push {r7} 2934: b083 sub sp, #12 2936: af00 add r7, sp, #0 2938: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->SWIER |= EXTI_Line; 293a: 4b05 ldr r3, [pc, #20] ; (2950 ) 293c: 691a ldr r2, [r3, #16] 293e: 4904 ldr r1, [pc, #16] ; (2950 ) 2940: 687b ldr r3, [r7, #4] 2942: 4313 orrs r3, r2 2944: 610b str r3, [r1, #16] } 2946: bf00 nop 2948: 370c adds r7, #12 294a: 46bd mov sp, r7 294c: bc80 pop {r7} 294e: 4770 bx lr 2950: 40010400 .word 0x40010400 00002954 : * This parameter can be: * @arg EXTI_Linex: External interrupt line x where x(0..19) * @retval The new state of EXTI_Line (SET or RESET). */ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) { 2954: b480 push {r7} 2956: b085 sub sp, #20 2958: af00 add r7, sp, #0 295a: 6078 str r0, [r7, #4] FlagStatus bitstatus = RESET; 295c: 2300 movs r3, #0 295e: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_GET_EXTI_LINE(EXTI_Line)); if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 2960: 4b08 ldr r3, [pc, #32] ; (2984 ) 2962: 695a ldr r2, [r3, #20] 2964: 687b ldr r3, [r7, #4] 2966: 4013 ands r3, r2 2968: 2b00 cmp r3, #0 296a: d002 beq.n 2972 { bitstatus = SET; 296c: 2301 movs r3, #1 296e: 73fb strb r3, [r7, #15] 2970: e001 b.n 2976 } else { bitstatus = RESET; 2972: 2300 movs r3, #0 2974: 73fb strb r3, [r7, #15] } return bitstatus; 2976: 7bfb ldrb r3, [r7, #15] } 2978: 4618 mov r0, r3 297a: 3714 adds r7, #20 297c: 46bd mov sp, r7 297e: bc80 pop {r7} 2980: 4770 bx lr 2982: bf00 nop 2984: 40010400 .word 0x40010400 00002988 : * @param EXTI_Line: specifies the EXTI lines flags to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..19). * @retval None */ void EXTI_ClearFlag(uint32_t EXTI_Line) { 2988: b480 push {r7} 298a: b083 sub sp, #12 298c: af00 add r7, sp, #0 298e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->PR = EXTI_Line; 2990: 4a03 ldr r2, [pc, #12] ; (29a0 ) 2992: 687b ldr r3, [r7, #4] 2994: 6153 str r3, [r2, #20] } 2996: bf00 nop 2998: 370c adds r7, #12 299a: 46bd mov sp, r7 299c: bc80 pop {r7} 299e: 4770 bx lr 29a0: 40010400 .word 0x40010400 000029a4 : * This parameter can be: * @arg EXTI_Linex: External interrupt line x where x(0..19) * @retval The new state of EXTI_Line (SET or RESET). */ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) { 29a4: b480 push {r7} 29a6: b085 sub sp, #20 29a8: af00 add r7, sp, #0 29aa: 6078 str r0, [r7, #4] ITStatus bitstatus = RESET; 29ac: 2300 movs r3, #0 29ae: 73fb strb r3, [r7, #15] uint32_t enablestatus = 0; 29b0: 2300 movs r3, #0 29b2: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_GET_EXTI_LINE(EXTI_Line)); enablestatus = EXTI->IMR & EXTI_Line; 29b4: 4b0c ldr r3, [pc, #48] ; (29e8 ) 29b6: 681b ldr r3, [r3, #0] 29b8: 687a ldr r2, [r7, #4] 29ba: 4013 ands r3, r2 29bc: 60bb str r3, [r7, #8] if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) 29be: 4b0a ldr r3, [pc, #40] ; (29e8 ) 29c0: 695a ldr r2, [r3, #20] 29c2: 687b ldr r3, [r7, #4] 29c4: 4013 ands r3, r2 29c6: 2b00 cmp r3, #0 29c8: d005 beq.n 29d6 29ca: 68bb ldr r3, [r7, #8] 29cc: 2b00 cmp r3, #0 29ce: d002 beq.n 29d6 { bitstatus = SET; 29d0: 2301 movs r3, #1 29d2: 73fb strb r3, [r7, #15] 29d4: e001 b.n 29da } else { bitstatus = RESET; 29d6: 2300 movs r3, #0 29d8: 73fb strb r3, [r7, #15] } return bitstatus; 29da: 7bfb ldrb r3, [r7, #15] } 29dc: 4618 mov r0, r3 29de: 3714 adds r7, #20 29e0: 46bd mov sp, r7 29e2: bc80 pop {r7} 29e4: 4770 bx lr 29e6: bf00 nop 29e8: 40010400 .word 0x40010400 000029ec : * @param EXTI_Line: specifies the EXTI lines to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..19). * @retval None */ void EXTI_ClearITPendingBit(uint32_t EXTI_Line) { 29ec: b480 push {r7} 29ee: b083 sub sp, #12 29f0: af00 add r7, sp, #0 29f2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->PR = EXTI_Line; 29f4: 4a03 ldr r2, [pc, #12] ; (2a04 ) 29f6: 687b ldr r3, [r7, #4] 29f8: 6153 str r3, [r2, #20] } 29fa: bf00 nop 29fc: 370c adds r7, #12 29fe: 46bd mov sp, r7 2a00: bc80 pop {r7} 2a02: 4770 bx lr 2a04: 40010400 .word 0x40010400 00002a08 : * @brief Deinitializes the ADCx peripheral registers to their default reset values. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval None */ void ADC_DeInit(ADC_TypeDef* ADCx) { 2a08: b580 push {r7, lr} 2a0a: b082 sub sp, #8 2a0c: af00 add r7, sp, #0 2a0e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); if (ADCx == ADC1) 2a10: 687b ldr r3, [r7, #4] 2a12: 4a17 ldr r2, [pc, #92] ; (2a70 ) 2a14: 4293 cmp r3, r2 2a16: d10a bne.n 2a2e { /* Enable ADC1 reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); 2a18: 2101 movs r1, #1 2a1a: f44f 7000 mov.w r0, #512 ; 0x200 2a1e: f7fe feaf bl 1780 /* Release ADC1 from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); 2a22: 2100 movs r1, #0 2a24: f44f 7000 mov.w r0, #512 ; 0x200 2a28: f7fe feaa bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); /* Release ADC3 from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); } } } 2a2c: e01c b.n 2a68 else if (ADCx == ADC2) 2a2e: 687b ldr r3, [r7, #4] 2a30: 4a10 ldr r2, [pc, #64] ; (2a74 ) 2a32: 4293 cmp r3, r2 2a34: d10a bne.n 2a4c RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); 2a36: 2101 movs r1, #1 2a38: f44f 6080 mov.w r0, #1024 ; 0x400 2a3c: f7fe fea0 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); 2a40: 2100 movs r1, #0 2a42: f44f 6080 mov.w r0, #1024 ; 0x400 2a46: f7fe fe9b bl 1780 } 2a4a: e00d b.n 2a68 if (ADCx == ADC3) 2a4c: 687b ldr r3, [r7, #4] 2a4e: 4a0a ldr r2, [pc, #40] ; (2a78 ) 2a50: 4293 cmp r3, r2 2a52: d109 bne.n 2a68 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); 2a54: 2101 movs r1, #1 2a56: f44f 4000 mov.w r0, #32768 ; 0x8000 2a5a: f7fe fe91 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); 2a5e: 2100 movs r1, #0 2a60: f44f 4000 mov.w r0, #32768 ; 0x8000 2a64: f7fe fe8c bl 1780 } 2a68: bf00 nop 2a6a: 3708 adds r7, #8 2a6c: 46bd mov sp, r7 2a6e: bd80 pop {r7, pc} 2a70: 40012400 .word 0x40012400 2a74: 40012800 .word 0x40012800 2a78: 40013c00 .word 0x40013c00 00002a7c : * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains * the configuration information for the specified ADC peripheral. * @retval None */ void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) { 2a7c: b480 push {r7} 2a7e: b085 sub sp, #20 2a80: af00 add r7, sp, #0 2a82: 6078 str r0, [r7, #4] 2a84: 6039 str r1, [r7, #0] uint32_t tmpreg1 = 0; 2a86: 2300 movs r3, #0 2a88: 60fb str r3, [r7, #12] uint8_t tmpreg2 = 0; 2a8a: 2300 movs r3, #0 2a8c: 72fb strb r3, [r7, #11] assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); /*---------------------------- ADCx CR1 Configuration -----------------*/ /* Get the ADCx CR1 value */ tmpreg1 = ADCx->CR1; 2a8e: 687b ldr r3, [r7, #4] 2a90: 685b ldr r3, [r3, #4] 2a92: 60fb str r3, [r7, #12] /* Clear DUALMOD and SCAN bits */ tmpreg1 &= CR1_CLEAR_Mask; 2a94: 68fb ldr r3, [r7, #12] 2a96: f423 2370 bic.w r3, r3, #983040 ; 0xf0000 2a9a: f423 7380 bic.w r3, r3, #256 ; 0x100 2a9e: 60fb str r3, [r7, #12] /* Configure ADCx: Dual mode and scan conversion mode */ /* Set DUALMOD bits according to ADC_Mode value */ /* Set SCAN bit according to ADC_ScanConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); 2aa0: 683b ldr r3, [r7, #0] 2aa2: 681a ldr r2, [r3, #0] 2aa4: 683b ldr r3, [r7, #0] 2aa6: 791b ldrb r3, [r3, #4] 2aa8: 021b lsls r3, r3, #8 2aaa: 4313 orrs r3, r2 2aac: 68fa ldr r2, [r7, #12] 2aae: 4313 orrs r3, r2 2ab0: 60fb str r3, [r7, #12] /* Write to ADCx CR1 */ ADCx->CR1 = tmpreg1; 2ab2: 687b ldr r3, [r7, #4] 2ab4: 68fa ldr r2, [r7, #12] 2ab6: 605a str r2, [r3, #4] /*---------------------------- ADCx CR2 Configuration -----------------*/ /* Get the ADCx CR2 value */ tmpreg1 = ADCx->CR2; 2ab8: 687b ldr r3, [r7, #4] 2aba: 689b ldr r3, [r3, #8] 2abc: 60fb str r3, [r7, #12] /* Clear CONT, ALIGN and EXTSEL bits */ tmpreg1 &= CR2_CLEAR_Mask; 2abe: 68fa ldr r2, [r7, #12] 2ac0: 4b16 ldr r3, [pc, #88] ; (2b1c ) 2ac2: 4013 ands r3, r2 2ac4: 60fb str r3, [r7, #12] /* Configure ADCx: external trigger event and continuous conversion mode */ /* Set ALIGN bit according to ADC_DataAlign value */ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ /* Set CONT bit according to ADC_ContinuousConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | 2ac6: 683b ldr r3, [r7, #0] 2ac8: 68da ldr r2, [r3, #12] 2aca: 683b ldr r3, [r7, #0] 2acc: 689b ldr r3, [r3, #8] 2ace: 431a orrs r2, r3 ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); 2ad0: 683b ldr r3, [r7, #0] 2ad2: 795b ldrb r3, [r3, #5] 2ad4: 005b lsls r3, r3, #1 tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | 2ad6: 4313 orrs r3, r2 2ad8: 68fa ldr r2, [r7, #12] 2ada: 4313 orrs r3, r2 2adc: 60fb str r3, [r7, #12] /* Write to ADCx CR2 */ ADCx->CR2 = tmpreg1; 2ade: 687b ldr r3, [r7, #4] 2ae0: 68fa ldr r2, [r7, #12] 2ae2: 609a str r2, [r3, #8] /*---------------------------- ADCx SQR1 Configuration -----------------*/ /* Get the ADCx SQR1 value */ tmpreg1 = ADCx->SQR1; 2ae4: 687b ldr r3, [r7, #4] 2ae6: 6adb ldr r3, [r3, #44] ; 0x2c 2ae8: 60fb str r3, [r7, #12] /* Clear L bits */ tmpreg1 &= SQR1_CLEAR_Mask; 2aea: 68fb ldr r3, [r7, #12] 2aec: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 2af0: 60fb str r3, [r7, #12] /* Configure ADCx: regular channel sequence length */ /* Set L bits according to ADC_NbrOfChannel value */ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); 2af2: 683b ldr r3, [r7, #0] 2af4: 7c1b ldrb r3, [r3, #16] 2af6: 3b01 subs r3, #1 2af8: b2da uxtb r2, r3 2afa: 7afb ldrb r3, [r7, #11] 2afc: 4313 orrs r3, r2 2afe: 72fb strb r3, [r7, #11] tmpreg1 |= (uint32_t)tmpreg2 << 20; 2b00: 7afb ldrb r3, [r7, #11] 2b02: 051b lsls r3, r3, #20 2b04: 68fa ldr r2, [r7, #12] 2b06: 4313 orrs r3, r2 2b08: 60fb str r3, [r7, #12] /* Write to ADCx SQR1 */ ADCx->SQR1 = tmpreg1; 2b0a: 687b ldr r3, [r7, #4] 2b0c: 68fa ldr r2, [r7, #12] 2b0e: 62da str r2, [r3, #44] ; 0x2c } 2b10: bf00 nop 2b12: 3714 adds r7, #20 2b14: 46bd mov sp, r7 2b16: bc80 pop {r7} 2b18: 4770 bx lr 2b1a: bf00 nop 2b1c: fff1f7fd .word 0xfff1f7fd 00002b20 : * @brief Fills each ADC_InitStruct member with its default value. * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. * @retval None */ void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) { 2b20: b480 push {r7} 2b22: b083 sub sp, #12 2b24: af00 add r7, sp, #0 2b26: 6078 str r0, [r7, #4] /* Reset ADC init structure parameters values */ /* Initialize the ADC_Mode member */ ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; 2b28: 687b ldr r3, [r7, #4] 2b2a: 2200 movs r2, #0 2b2c: 601a str r2, [r3, #0] /* initialize the ADC_ScanConvMode member */ ADC_InitStruct->ADC_ScanConvMode = DISABLE; 2b2e: 687b ldr r3, [r7, #4] 2b30: 2200 movs r2, #0 2b32: 711a strb r2, [r3, #4] /* Initialize the ADC_ContinuousConvMode member */ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; 2b34: 687b ldr r3, [r7, #4] 2b36: 2200 movs r2, #0 2b38: 715a strb r2, [r3, #5] /* Initialize the ADC_ExternalTrigConv member */ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; 2b3a: 687b ldr r3, [r7, #4] 2b3c: 2200 movs r2, #0 2b3e: 609a str r2, [r3, #8] /* Initialize the ADC_DataAlign member */ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; 2b40: 687b ldr r3, [r7, #4] 2b42: 2200 movs r2, #0 2b44: 60da str r2, [r3, #12] /* Initialize the ADC_NbrOfChannel member */ ADC_InitStruct->ADC_NbrOfChannel = 1; 2b46: 687b ldr r3, [r7, #4] 2b48: 2201 movs r2, #1 2b4a: 741a strb r2, [r3, #16] } 2b4c: bf00 nop 2b4e: 370c adds r7, #12 2b50: 46bd mov sp, r7 2b52: bc80 pop {r7} 2b54: 4770 bx lr 00002b56 : * @param NewState: new state of the ADCx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 2b56: b480 push {r7} 2b58: b083 sub sp, #12 2b5a: af00 add r7, sp, #0 2b5c: 6078 str r0, [r7, #4] 2b5e: 460b mov r3, r1 2b60: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2b62: 78fb ldrb r3, [r7, #3] 2b64: 2b00 cmp r3, #0 2b66: d006 beq.n 2b76 { /* Set the ADON bit to wake up the ADC from power down mode */ ADCx->CR2 |= CR2_ADON_Set; 2b68: 687b ldr r3, [r7, #4] 2b6a: 689b ldr r3, [r3, #8] 2b6c: f043 0201 orr.w r2, r3, #1 2b70: 687b ldr r3, [r7, #4] 2b72: 609a str r2, [r3, #8] else { /* Disable the selected ADC peripheral */ ADCx->CR2 &= CR2_ADON_Reset; } } 2b74: e005 b.n 2b82 ADCx->CR2 &= CR2_ADON_Reset; 2b76: 687b ldr r3, [r7, #4] 2b78: 689b ldr r3, [r3, #8] 2b7a: f023 0201 bic.w r2, r3, #1 2b7e: 687b ldr r3, [r7, #4] 2b80: 609a str r2, [r3, #8] } 2b82: bf00 nop 2b84: 370c adds r7, #12 2b86: 46bd mov sp, r7 2b88: bc80 pop {r7} 2b8a: 4770 bx lr 00002b8c : * @param NewState: new state of the selected ADC DMA transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 2b8c: b480 push {r7} 2b8e: b083 sub sp, #12 2b90: af00 add r7, sp, #0 2b92: 6078 str r0, [r7, #4] 2b94: 460b mov r3, r1 2b96: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_DMA_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2b98: 78fb ldrb r3, [r7, #3] 2b9a: 2b00 cmp r3, #0 2b9c: d006 beq.n 2bac { /* Enable the selected ADC DMA request */ ADCx->CR2 |= CR2_DMA_Set; 2b9e: 687b ldr r3, [r7, #4] 2ba0: 689b ldr r3, [r3, #8] 2ba2: f443 7280 orr.w r2, r3, #256 ; 0x100 2ba6: 687b ldr r3, [r7, #4] 2ba8: 609a str r2, [r3, #8] else { /* Disable the selected ADC DMA request */ ADCx->CR2 &= CR2_DMA_Reset; } } 2baa: e005 b.n 2bb8 ADCx->CR2 &= CR2_DMA_Reset; 2bac: 687b ldr r3, [r7, #4] 2bae: 689b ldr r3, [r3, #8] 2bb0: f423 7280 bic.w r2, r3, #256 ; 0x100 2bb4: 687b ldr r3, [r7, #4] 2bb6: 609a str r2, [r3, #8] } 2bb8: bf00 nop 2bba: 370c adds r7, #12 2bbc: 46bd mov sp, r7 2bbe: bc80 pop {r7} 2bc0: 4770 bx lr 00002bc2 : * @param NewState: new state of the specified ADC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) { 2bc2: b480 push {r7} 2bc4: b085 sub sp, #20 2bc6: af00 add r7, sp, #0 2bc8: 6078 str r0, [r7, #4] 2bca: 460b mov r3, r1 2bcc: 807b strh r3, [r7, #2] 2bce: 4613 mov r3, r2 2bd0: 707b strb r3, [r7, #1] uint8_t itmask = 0; 2bd2: 2300 movs r3, #0 2bd4: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = (uint8_t)ADC_IT; 2bd6: 887b ldrh r3, [r7, #2] 2bd8: 73fb strb r3, [r7, #15] if (NewState != DISABLE) 2bda: 787b ldrb r3, [r7, #1] 2bdc: 2b00 cmp r3, #0 2bde: d006 beq.n 2bee { /* Enable the selected ADC interrupts */ ADCx->CR1 |= itmask; 2be0: 687b ldr r3, [r7, #4] 2be2: 685a ldr r2, [r3, #4] 2be4: 7bfb ldrb r3, [r7, #15] 2be6: 431a orrs r2, r3 2be8: 687b ldr r3, [r7, #4] 2bea: 605a str r2, [r3, #4] else { /* Disable the selected ADC interrupts */ ADCx->CR1 &= (~(uint32_t)itmask); } } 2bec: e006 b.n 2bfc ADCx->CR1 &= (~(uint32_t)itmask); 2bee: 687b ldr r3, [r7, #4] 2bf0: 685a ldr r2, [r3, #4] 2bf2: 7bfb ldrb r3, [r7, #15] 2bf4: 43db mvns r3, r3 2bf6: 401a ands r2, r3 2bf8: 687b ldr r3, [r7, #4] 2bfa: 605a str r2, [r3, #4] } 2bfc: bf00 nop 2bfe: 3714 adds r7, #20 2c00: 46bd mov sp, r7 2c02: bc80 pop {r7} 2c04: 4770 bx lr 00002c06 : * @brief Resets the selected ADC calibration registers. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval None */ void ADC_ResetCalibration(ADC_TypeDef* ADCx) { 2c06: b480 push {r7} 2c08: b083 sub sp, #12 2c0a: af00 add r7, sp, #0 2c0c: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Resets the selected ADC calibration registers */ ADCx->CR2 |= CR2_RSTCAL_Set; 2c0e: 687b ldr r3, [r7, #4] 2c10: 689b ldr r3, [r3, #8] 2c12: f043 0208 orr.w r2, r3, #8 2c16: 687b ldr r3, [r7, #4] 2c18: 609a str r2, [r3, #8] } 2c1a: bf00 nop 2c1c: 370c adds r7, #12 2c1e: 46bd mov sp, r7 2c20: bc80 pop {r7} 2c22: 4770 bx lr 00002c24 : * @brief Gets the selected ADC reset calibration registers status. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The new state of ADC reset calibration registers (SET or RESET). */ FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) { 2c24: b480 push {r7} 2c26: b085 sub sp, #20 2c28: af00 add r7, sp, #0 2c2a: 6078 str r0, [r7, #4] FlagStatus bitstatus = RESET; 2c2c: 2300 movs r3, #0 2c2e: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of RSTCAL bit */ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) 2c30: 687b ldr r3, [r7, #4] 2c32: 689b ldr r3, [r3, #8] 2c34: f003 0308 and.w r3, r3, #8 2c38: 2b00 cmp r3, #0 2c3a: d002 beq.n 2c42 { /* RSTCAL bit is set */ bitstatus = SET; 2c3c: 2301 movs r3, #1 2c3e: 73fb strb r3, [r7, #15] 2c40: e001 b.n 2c46 } else { /* RSTCAL bit is reset */ bitstatus = RESET; 2c42: 2300 movs r3, #0 2c44: 73fb strb r3, [r7, #15] } /* Return the RSTCAL bit status */ return bitstatus; 2c46: 7bfb ldrb r3, [r7, #15] } 2c48: 4618 mov r0, r3 2c4a: 3714 adds r7, #20 2c4c: 46bd mov sp, r7 2c4e: bc80 pop {r7} 2c50: 4770 bx lr 00002c52 : * @brief Starts the selected ADC calibration process. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval None */ void ADC_StartCalibration(ADC_TypeDef* ADCx) { 2c52: b480 push {r7} 2c54: b083 sub sp, #12 2c56: af00 add r7, sp, #0 2c58: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC calibration process */ ADCx->CR2 |= CR2_CAL_Set; 2c5a: 687b ldr r3, [r7, #4] 2c5c: 689b ldr r3, [r3, #8] 2c5e: f043 0204 orr.w r2, r3, #4 2c62: 687b ldr r3, [r7, #4] 2c64: 609a str r2, [r3, #8] } 2c66: bf00 nop 2c68: 370c adds r7, #12 2c6a: 46bd mov sp, r7 2c6c: bc80 pop {r7} 2c6e: 4770 bx lr 00002c70 : * @brief Gets the selected ADC calibration status. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The new state of ADC calibration (SET or RESET). */ FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) { 2c70: b480 push {r7} 2c72: b085 sub sp, #20 2c74: af00 add r7, sp, #0 2c76: 6078 str r0, [r7, #4] FlagStatus bitstatus = RESET; 2c78: 2300 movs r3, #0 2c7a: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of CAL bit */ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) 2c7c: 687b ldr r3, [r7, #4] 2c7e: 689b ldr r3, [r3, #8] 2c80: f003 0304 and.w r3, r3, #4 2c84: 2b00 cmp r3, #0 2c86: d002 beq.n 2c8e { /* CAL bit is set: calibration on going */ bitstatus = SET; 2c88: 2301 movs r3, #1 2c8a: 73fb strb r3, [r7, #15] 2c8c: e001 b.n 2c92 } else { /* CAL bit is reset: end of calibration */ bitstatus = RESET; 2c8e: 2300 movs r3, #0 2c90: 73fb strb r3, [r7, #15] } /* Return the CAL bit status */ return bitstatus; 2c92: 7bfb ldrb r3, [r7, #15] } 2c94: 4618 mov r0, r3 2c96: 3714 adds r7, #20 2c98: 46bd mov sp, r7 2c9a: bc80 pop {r7} 2c9c: 4770 bx lr 00002c9e : * @param NewState: new state of the selected ADC software start conversion. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 2c9e: b480 push {r7} 2ca0: b083 sub sp, #12 2ca2: af00 add r7, sp, #0 2ca4: 6078 str r0, [r7, #4] 2ca6: 460b mov r3, r1 2ca8: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2caa: 78fb ldrb r3, [r7, #3] 2cac: 2b00 cmp r3, #0 2cae: d006 beq.n 2cbe { /* Enable the selected ADC conversion on external event and start the selected ADC conversion */ ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; 2cb0: 687b ldr r3, [r7, #4] 2cb2: 689b ldr r3, [r3, #8] 2cb4: f443 02a0 orr.w r2, r3, #5242880 ; 0x500000 2cb8: 687b ldr r3, [r7, #4] 2cba: 609a str r2, [r3, #8] { /* Disable the selected ADC conversion on external event and stop the selected ADC conversion */ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; } } 2cbc: e005 b.n 2cca ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; 2cbe: 687b ldr r3, [r7, #4] 2cc0: 689b ldr r3, [r3, #8] 2cc2: f423 02a0 bic.w r2, r3, #5242880 ; 0x500000 2cc6: 687b ldr r3, [r7, #4] 2cc8: 609a str r2, [r3, #8] } 2cca: bf00 nop 2ccc: 370c adds r7, #12 2cce: 46bd mov sp, r7 2cd0: bc80 pop {r7} 2cd2: 4770 bx lr 00002cd4 : * @brief Gets the selected ADC Software start conversion Status. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The new state of ADC software start conversion (SET or RESET). */ FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) { 2cd4: b480 push {r7} 2cd6: b085 sub sp, #20 2cd8: af00 add r7, sp, #0 2cda: 6078 str r0, [r7, #4] FlagStatus bitstatus = RESET; 2cdc: 2300 movs r3, #0 2cde: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of SWSTART bit */ if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) 2ce0: 687b ldr r3, [r7, #4] 2ce2: 689b ldr r3, [r3, #8] 2ce4: f403 0380 and.w r3, r3, #4194304 ; 0x400000 2ce8: 2b00 cmp r3, #0 2cea: d002 beq.n 2cf2 { /* SWSTART bit is set */ bitstatus = SET; 2cec: 2301 movs r3, #1 2cee: 73fb strb r3, [r7, #15] 2cf0: e001 b.n 2cf6 } else { /* SWSTART bit is reset */ bitstatus = RESET; 2cf2: 2300 movs r3, #0 2cf4: 73fb strb r3, [r7, #15] } /* Return the SWSTART bit status */ return bitstatus; 2cf6: 7bfb ldrb r3, [r7, #15] } 2cf8: 4618 mov r0, r3 2cfa: 3714 adds r7, #20 2cfc: 46bd mov sp, r7 2cfe: bc80 pop {r7} 2d00: 4770 bx lr 00002d02 : * @param Number: specifies the discontinuous mode regular channel * count value. This number must be between 1 and 8. * @retval None */ void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) { 2d02: b480 push {r7} 2d04: b085 sub sp, #20 2d06: af00 add r7, sp, #0 2d08: 6078 str r0, [r7, #4] 2d0a: 460b mov r3, r1 2d0c: 70fb strb r3, [r7, #3] uint32_t tmpreg1 = 0; 2d0e: 2300 movs r3, #0 2d10: 60fb str r3, [r7, #12] uint32_t tmpreg2 = 0; 2d12: 2300 movs r3, #0 2d14: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); /* Get the old register value */ tmpreg1 = ADCx->CR1; 2d16: 687b ldr r3, [r7, #4] 2d18: 685b ldr r3, [r3, #4] 2d1a: 60fb str r3, [r7, #12] /* Clear the old discontinuous mode channel count */ tmpreg1 &= CR1_DISCNUM_Reset; 2d1c: 68fb ldr r3, [r7, #12] 2d1e: f423 4360 bic.w r3, r3, #57344 ; 0xe000 2d22: 60fb str r3, [r7, #12] /* Set the discontinuous mode channel count */ tmpreg2 = Number - 1; 2d24: 78fb ldrb r3, [r7, #3] 2d26: 3b01 subs r3, #1 2d28: 60bb str r3, [r7, #8] tmpreg1 |= tmpreg2 << 13; 2d2a: 68bb ldr r3, [r7, #8] 2d2c: 035b lsls r3, r3, #13 2d2e: 68fa ldr r2, [r7, #12] 2d30: 4313 orrs r3, r2 2d32: 60fb str r3, [r7, #12] /* Store the new register value */ ADCx->CR1 = tmpreg1; 2d34: 687b ldr r3, [r7, #4] 2d36: 68fa ldr r2, [r7, #12] 2d38: 605a str r2, [r3, #4] } 2d3a: bf00 nop 2d3c: 3714 adds r7, #20 2d3e: 46bd mov sp, r7 2d40: bc80 pop {r7} 2d42: 4770 bx lr 00002d44 : * on regular group channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 2d44: b480 push {r7} 2d46: b083 sub sp, #12 2d48: af00 add r7, sp, #0 2d4a: 6078 str r0, [r7, #4] 2d4c: 460b mov r3, r1 2d4e: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2d50: 78fb ldrb r3, [r7, #3] 2d52: 2b00 cmp r3, #0 2d54: d006 beq.n 2d64 { /* Enable the selected ADC regular discontinuous mode */ ADCx->CR1 |= CR1_DISCEN_Set; 2d56: 687b ldr r3, [r7, #4] 2d58: 685b ldr r3, [r3, #4] 2d5a: f443 6200 orr.w r2, r3, #2048 ; 0x800 2d5e: 687b ldr r3, [r7, #4] 2d60: 605a str r2, [r3, #4] else { /* Disable the selected ADC regular discontinuous mode */ ADCx->CR1 &= CR1_DISCEN_Reset; } } 2d62: e005 b.n 2d70 ADCx->CR1 &= CR1_DISCEN_Reset; 2d64: 687b ldr r3, [r7, #4] 2d66: 685b ldr r3, [r3, #4] 2d68: f423 6200 bic.w r2, r3, #2048 ; 0x800 2d6c: 687b ldr r3, [r7, #4] 2d6e: 605a str r2, [r3, #4] } 2d70: bf00 nop 2d72: 370c adds r7, #12 2d74: 46bd mov sp, r7 2d76: bc80 pop {r7} 2d78: 4770 bx lr 00002d7a : * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles * @retval None */ void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) { 2d7a: b480 push {r7} 2d7c: b085 sub sp, #20 2d7e: af00 add r7, sp, #0 2d80: 6078 str r0, [r7, #4] 2d82: 4608 mov r0, r1 2d84: 4611 mov r1, r2 2d86: 461a mov r2, r3 2d88: 4603 mov r3, r0 2d8a: 70fb strb r3, [r7, #3] 2d8c: 460b mov r3, r1 2d8e: 70bb strb r3, [r7, #2] 2d90: 4613 mov r3, r2 2d92: 707b strb r3, [r7, #1] uint32_t tmpreg1 = 0, tmpreg2 = 0; 2d94: 2300 movs r3, #0 2d96: 60fb str r3, [r7, #12] 2d98: 2300 movs r3, #0 2d9a: 60bb str r3, [r7, #8] assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); assert_param(IS_ADC_REGULAR_RANK(Rank)); assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ if (ADC_Channel > ADC_Channel_9) 2d9c: 78fb ldrb r3, [r7, #3] 2d9e: 2b09 cmp r3, #9 2da0: d923 bls.n 2dea { /* Get the old register value */ tmpreg1 = ADCx->SMPR1; 2da2: 687b ldr r3, [r7, #4] 2da4: 68db ldr r3, [r3, #12] 2da6: 60fb str r3, [r7, #12] /* Calculate the mask to clear */ tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); 2da8: 78fb ldrb r3, [r7, #3] 2daa: f1a3 020a sub.w r2, r3, #10 2dae: 4613 mov r3, r2 2db0: 005b lsls r3, r3, #1 2db2: 4413 add r3, r2 2db4: 2207 movs r2, #7 2db6: fa02 f303 lsl.w r3, r2, r3 2dba: 60bb str r3, [r7, #8] /* Clear the old channel sample time */ tmpreg1 &= ~tmpreg2; 2dbc: 68bb ldr r3, [r7, #8] 2dbe: 43db mvns r3, r3 2dc0: 68fa ldr r2, [r7, #12] 2dc2: 4013 ands r3, r2 2dc4: 60fb str r3, [r7, #12] /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); 2dc6: 7879 ldrb r1, [r7, #1] 2dc8: 78fb ldrb r3, [r7, #3] 2dca: f1a3 020a sub.w r2, r3, #10 2dce: 4613 mov r3, r2 2dd0: 005b lsls r3, r3, #1 2dd2: 4413 add r3, r2 2dd4: fa01 f303 lsl.w r3, r1, r3 2dd8: 60bb str r3, [r7, #8] /* Set the new channel sample time */ tmpreg1 |= tmpreg2; 2dda: 68fa ldr r2, [r7, #12] 2ddc: 68bb ldr r3, [r7, #8] 2dde: 4313 orrs r3, r2 2de0: 60fb str r3, [r7, #12] /* Store the new register value */ ADCx->SMPR1 = tmpreg1; 2de2: 687b ldr r3, [r7, #4] 2de4: 68fa ldr r2, [r7, #12] 2de6: 60da str r2, [r3, #12] 2de8: e01e b.n 2e28 } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Get the old register value */ tmpreg1 = ADCx->SMPR2; 2dea: 687b ldr r3, [r7, #4] 2dec: 691b ldr r3, [r3, #16] 2dee: 60fb str r3, [r7, #12] /* Calculate the mask to clear */ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); 2df0: 78fa ldrb r2, [r7, #3] 2df2: 4613 mov r3, r2 2df4: 005b lsls r3, r3, #1 2df6: 4413 add r3, r2 2df8: 2207 movs r2, #7 2dfa: fa02 f303 lsl.w r3, r2, r3 2dfe: 60bb str r3, [r7, #8] /* Clear the old channel sample time */ tmpreg1 &= ~tmpreg2; 2e00: 68bb ldr r3, [r7, #8] 2e02: 43db mvns r3, r3 2e04: 68fa ldr r2, [r7, #12] 2e06: 4013 ands r3, r2 2e08: 60fb str r3, [r7, #12] /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); 2e0a: 7879 ldrb r1, [r7, #1] 2e0c: 78fa ldrb r2, [r7, #3] 2e0e: 4613 mov r3, r2 2e10: 005b lsls r3, r3, #1 2e12: 4413 add r3, r2 2e14: fa01 f303 lsl.w r3, r1, r3 2e18: 60bb str r3, [r7, #8] /* Set the new channel sample time */ tmpreg1 |= tmpreg2; 2e1a: 68fa ldr r2, [r7, #12] 2e1c: 68bb ldr r3, [r7, #8] 2e1e: 4313 orrs r3, r2 2e20: 60fb str r3, [r7, #12] /* Store the new register value */ ADCx->SMPR2 = tmpreg1; 2e22: 687b ldr r3, [r7, #4] 2e24: 68fa ldr r2, [r7, #12] 2e26: 611a str r2, [r3, #16] } /* For Rank 1 to 6 */ if (Rank < 7) 2e28: 78bb ldrb r3, [r7, #2] 2e2a: 2b06 cmp r3, #6 2e2c: d821 bhi.n 2e72 { /* Get the old register value */ tmpreg1 = ADCx->SQR3; 2e2e: 687b ldr r3, [r7, #4] 2e30: 6b5b ldr r3, [r3, #52] ; 0x34 2e32: 60fb str r3, [r7, #12] /* Calculate the mask to clear */ tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); 2e34: 78bb ldrb r3, [r7, #2] 2e36: 1e5a subs r2, r3, #1 2e38: 4613 mov r3, r2 2e3a: 009b lsls r3, r3, #2 2e3c: 4413 add r3, r2 2e3e: 221f movs r2, #31 2e40: fa02 f303 lsl.w r3, r2, r3 2e44: 60bb str r3, [r7, #8] /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; 2e46: 68bb ldr r3, [r7, #8] 2e48: 43db mvns r3, r3 2e4a: 68fa ldr r2, [r7, #12] 2e4c: 4013 ands r3, r2 2e4e: 60fb str r3, [r7, #12] /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); 2e50: 78f9 ldrb r1, [r7, #3] 2e52: 78bb ldrb r3, [r7, #2] 2e54: 1e5a subs r2, r3, #1 2e56: 4613 mov r3, r2 2e58: 009b lsls r3, r3, #2 2e5a: 4413 add r3, r2 2e5c: fa01 f303 lsl.w r3, r1, r3 2e60: 60bb str r3, [r7, #8] /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; 2e62: 68fa ldr r2, [r7, #12] 2e64: 68bb ldr r3, [r7, #8] 2e66: 4313 orrs r3, r2 2e68: 60fb str r3, [r7, #12] /* Store the new register value */ ADCx->SQR3 = tmpreg1; 2e6a: 687b ldr r3, [r7, #4] 2e6c: 68fa ldr r2, [r7, #12] 2e6e: 635a str r2, [r3, #52] ; 0x34 /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR1 = tmpreg1; } } 2e70: e047 b.n 2f02 else if (Rank < 13) 2e72: 78bb ldrb r3, [r7, #2] 2e74: 2b0c cmp r3, #12 2e76: d821 bhi.n 2ebc tmpreg1 = ADCx->SQR2; 2e78: 687b ldr r3, [r7, #4] 2e7a: 6b1b ldr r3, [r3, #48] ; 0x30 2e7c: 60fb str r3, [r7, #12] tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); 2e7e: 78bb ldrb r3, [r7, #2] 2e80: 1fda subs r2, r3, #7 2e82: 4613 mov r3, r2 2e84: 009b lsls r3, r3, #2 2e86: 4413 add r3, r2 2e88: 221f movs r2, #31 2e8a: fa02 f303 lsl.w r3, r2, r3 2e8e: 60bb str r3, [r7, #8] tmpreg1 &= ~tmpreg2; 2e90: 68bb ldr r3, [r7, #8] 2e92: 43db mvns r3, r3 2e94: 68fa ldr r2, [r7, #12] 2e96: 4013 ands r3, r2 2e98: 60fb str r3, [r7, #12] tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); 2e9a: 78f9 ldrb r1, [r7, #3] 2e9c: 78bb ldrb r3, [r7, #2] 2e9e: 1fda subs r2, r3, #7 2ea0: 4613 mov r3, r2 2ea2: 009b lsls r3, r3, #2 2ea4: 4413 add r3, r2 2ea6: fa01 f303 lsl.w r3, r1, r3 2eaa: 60bb str r3, [r7, #8] tmpreg1 |= tmpreg2; 2eac: 68fa ldr r2, [r7, #12] 2eae: 68bb ldr r3, [r7, #8] 2eb0: 4313 orrs r3, r2 2eb2: 60fb str r3, [r7, #12] ADCx->SQR2 = tmpreg1; 2eb4: 687b ldr r3, [r7, #4] 2eb6: 68fa ldr r2, [r7, #12] 2eb8: 631a str r2, [r3, #48] ; 0x30 } 2eba: e022 b.n 2f02 tmpreg1 = ADCx->SQR1; 2ebc: 687b ldr r3, [r7, #4] 2ebe: 6adb ldr r3, [r3, #44] ; 0x2c 2ec0: 60fb str r3, [r7, #12] tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); 2ec2: 78bb ldrb r3, [r7, #2] 2ec4: f1a3 020d sub.w r2, r3, #13 2ec8: 4613 mov r3, r2 2eca: 009b lsls r3, r3, #2 2ecc: 4413 add r3, r2 2ece: 221f movs r2, #31 2ed0: fa02 f303 lsl.w r3, r2, r3 2ed4: 60bb str r3, [r7, #8] tmpreg1 &= ~tmpreg2; 2ed6: 68bb ldr r3, [r7, #8] 2ed8: 43db mvns r3, r3 2eda: 68fa ldr r2, [r7, #12] 2edc: 4013 ands r3, r2 2ede: 60fb str r3, [r7, #12] tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); 2ee0: 78f9 ldrb r1, [r7, #3] 2ee2: 78bb ldrb r3, [r7, #2] 2ee4: f1a3 020d sub.w r2, r3, #13 2ee8: 4613 mov r3, r2 2eea: 009b lsls r3, r3, #2 2eec: 4413 add r3, r2 2eee: fa01 f303 lsl.w r3, r1, r3 2ef2: 60bb str r3, [r7, #8] tmpreg1 |= tmpreg2; 2ef4: 68fa ldr r2, [r7, #12] 2ef6: 68bb ldr r3, [r7, #8] 2ef8: 4313 orrs r3, r2 2efa: 60fb str r3, [r7, #12] ADCx->SQR1 = tmpreg1; 2efc: 687b ldr r3, [r7, #4] 2efe: 68fa ldr r2, [r7, #12] 2f00: 62da str r2, [r3, #44] ; 0x2c } 2f02: bf00 nop 2f04: 3714 adds r7, #20 2f06: 46bd mov sp, r7 2f08: bc80 pop {r7} 2f0a: 4770 bx lr 00002f0c : * @param NewState: new state of the selected ADC external trigger start of conversion. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 2f0c: b480 push {r7} 2f0e: b083 sub sp, #12 2f10: af00 add r7, sp, #0 2f12: 6078 str r0, [r7, #4] 2f14: 460b mov r3, r1 2f16: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2f18: 78fb ldrb r3, [r7, #3] 2f1a: 2b00 cmp r3, #0 2f1c: d006 beq.n 2f2c { /* Enable the selected ADC conversion on external event */ ADCx->CR2 |= CR2_EXTTRIG_Set; 2f1e: 687b ldr r3, [r7, #4] 2f20: 689b ldr r3, [r3, #8] 2f22: f443 1280 orr.w r2, r3, #1048576 ; 0x100000 2f26: 687b ldr r3, [r7, #4] 2f28: 609a str r2, [r3, #8] else { /* Disable the selected ADC conversion on external event */ ADCx->CR2 &= CR2_EXTTRIG_Reset; } } 2f2a: e005 b.n 2f38 ADCx->CR2 &= CR2_EXTTRIG_Reset; 2f2c: 687b ldr r3, [r7, #4] 2f2e: 689b ldr r3, [r3, #8] 2f30: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 2f34: 687b ldr r3, [r7, #4] 2f36: 609a str r2, [r3, #8] } 2f38: bf00 nop 2f3a: 370c adds r7, #12 2f3c: 46bd mov sp, r7 2f3e: bc80 pop {r7} 2f40: 4770 bx lr 00002f42 : * @brief Returns the last ADCx conversion result data for regular channel. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The Data conversion value. */ uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) { 2f42: b480 push {r7} 2f44: b083 sub sp, #12 2f46: af00 add r7, sp, #0 2f48: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Return the selected ADC conversion value */ return (uint16_t) ADCx->DR; 2f4a: 687b ldr r3, [r7, #4] 2f4c: 6cdb ldr r3, [r3, #76] ; 0x4c 2f4e: b29b uxth r3, r3 } 2f50: 4618 mov r0, r3 2f52: 370c adds r7, #12 2f54: 46bd mov sp, r7 2f56: bc80 pop {r7} 2f58: 4770 bx lr 00002f5a : /** * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. * @retval The Data conversion value. */ uint32_t ADC_GetDualModeConversionValue(void) { 2f5a: b480 push {r7} 2f5c: af00 add r7, sp, #0 /* Return the dual mode conversion value */ return (*(__IO uint32_t *) DR_ADDRESS); 2f5e: 4b03 ldr r3, [pc, #12] ; (2f6c ) 2f60: 681b ldr r3, [r3, #0] } 2f62: 4618 mov r0, r3 2f64: 46bd mov sp, r7 2f66: bc80 pop {r7} 2f68: 4770 bx lr 2f6a: bf00 nop 2f6c: 4001244c .word 0x4001244c 00002f70 : * @param NewState: new state of the selected ADC auto injected conversion * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 2f70: b480 push {r7} 2f72: b083 sub sp, #12 2f74: af00 add r7, sp, #0 2f76: 6078 str r0, [r7, #4] 2f78: 460b mov r3, r1 2f7a: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2f7c: 78fb ldrb r3, [r7, #3] 2f7e: 2b00 cmp r3, #0 2f80: d006 beq.n 2f90 { /* Enable the selected ADC automatic injected group conversion */ ADCx->CR1 |= CR1_JAUTO_Set; 2f82: 687b ldr r3, [r7, #4] 2f84: 685b ldr r3, [r3, #4] 2f86: f443 6280 orr.w r2, r3, #1024 ; 0x400 2f8a: 687b ldr r3, [r7, #4] 2f8c: 605a str r2, [r3, #4] else { /* Disable the selected ADC automatic injected group conversion */ ADCx->CR1 &= CR1_JAUTO_Reset; } } 2f8e: e005 b.n 2f9c ADCx->CR1 &= CR1_JAUTO_Reset; 2f90: 687b ldr r3, [r7, #4] 2f92: 685b ldr r3, [r3, #4] 2f94: f423 6280 bic.w r2, r3, #1024 ; 0x400 2f98: 687b ldr r3, [r7, #4] 2f9a: 605a str r2, [r3, #4] } 2f9c: bf00 nop 2f9e: 370c adds r7, #12 2fa0: 46bd mov sp, r7 2fa2: bc80 pop {r7} 2fa4: 4770 bx lr 00002fa6 : * on injected group channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 2fa6: b480 push {r7} 2fa8: b083 sub sp, #12 2faa: af00 add r7, sp, #0 2fac: 6078 str r0, [r7, #4] 2fae: 460b mov r3, r1 2fb0: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 2fb2: 78fb ldrb r3, [r7, #3] 2fb4: 2b00 cmp r3, #0 2fb6: d006 beq.n 2fc6 { /* Enable the selected ADC injected discontinuous mode */ ADCx->CR1 |= CR1_JDISCEN_Set; 2fb8: 687b ldr r3, [r7, #4] 2fba: 685b ldr r3, [r3, #4] 2fbc: f443 5280 orr.w r2, r3, #4096 ; 0x1000 2fc0: 687b ldr r3, [r7, #4] 2fc2: 605a str r2, [r3, #4] else { /* Disable the selected ADC injected discontinuous mode */ ADCx->CR1 &= CR1_JDISCEN_Reset; } } 2fc4: e005 b.n 2fd2 ADCx->CR1 &= CR1_JDISCEN_Reset; 2fc6: 687b ldr r3, [r7, #4] 2fc8: 685b ldr r3, [r3, #4] 2fca: f423 5280 bic.w r2, r3, #4096 ; 0x1000 2fce: 687b ldr r3, [r7, #4] 2fd0: 605a str r2, [r3, #4] } 2fd2: bf00 nop 2fd4: 370c adds r7, #12 2fd6: 46bd mov sp, r7 2fd8: bc80 pop {r7} 2fda: 4770 bx lr 00002fdc : * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not * by external trigger (for ADC1, ADC2 and ADC3) * @retval None */ void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) { 2fdc: b480 push {r7} 2fde: b085 sub sp, #20 2fe0: af00 add r7, sp, #0 2fe2: 6078 str r0, [r7, #4] 2fe4: 6039 str r1, [r7, #0] uint32_t tmpreg = 0; 2fe6: 2300 movs r3, #0 2fe8: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); /* Get the old register value */ tmpreg = ADCx->CR2; 2fea: 687b ldr r3, [r7, #4] 2fec: 689b ldr r3, [r3, #8] 2fee: 60fb str r3, [r7, #12] /* Clear the old external event selection for injected group */ tmpreg &= CR2_JEXTSEL_Reset; 2ff0: 68fb ldr r3, [r7, #12] 2ff2: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 2ff6: 60fb str r3, [r7, #12] /* Set the external event selection for injected group */ tmpreg |= ADC_ExternalTrigInjecConv; 2ff8: 68fa ldr r2, [r7, #12] 2ffa: 683b ldr r3, [r7, #0] 2ffc: 4313 orrs r3, r2 2ffe: 60fb str r3, [r7, #12] /* Store the new register value */ ADCx->CR2 = tmpreg; 3000: 687b ldr r3, [r7, #4] 3002: 68fa ldr r2, [r7, #12] 3004: 609a str r2, [r3, #8] } 3006: bf00 nop 3008: 3714 adds r7, #20 300a: 46bd mov sp, r7 300c: bc80 pop {r7} 300e: 4770 bx lr 00003010 : * injected conversion. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 3010: b480 push {r7} 3012: b083 sub sp, #12 3014: af00 add r7, sp, #0 3016: 6078 str r0, [r7, #4] 3018: 460b mov r3, r1 301a: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 301c: 78fb ldrb r3, [r7, #3] 301e: 2b00 cmp r3, #0 3020: d006 beq.n 3030 { /* Enable the selected ADC external event selection for injected group */ ADCx->CR2 |= CR2_JEXTTRIG_Set; 3022: 687b ldr r3, [r7, #4] 3024: 689b ldr r3, [r3, #8] 3026: f443 4200 orr.w r2, r3, #32768 ; 0x8000 302a: 687b ldr r3, [r7, #4] 302c: 609a str r2, [r3, #8] else { /* Disable the selected ADC external event selection for injected group */ ADCx->CR2 &= CR2_JEXTTRIG_Reset; } } 302e: e005 b.n 303c ADCx->CR2 &= CR2_JEXTTRIG_Reset; 3030: 687b ldr r3, [r7, #4] 3032: 689b ldr r3, [r3, #8] 3034: f423 4200 bic.w r2, r3, #32768 ; 0x8000 3038: 687b ldr r3, [r7, #4] 303a: 609a str r2, [r3, #8] } 303c: bf00 nop 303e: 370c adds r7, #12 3040: 46bd mov sp, r7 3042: bc80 pop {r7} 3044: 4770 bx lr 00003046 : * @param NewState: new state of the selected ADC software start injected conversion. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { 3046: b480 push {r7} 3048: b083 sub sp, #12 304a: af00 add r7, sp, #0 304c: 6078 str r0, [r7, #4] 304e: 460b mov r3, r1 3050: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 3052: 78fb ldrb r3, [r7, #3] 3054: 2b00 cmp r3, #0 3056: d006 beq.n 3066 { /* Enable the selected ADC conversion for injected group on external event and start the selected ADC injected conversion */ ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; 3058: 687b ldr r3, [r7, #4] 305a: 689b ldr r3, [r3, #8] 305c: f443 1202 orr.w r2, r3, #2129920 ; 0x208000 3060: 687b ldr r3, [r7, #4] 3062: 609a str r2, [r3, #8] { /* Disable the selected ADC conversion on external event for injected group and stop the selected ADC injected conversion */ ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; } } 3064: e005 b.n 3072 ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; 3066: 687b ldr r3, [r7, #4] 3068: 689b ldr r3, [r3, #8] 306a: f423 1202 bic.w r2, r3, #2129920 ; 0x208000 306e: 687b ldr r3, [r7, #4] 3070: 609a str r2, [r3, #8] } 3072: bf00 nop 3074: 370c adds r7, #12 3076: 46bd mov sp, r7 3078: bc80 pop {r7} 307a: 4770 bx lr 0000307c : * @brief Gets the selected ADC Software start injected conversion Status. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The new state of ADC software start injected conversion (SET or RESET). */ FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) { 307c: b480 push {r7} 307e: b085 sub sp, #20 3080: af00 add r7, sp, #0 3082: 6078 str r0, [r7, #4] FlagStatus bitstatus = RESET; 3084: 2300 movs r3, #0 3086: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of JSWSTART bit */ if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) 3088: 687b ldr r3, [r7, #4] 308a: 689b ldr r3, [r3, #8] 308c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 3090: 2b00 cmp r3, #0 3092: d002 beq.n 309a { /* JSWSTART bit is set */ bitstatus = SET; 3094: 2301 movs r3, #1 3096: 73fb strb r3, [r7, #15] 3098: e001 b.n 309e } else { /* JSWSTART bit is reset */ bitstatus = RESET; 309a: 2300 movs r3, #0 309c: 73fb strb r3, [r7, #15] } /* Return the JSWSTART bit status */ return bitstatus; 309e: 7bfb ldrb r3, [r7, #15] } 30a0: 4618 mov r0, r3 30a2: 3714 adds r7, #20 30a4: 46bd mov sp, r7 30a6: bc80 pop {r7} 30a8: 4770 bx lr 000030aa : * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles * @retval None */ void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) { 30aa: b480 push {r7} 30ac: b087 sub sp, #28 30ae: af00 add r7, sp, #0 30b0: 6078 str r0, [r7, #4] 30b2: 4608 mov r0, r1 30b4: 4611 mov r1, r2 30b6: 461a mov r2, r3 30b8: 4603 mov r3, r0 30ba: 70fb strb r3, [r7, #3] 30bc: 460b mov r3, r1 30be: 70bb strb r3, [r7, #2] 30c0: 4613 mov r3, r2 30c2: 707b strb r3, [r7, #1] uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; 30c4: 2300 movs r3, #0 30c6: 617b str r3, [r7, #20] 30c8: 2300 movs r3, #0 30ca: 613b str r3, [r7, #16] 30cc: 2300 movs r3, #0 30ce: 60fb str r3, [r7, #12] assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); assert_param(IS_ADC_INJECTED_RANK(Rank)); assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ if (ADC_Channel > ADC_Channel_9) 30d0: 78fb ldrb r3, [r7, #3] 30d2: 2b09 cmp r3, #9 30d4: d923 bls.n 311e { /* Get the old register value */ tmpreg1 = ADCx->SMPR1; 30d6: 687b ldr r3, [r7, #4] 30d8: 68db ldr r3, [r3, #12] 30da: 617b str r3, [r7, #20] /* Calculate the mask to clear */ tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); 30dc: 78fb ldrb r3, [r7, #3] 30de: f1a3 020a sub.w r2, r3, #10 30e2: 4613 mov r3, r2 30e4: 005b lsls r3, r3, #1 30e6: 4413 add r3, r2 30e8: 2207 movs r2, #7 30ea: fa02 f303 lsl.w r3, r2, r3 30ee: 613b str r3, [r7, #16] /* Clear the old channel sample time */ tmpreg1 &= ~tmpreg2; 30f0: 693b ldr r3, [r7, #16] 30f2: 43db mvns r3, r3 30f4: 697a ldr r2, [r7, #20] 30f6: 4013 ands r3, r2 30f8: 617b str r3, [r7, #20] /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); 30fa: 7879 ldrb r1, [r7, #1] 30fc: 78fb ldrb r3, [r7, #3] 30fe: f1a3 020a sub.w r2, r3, #10 3102: 4613 mov r3, r2 3104: 005b lsls r3, r3, #1 3106: 4413 add r3, r2 3108: fa01 f303 lsl.w r3, r1, r3 310c: 613b str r3, [r7, #16] /* Set the new channel sample time */ tmpreg1 |= tmpreg2; 310e: 697a ldr r2, [r7, #20] 3110: 693b ldr r3, [r7, #16] 3112: 4313 orrs r3, r2 3114: 617b str r3, [r7, #20] /* Store the new register value */ ADCx->SMPR1 = tmpreg1; 3116: 687b ldr r3, [r7, #4] 3118: 697a ldr r2, [r7, #20] 311a: 60da str r2, [r3, #12] 311c: e01e b.n 315c } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Get the old register value */ tmpreg1 = ADCx->SMPR2; 311e: 687b ldr r3, [r7, #4] 3120: 691b ldr r3, [r3, #16] 3122: 617b str r3, [r7, #20] /* Calculate the mask to clear */ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); 3124: 78fa ldrb r2, [r7, #3] 3126: 4613 mov r3, r2 3128: 005b lsls r3, r3, #1 312a: 4413 add r3, r2 312c: 2207 movs r2, #7 312e: fa02 f303 lsl.w r3, r2, r3 3132: 613b str r3, [r7, #16] /* Clear the old channel sample time */ tmpreg1 &= ~tmpreg2; 3134: 693b ldr r3, [r7, #16] 3136: 43db mvns r3, r3 3138: 697a ldr r2, [r7, #20] 313a: 4013 ands r3, r2 313c: 617b str r3, [r7, #20] /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); 313e: 7879 ldrb r1, [r7, #1] 3140: 78fa ldrb r2, [r7, #3] 3142: 4613 mov r3, r2 3144: 005b lsls r3, r3, #1 3146: 4413 add r3, r2 3148: fa01 f303 lsl.w r3, r1, r3 314c: 613b str r3, [r7, #16] /* Set the new channel sample time */ tmpreg1 |= tmpreg2; 314e: 697a ldr r2, [r7, #20] 3150: 693b ldr r3, [r7, #16] 3152: 4313 orrs r3, r2 3154: 617b str r3, [r7, #20] /* Store the new register value */ ADCx->SMPR2 = tmpreg1; 3156: 687b ldr r3, [r7, #4] 3158: 697a ldr r2, [r7, #20] 315a: 611a str r2, [r3, #16] } /* Rank configuration */ /* Get the old register value */ tmpreg1 = ADCx->JSQR; 315c: 687b ldr r3, [r7, #4] 315e: 6b9b ldr r3, [r3, #56] ; 0x38 3160: 617b str r3, [r7, #20] /* Get JL value: Number = JL+1 */ tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; 3162: 697b ldr r3, [r7, #20] 3164: 0d1b lsrs r3, r3, #20 3166: f003 0303 and.w r3, r3, #3 316a: 60fb str r3, [r7, #12] /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); 316c: 68fb ldr r3, [r7, #12] 316e: b2db uxtb r3, r3 3170: 78ba ldrb r2, [r7, #2] 3172: 1ad3 subs r3, r2, r3 3174: b2db uxtb r3, r3 3176: 3302 adds r3, #2 3178: b2db uxtb r3, r3 317a: 461a mov r2, r3 317c: 4613 mov r3, r2 317e: 009b lsls r3, r3, #2 3180: 4413 add r3, r2 3182: 221f movs r2, #31 3184: fa02 f303 lsl.w r3, r2, r3 3188: 613b str r3, [r7, #16] /* Clear the old JSQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; 318a: 693b ldr r3, [r7, #16] 318c: 43db mvns r3, r3 318e: 697a ldr r2, [r7, #20] 3190: 4013 ands r3, r2 3192: 617b str r3, [r7, #20] /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); 3194: 78fa ldrb r2, [r7, #3] 3196: 68fb ldr r3, [r7, #12] 3198: b2db uxtb r3, r3 319a: 78b9 ldrb r1, [r7, #2] 319c: 1acb subs r3, r1, r3 319e: b2db uxtb r3, r3 31a0: 3302 adds r3, #2 31a2: b2db uxtb r3, r3 31a4: 4619 mov r1, r3 31a6: 460b mov r3, r1 31a8: 009b lsls r3, r3, #2 31aa: 440b add r3, r1 31ac: fa02 f303 lsl.w r3, r2, r3 31b0: 613b str r3, [r7, #16] /* Set the JSQx bits for the selected rank */ tmpreg1 |= tmpreg2; 31b2: 697a ldr r2, [r7, #20] 31b4: 693b ldr r3, [r7, #16] 31b6: 4313 orrs r3, r2 31b8: 617b str r3, [r7, #20] /* Store the new register value */ ADCx->JSQR = tmpreg1; 31ba: 687b ldr r3, [r7, #4] 31bc: 697a ldr r2, [r7, #20] 31be: 639a str r2, [r3, #56] ; 0x38 } 31c0: bf00 nop 31c2: 371c adds r7, #28 31c4: 46bd mov sp, r7 31c6: bc80 pop {r7} 31c8: 4770 bx lr 000031ca : * @param Length: The sequencer length. * This parameter must be a number between 1 to 4. * @retval None */ void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) { 31ca: b480 push {r7} 31cc: b085 sub sp, #20 31ce: af00 add r7, sp, #0 31d0: 6078 str r0, [r7, #4] 31d2: 460b mov r3, r1 31d4: 70fb strb r3, [r7, #3] uint32_t tmpreg1 = 0; 31d6: 2300 movs r3, #0 31d8: 60fb str r3, [r7, #12] uint32_t tmpreg2 = 0; 31da: 2300 movs r3, #0 31dc: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_LENGTH(Length)); /* Get the old register value */ tmpreg1 = ADCx->JSQR; 31de: 687b ldr r3, [r7, #4] 31e0: 6b9b ldr r3, [r3, #56] ; 0x38 31e2: 60fb str r3, [r7, #12] /* Clear the old injected sequnence lenght JL bits */ tmpreg1 &= JSQR_JL_Reset; 31e4: 68fb ldr r3, [r7, #12] 31e6: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 31ea: 60fb str r3, [r7, #12] /* Set the injected sequnence lenght JL bits */ tmpreg2 = Length - 1; 31ec: 78fb ldrb r3, [r7, #3] 31ee: 3b01 subs r3, #1 31f0: 60bb str r3, [r7, #8] tmpreg1 |= tmpreg2 << 20; 31f2: 68bb ldr r3, [r7, #8] 31f4: 051b lsls r3, r3, #20 31f6: 68fa ldr r2, [r7, #12] 31f8: 4313 orrs r3, r2 31fa: 60fb str r3, [r7, #12] /* Store the new register value */ ADCx->JSQR = tmpreg1; 31fc: 687b ldr r3, [r7, #4] 31fe: 68fa ldr r2, [r7, #12] 3200: 639a str r2, [r3, #56] ; 0x38 } 3202: bf00 nop 3204: 3714 adds r7, #20 3206: 46bd mov sp, r7 3208: bc80 pop {r7} 320a: 4770 bx lr 0000320c : * @param Offset: the offset value for the selected ADC injected channel * This parameter must be a 12bit value. * @retval None */ void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) { 320c: b480 push {r7} 320e: b085 sub sp, #20 3210: af00 add r7, sp, #0 3212: 6078 str r0, [r7, #4] 3214: 460b mov r3, r1 3216: 70fb strb r3, [r7, #3] 3218: 4613 mov r3, r2 321a: 803b strh r3, [r7, #0] __IO uint32_t tmp = 0; 321c: 2300 movs r3, #0 321e: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); assert_param(IS_ADC_OFFSET(Offset)); tmp = (uint32_t)ADCx; 3220: 687b ldr r3, [r7, #4] 3222: 60fb str r3, [r7, #12] tmp += ADC_InjectedChannel; 3224: 78fa ldrb r2, [r7, #3] 3226: 68fb ldr r3, [r7, #12] 3228: 4413 add r3, r2 322a: 60fb str r3, [r7, #12] /* Set the selected injected channel data offset */ *(__IO uint32_t *) tmp = (uint32_t)Offset; 322c: 68fb ldr r3, [r7, #12] 322e: 461a mov r2, r3 3230: 883b ldrh r3, [r7, #0] 3232: 6013 str r3, [r2, #0] } 3234: bf00 nop 3236: 3714 adds r7, #20 3238: 46bd mov sp, r7 323a: bc80 pop {r7} 323c: 4770 bx lr 0000323e : * @arg ADC_InjectedChannel_3: Injected Channel3 selected * @arg ADC_InjectedChannel_4: Injected Channel4 selected * @retval The Data conversion value. */ uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) { 323e: b480 push {r7} 3240: b085 sub sp, #20 3242: af00 add r7, sp, #0 3244: 6078 str r0, [r7, #4] 3246: 460b mov r3, r1 3248: 70fb strb r3, [r7, #3] __IO uint32_t tmp = 0; 324a: 2300 movs r3, #0 324c: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); tmp = (uint32_t)ADCx; 324e: 687b ldr r3, [r7, #4] 3250: 60fb str r3, [r7, #12] tmp += ADC_InjectedChannel + JDR_Offset; 3252: 78fa ldrb r2, [r7, #3] 3254: 68fb ldr r3, [r7, #12] 3256: 4413 add r3, r2 3258: 3328 adds r3, #40 ; 0x28 325a: 60fb str r3, [r7, #12] /* Returns the selected injected channel conversion data value */ return (uint16_t) (*(__IO uint32_t*) tmp); 325c: 68fb ldr r3, [r7, #12] 325e: 681b ldr r3, [r3, #0] 3260: b29b uxth r3, r3 } 3262: 4618 mov r0, r3 3264: 3714 adds r7, #20 3266: 46bd mov sp, r7 3268: bc80 pop {r7} 326a: 4770 bx lr 0000326c : * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog * @retval None */ void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) { 326c: b480 push {r7} 326e: b085 sub sp, #20 3270: af00 add r7, sp, #0 3272: 6078 str r0, [r7, #4] 3274: 6039 str r1, [r7, #0] uint32_t tmpreg = 0; 3276: 2300 movs r3, #0 3278: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); /* Get the old register value */ tmpreg = ADCx->CR1; 327a: 687b ldr r3, [r7, #4] 327c: 685b ldr r3, [r3, #4] 327e: 60fb str r3, [r7, #12] /* Clear AWDEN, AWDENJ and AWDSGL bits */ tmpreg &= CR1_AWDMode_Reset; 3280: 68fb ldr r3, [r7, #12] 3282: f423 0340 bic.w r3, r3, #12582912 ; 0xc00000 3286: f423 7300 bic.w r3, r3, #512 ; 0x200 328a: 60fb str r3, [r7, #12] /* Set the analog watchdog enable mode */ tmpreg |= ADC_AnalogWatchdog; 328c: 68fa ldr r2, [r7, #12] 328e: 683b ldr r3, [r7, #0] 3290: 4313 orrs r3, r2 3292: 60fb str r3, [r7, #12] /* Store the new register value */ ADCx->CR1 = tmpreg; 3294: 687b ldr r3, [r7, #4] 3296: 68fa ldr r2, [r7, #12] 3298: 605a str r2, [r3, #4] } 329a: bf00 nop 329c: 3714 adds r7, #20 329e: 46bd mov sp, r7 32a0: bc80 pop {r7} 32a2: 4770 bx lr 000032a4 : * This parameter must be a 12bit value. * @retval None */ void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold) { 32a4: b480 push {r7} 32a6: b083 sub sp, #12 32a8: af00 add r7, sp, #0 32aa: 6078 str r0, [r7, #4] 32ac: 460b mov r3, r1 32ae: 807b strh r3, [r7, #2] 32b0: 4613 mov r3, r2 32b2: 803b strh r3, [r7, #0] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_THRESHOLD(HighThreshold)); assert_param(IS_ADC_THRESHOLD(LowThreshold)); /* Set the ADCx high threshold */ ADCx->HTR = HighThreshold; 32b4: 887a ldrh r2, [r7, #2] 32b6: 687b ldr r3, [r7, #4] 32b8: 625a str r2, [r3, #36] ; 0x24 /* Set the ADCx low threshold */ ADCx->LTR = LowThreshold; 32ba: 883a ldrh r2, [r7, #0] 32bc: 687b ldr r3, [r7, #4] 32be: 629a str r2, [r3, #40] ; 0x28 } 32c0: bf00 nop 32c2: 370c adds r7, #12 32c4: 46bd mov sp, r7 32c6: bc80 pop {r7} 32c8: 4770 bx lr 000032ca : * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @retval None */ void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) { 32ca: b480 push {r7} 32cc: b085 sub sp, #20 32ce: af00 add r7, sp, #0 32d0: 6078 str r0, [r7, #4] 32d2: 460b mov r3, r1 32d4: 70fb strb r3, [r7, #3] uint32_t tmpreg = 0; 32d6: 2300 movs r3, #0 32d8: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); /* Get the old register value */ tmpreg = ADCx->CR1; 32da: 687b ldr r3, [r7, #4] 32dc: 685b ldr r3, [r3, #4] 32de: 60fb str r3, [r7, #12] /* Clear the Analog watchdog channel select bits */ tmpreg &= CR1_AWDCH_Reset; 32e0: 68fb ldr r3, [r7, #12] 32e2: f023 031f bic.w r3, r3, #31 32e6: 60fb str r3, [r7, #12] /* Set the Analog watchdog channel */ tmpreg |= ADC_Channel; 32e8: 78fb ldrb r3, [r7, #3] 32ea: 68fa ldr r2, [r7, #12] 32ec: 4313 orrs r3, r2 32ee: 60fb str r3, [r7, #12] /* Store the new register value */ ADCx->CR1 = tmpreg; 32f0: 687b ldr r3, [r7, #4] 32f2: 68fa ldr r2, [r7, #12] 32f4: 605a str r2, [r3, #4] } 32f6: bf00 nop 32f8: 3714 adds r7, #20 32fa: 46bd mov sp, r7 32fc: bc80 pop {r7} 32fe: 4770 bx lr 00003300 : * @param NewState: new state of the temperature sensor. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_TempSensorVrefintCmd(FunctionalState NewState) { 3300: b480 push {r7} 3302: b083 sub sp, #12 3304: af00 add r7, sp, #0 3306: 4603 mov r3, r0 3308: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 330a: 79fb ldrb r3, [r7, #7] 330c: 2b00 cmp r3, #0 330e: d006 beq.n 331e { /* Enable the temperature sensor and Vrefint channel*/ ADC1->CR2 |= CR2_TSVREFE_Set; 3310: 4b08 ldr r3, [pc, #32] ; (3334 ) 3312: 689b ldr r3, [r3, #8] 3314: 4a07 ldr r2, [pc, #28] ; (3334 ) 3316: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 331a: 6093 str r3, [r2, #8] else { /* Disable the temperature sensor and Vrefint channel*/ ADC1->CR2 &= CR2_TSVREFE_Reset; } } 331c: e005 b.n 332a ADC1->CR2 &= CR2_TSVREFE_Reset; 331e: 4b05 ldr r3, [pc, #20] ; (3334 ) 3320: 689b ldr r3, [r3, #8] 3322: 4a04 ldr r2, [pc, #16] ; (3334 ) 3324: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 3328: 6093 str r3, [r2, #8] } 332a: bf00 nop 332c: 370c adds r7, #12 332e: 46bd mov sp, r7 3330: bc80 pop {r7} 3332: 4770 bx lr 3334: 40012400 .word 0x40012400 00003338 : * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag * @arg ADC_FLAG_STRT: Start of regular group conversion flag * @retval The new state of ADC_FLAG (SET or RESET). */ FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) { 3338: b480 push {r7} 333a: b085 sub sp, #20 333c: af00 add r7, sp, #0 333e: 6078 str r0, [r7, #4] 3340: 460b mov r3, r1 3342: 70fb strb r3, [r7, #3] FlagStatus bitstatus = RESET; 3344: 2300 movs r3, #0 3346: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); /* Check the status of the specified ADC flag */ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) 3348: 687b ldr r3, [r7, #4] 334a: 681a ldr r2, [r3, #0] 334c: 78fb ldrb r3, [r7, #3] 334e: 4013 ands r3, r2 3350: 2b00 cmp r3, #0 3352: d002 beq.n 335a { /* ADC_FLAG is set */ bitstatus = SET; 3354: 2301 movs r3, #1 3356: 73fb strb r3, [r7, #15] 3358: e001 b.n 335e } else { /* ADC_FLAG is reset */ bitstatus = RESET; 335a: 2300 movs r3, #0 335c: 73fb strb r3, [r7, #15] } /* Return the ADC_FLAG status */ return bitstatus; 335e: 7bfb ldrb r3, [r7, #15] } 3360: 4618 mov r0, r3 3362: 3714 adds r7, #20 3364: 46bd mov sp, r7 3366: bc80 pop {r7} 3368: 4770 bx lr 0000336a : * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag * @arg ADC_FLAG_STRT: Start of regular group conversion flag * @retval None */ void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) { 336a: b480 push {r7} 336c: b083 sub sp, #12 336e: af00 add r7, sp, #0 3370: 6078 str r0, [r7, #4] 3372: 460b mov r3, r1 3374: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); /* Clear the selected ADC flags */ ADCx->SR = ~(uint32_t)ADC_FLAG; 3376: 78fb ldrb r3, [r7, #3] 3378: 43da mvns r2, r3 337a: 687b ldr r3, [r7, #4] 337c: 601a str r2, [r3, #0] } 337e: bf00 nop 3380: 370c adds r7, #12 3382: 46bd mov sp, r7 3384: bc80 pop {r7} 3386: 4770 bx lr 00003388 : * @arg ADC_IT_AWD: Analog watchdog interrupt mask * @arg ADC_IT_JEOC: End of injected conversion interrupt mask * @retval The new state of ADC_IT (SET or RESET). */ ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) { 3388: b480 push {r7} 338a: b087 sub sp, #28 338c: af00 add r7, sp, #0 338e: 6078 str r0, [r7, #4] 3390: 460b mov r3, r1 3392: 807b strh r3, [r7, #2] ITStatus bitstatus = RESET; 3394: 2300 movs r3, #0 3396: 75fb strb r3, [r7, #23] uint32_t itmask = 0, enablestatus = 0; 3398: 2300 movs r3, #0 339a: 613b str r3, [r7, #16] 339c: 2300 movs r3, #0 339e: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_GET_IT(ADC_IT)); /* Get the ADC IT index */ itmask = ADC_IT >> 8; 33a0: 887b ldrh r3, [r7, #2] 33a2: 0a1b lsrs r3, r3, #8 33a4: b29b uxth r3, r3 33a6: 613b str r3, [r7, #16] /* Get the ADC_IT enable bit status */ enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; 33a8: 687b ldr r3, [r7, #4] 33aa: 685b ldr r3, [r3, #4] 33ac: 887a ldrh r2, [r7, #2] 33ae: b2d2 uxtb r2, r2 33b0: 4013 ands r3, r2 33b2: 60fb str r3, [r7, #12] /* Check the status of the specified ADC interrupt */ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) 33b4: 687b ldr r3, [r7, #4] 33b6: 681a ldr r2, [r3, #0] 33b8: 693b ldr r3, [r7, #16] 33ba: 4013 ands r3, r2 33bc: 2b00 cmp r3, #0 33be: d005 beq.n 33cc 33c0: 68fb ldr r3, [r7, #12] 33c2: 2b00 cmp r3, #0 33c4: d002 beq.n 33cc { /* ADC_IT is set */ bitstatus = SET; 33c6: 2301 movs r3, #1 33c8: 75fb strb r3, [r7, #23] 33ca: e001 b.n 33d0 } else { /* ADC_IT is reset */ bitstatus = RESET; 33cc: 2300 movs r3, #0 33ce: 75fb strb r3, [r7, #23] } /* Return the ADC_IT status */ return bitstatus; 33d0: 7dfb ldrb r3, [r7, #23] } 33d2: 4618 mov r0, r3 33d4: 371c adds r7, #28 33d6: 46bd mov sp, r7 33d8: bc80 pop {r7} 33da: 4770 bx lr 000033dc : * @arg ADC_IT_AWD: Analog watchdog interrupt mask * @arg ADC_IT_JEOC: End of injected conversion interrupt mask * @retval None */ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) { 33dc: b480 push {r7} 33de: b085 sub sp, #20 33e0: af00 add r7, sp, #0 33e2: 6078 str r0, [r7, #4] 33e4: 460b mov r3, r1 33e6: 807b strh r3, [r7, #2] uint8_t itmask = 0; 33e8: 2300 movs r3, #0 33ea: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = (uint8_t)(ADC_IT >> 8); 33ec: 887b ldrh r3, [r7, #2] 33ee: 0a1b lsrs r3, r3, #8 33f0: b29b uxth r3, r3 33f2: 73fb strb r3, [r7, #15] /* Clear the selected ADC interrupt pending bits */ ADCx->SR = ~(uint32_t)itmask; 33f4: 7bfb ldrb r3, [r7, #15] 33f6: 43da mvns r2, r3 33f8: 687b ldr r3, [r7, #4] 33fa: 601a str r2, [r3, #0] } 33fc: bf00 nop 33fe: 3714 adds r7, #20 3400: 46bd mov sp, r7 3402: bc80 pop {r7} 3404: 4770 bx lr 3406: bf00 nop 00003408 : * @brief Deinitializes the TIMx peripheral registers to their default reset values. * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. * @retval None */ void TIM_DeInit(TIM_TypeDef* TIMx) { 3408: b580 push {r7, lr} 340a: b082 sub sp, #8 340c: af00 add r7, sp, #0 340e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); if (TIMx == TIM1) 3410: 687b ldr r3, [r7, #4] 3412: 4a78 ldr r2, [pc, #480] ; (35f4 ) 3414: 4293 cmp r3, r2 3416: d10a bne.n 342e { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); 3418: 2101 movs r1, #1 341a: f44f 6000 mov.w r0, #2048 ; 0x800 341e: f7fe f9af bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); 3422: 2100 movs r1, #0 3424: f44f 6000 mov.w r0, #2048 ; 0x800 3428: f7fe f9aa bl 1780 { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); } } } 342c: e0de b.n 35ec else if (TIMx == TIM2) 342e: 687b ldr r3, [r7, #4] 3430: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 3434: d108 bne.n 3448 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); 3436: 2101 movs r1, #1 3438: 2001 movs r0, #1 343a: f7fe f9bf bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); 343e: 2100 movs r1, #0 3440: 2001 movs r0, #1 3442: f7fe f9bb bl 17bc } 3446: e0d1 b.n 35ec else if (TIMx == TIM3) 3448: 687b ldr r3, [r7, #4] 344a: 4a6b ldr r2, [pc, #428] ; (35f8 ) 344c: 4293 cmp r3, r2 344e: d108 bne.n 3462 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); 3450: 2101 movs r1, #1 3452: 2002 movs r0, #2 3454: f7fe f9b2 bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); 3458: 2100 movs r1, #0 345a: 2002 movs r0, #2 345c: f7fe f9ae bl 17bc } 3460: e0c4 b.n 35ec else if (TIMx == TIM4) 3462: 687b ldr r3, [r7, #4] 3464: 4a65 ldr r2, [pc, #404] ; (35fc ) 3466: 4293 cmp r3, r2 3468: d108 bne.n 347c RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); 346a: 2101 movs r1, #1 346c: 2004 movs r0, #4 346e: f7fe f9a5 bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); 3472: 2100 movs r1, #0 3474: 2004 movs r0, #4 3476: f7fe f9a1 bl 17bc } 347a: e0b7 b.n 35ec else if (TIMx == TIM5) 347c: 687b ldr r3, [r7, #4] 347e: 4a60 ldr r2, [pc, #384] ; (3600 ) 3480: 4293 cmp r3, r2 3482: d108 bne.n 3496 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); 3484: 2101 movs r1, #1 3486: 2008 movs r0, #8 3488: f7fe f998 bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); 348c: 2100 movs r1, #0 348e: 2008 movs r0, #8 3490: f7fe f994 bl 17bc } 3494: e0aa b.n 35ec else if (TIMx == TIM6) 3496: 687b ldr r3, [r7, #4] 3498: 4a5a ldr r2, [pc, #360] ; (3604 ) 349a: 4293 cmp r3, r2 349c: d108 bne.n 34b0 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); 349e: 2101 movs r1, #1 34a0: 2010 movs r0, #16 34a2: f7fe f98b bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); 34a6: 2100 movs r1, #0 34a8: 2010 movs r0, #16 34aa: f7fe f987 bl 17bc } 34ae: e09d b.n 35ec else if (TIMx == TIM7) 34b0: 687b ldr r3, [r7, #4] 34b2: 4a55 ldr r2, [pc, #340] ; (3608 ) 34b4: 4293 cmp r3, r2 34b6: d108 bne.n 34ca RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); 34b8: 2101 movs r1, #1 34ba: 2020 movs r0, #32 34bc: f7fe f97e bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); 34c0: 2100 movs r1, #0 34c2: 2020 movs r0, #32 34c4: f7fe f97a bl 17bc } 34c8: e090 b.n 35ec else if (TIMx == TIM8) 34ca: 687b ldr r3, [r7, #4] 34cc: 4a4f ldr r2, [pc, #316] ; (360c ) 34ce: 4293 cmp r3, r2 34d0: d10a bne.n 34e8 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); 34d2: 2101 movs r1, #1 34d4: f44f 5000 mov.w r0, #8192 ; 0x2000 34d8: f7fe f952 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); 34dc: 2100 movs r1, #0 34de: f44f 5000 mov.w r0, #8192 ; 0x2000 34e2: f7fe f94d bl 1780 } 34e6: e081 b.n 35ec else if (TIMx == TIM9) 34e8: 687b ldr r3, [r7, #4] 34ea: 4a49 ldr r2, [pc, #292] ; (3610 ) 34ec: 4293 cmp r3, r2 34ee: d10a bne.n 3506 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); 34f0: 2101 movs r1, #1 34f2: f44f 2000 mov.w r0, #524288 ; 0x80000 34f6: f7fe f943 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); 34fa: 2100 movs r1, #0 34fc: f44f 2000 mov.w r0, #524288 ; 0x80000 3500: f7fe f93e bl 1780 } 3504: e072 b.n 35ec else if (TIMx == TIM10) 3506: 687b ldr r3, [r7, #4] 3508: 4a42 ldr r2, [pc, #264] ; (3614 ) 350a: 4293 cmp r3, r2 350c: d10a bne.n 3524 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); 350e: 2101 movs r1, #1 3510: f44f 1080 mov.w r0, #1048576 ; 0x100000 3514: f7fe f934 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); 3518: 2100 movs r1, #0 351a: f44f 1080 mov.w r0, #1048576 ; 0x100000 351e: f7fe f92f bl 1780 } 3522: e063 b.n 35ec else if (TIMx == TIM11) 3524: 687b ldr r3, [r7, #4] 3526: 4a3c ldr r2, [pc, #240] ; (3618 ) 3528: 4293 cmp r3, r2 352a: d10a bne.n 3542 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); 352c: 2101 movs r1, #1 352e: f44f 1000 mov.w r0, #2097152 ; 0x200000 3532: f7fe f925 bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); 3536: 2100 movs r1, #0 3538: f44f 1000 mov.w r0, #2097152 ; 0x200000 353c: f7fe f920 bl 1780 } 3540: e054 b.n 35ec else if (TIMx == TIM12) 3542: 687b ldr r3, [r7, #4] 3544: 4a35 ldr r2, [pc, #212] ; (361c ) 3546: 4293 cmp r3, r2 3548: d108 bne.n 355c RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); 354a: 2101 movs r1, #1 354c: 2040 movs r0, #64 ; 0x40 354e: f7fe f935 bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); 3552: 2100 movs r1, #0 3554: 2040 movs r0, #64 ; 0x40 3556: f7fe f931 bl 17bc } 355a: e047 b.n 35ec else if (TIMx == TIM13) 355c: 687b ldr r3, [r7, #4] 355e: 4a30 ldr r2, [pc, #192] ; (3620 ) 3560: 4293 cmp r3, r2 3562: d108 bne.n 3576 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); 3564: 2101 movs r1, #1 3566: 2080 movs r0, #128 ; 0x80 3568: f7fe f928 bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); 356c: 2100 movs r1, #0 356e: 2080 movs r0, #128 ; 0x80 3570: f7fe f924 bl 17bc } 3574: e03a b.n 35ec else if (TIMx == TIM14) 3576: 687b ldr r3, [r7, #4] 3578: 4a2a ldr r2, [pc, #168] ; (3624 ) 357a: 4293 cmp r3, r2 357c: d10a bne.n 3594 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); 357e: 2101 movs r1, #1 3580: f44f 7080 mov.w r0, #256 ; 0x100 3584: f7fe f91a bl 17bc RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); 3588: 2100 movs r1, #0 358a: f44f 7080 mov.w r0, #256 ; 0x100 358e: f7fe f915 bl 17bc } 3592: e02b b.n 35ec else if (TIMx == TIM15) 3594: 687b ldr r3, [r7, #4] 3596: 4a24 ldr r2, [pc, #144] ; (3628 ) 3598: 4293 cmp r3, r2 359a: d10a bne.n 35b2 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); 359c: 2101 movs r1, #1 359e: f44f 3080 mov.w r0, #65536 ; 0x10000 35a2: f7fe f8ed bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); 35a6: 2100 movs r1, #0 35a8: f44f 3080 mov.w r0, #65536 ; 0x10000 35ac: f7fe f8e8 bl 1780 } 35b0: e01c b.n 35ec else if (TIMx == TIM16) 35b2: 687b ldr r3, [r7, #4] 35b4: 4a1d ldr r2, [pc, #116] ; (362c ) 35b6: 4293 cmp r3, r2 35b8: d10a bne.n 35d0 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); 35ba: 2101 movs r1, #1 35bc: f44f 3000 mov.w r0, #131072 ; 0x20000 35c0: f7fe f8de bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); 35c4: 2100 movs r1, #0 35c6: f44f 3000 mov.w r0, #131072 ; 0x20000 35ca: f7fe f8d9 bl 1780 } 35ce: e00d b.n 35ec if (TIMx == TIM17) 35d0: 687b ldr r3, [r7, #4] 35d2: 4a17 ldr r2, [pc, #92] ; (3630 ) 35d4: 4293 cmp r3, r2 35d6: d109 bne.n 35ec RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); 35d8: 2101 movs r1, #1 35da: f44f 2080 mov.w r0, #262144 ; 0x40000 35de: f7fe f8cf bl 1780 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); 35e2: 2100 movs r1, #0 35e4: f44f 2080 mov.w r0, #262144 ; 0x40000 35e8: f7fe f8ca bl 1780 } 35ec: bf00 nop 35ee: 3708 adds r7, #8 35f0: 46bd mov sp, r7 35f2: bd80 pop {r7, pc} 35f4: 40012c00 .word 0x40012c00 35f8: 40000400 .word 0x40000400 35fc: 40000800 .word 0x40000800 3600: 40000c00 .word 0x40000c00 3604: 40001000 .word 0x40001000 3608: 40001400 .word 0x40001400 360c: 40013400 .word 0x40013400 3610: 40014c00 .word 0x40014c00 3614: 40015000 .word 0x40015000 3618: 40015400 .word 0x40015400 361c: 40001800 .word 0x40001800 3620: 40001c00 .word 0x40001c00 3624: 40002000 .word 0x40002000 3628: 40014000 .word 0x40014000 362c: 40014400 .word 0x40014400 3630: 40014800 .word 0x40014800 00003634 : * structure that contains the configuration information for the * specified TIM peripheral. * @retval None */ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) { 3634: b480 push {r7} 3636: b085 sub sp, #20 3638: af00 add r7, sp, #0 363a: 6078 str r0, [r7, #4] 363c: 6039 str r1, [r7, #0] uint16_t tmpcr1 = 0; 363e: 2300 movs r3, #0 3640: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); tmpcr1 = TIMx->CR1; 3642: 687b ldr r3, [r7, #4] 3644: 881b ldrh r3, [r3, #0] 3646: 81fb strh r3, [r7, #14] if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| 3648: 687b ldr r3, [r7, #4] 364a: 4a2e ldr r2, [pc, #184] ; (3704 ) 364c: 4293 cmp r3, r2 364e: d013 beq.n 3678 3650: 687b ldr r3, [r7, #4] 3652: 4a2d ldr r2, [pc, #180] ; (3708 ) 3654: 4293 cmp r3, r2 3656: d00f beq.n 3678 3658: 687b ldr r3, [r7, #4] 365a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 365e: d00b beq.n 3678 3660: 687b ldr r3, [r7, #4] 3662: 4a2a ldr r2, [pc, #168] ; (370c ) 3664: 4293 cmp r3, r2 3666: d007 beq.n 3678 3668: 687b ldr r3, [r7, #4] 366a: 4a29 ldr r2, [pc, #164] ; (3710 ) 366c: 4293 cmp r3, r2 366e: d003 beq.n 3678 (TIMx == TIM4) || (TIMx == TIM5)) 3670: 687b ldr r3, [r7, #4] 3672: 4a28 ldr r2, [pc, #160] ; (3714 ) 3674: 4293 cmp r3, r2 3676: d108 bne.n 368a { /* Select the Counter Mode */ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); 3678: 89fb ldrh r3, [r7, #14] 367a: f023 0370 bic.w r3, r3, #112 ; 0x70 367e: 81fb strh r3, [r7, #14] tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; 3680: 683b ldr r3, [r7, #0] 3682: 885a ldrh r2, [r3, #2] 3684: 89fb ldrh r3, [r7, #14] 3686: 4313 orrs r3, r2 3688: 81fb strh r3, [r7, #14] } if((TIMx != TIM6) && (TIMx != TIM7)) 368a: 687b ldr r3, [r7, #4] 368c: 4a22 ldr r2, [pc, #136] ; (3718 ) 368e: 4293 cmp r3, r2 3690: d00c beq.n 36ac 3692: 687b ldr r3, [r7, #4] 3694: 4a21 ldr r2, [pc, #132] ; (371c ) 3696: 4293 cmp r3, r2 3698: d008 beq.n 36ac { /* Set the clock division */ tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); 369a: 89fb ldrh r3, [r7, #14] 369c: f423 7340 bic.w r3, r3, #768 ; 0x300 36a0: 81fb strh r3, [r7, #14] tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; 36a2: 683b ldr r3, [r7, #0] 36a4: 88da ldrh r2, [r3, #6] 36a6: 89fb ldrh r3, [r7, #14] 36a8: 4313 orrs r3, r2 36aa: 81fb strh r3, [r7, #14] } TIMx->CR1 = tmpcr1; 36ac: 687b ldr r3, [r7, #4] 36ae: 89fa ldrh r2, [r7, #14] 36b0: 801a strh r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; 36b2: 683b ldr r3, [r7, #0] 36b4: 889a ldrh r2, [r3, #4] 36b6: 687b ldr r3, [r7, #4] 36b8: 859a strh r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; 36ba: 683b ldr r3, [r7, #0] 36bc: 881a ldrh r2, [r3, #0] 36be: 687b ldr r3, [r7, #4] 36c0: 851a strh r2, [r3, #40] ; 0x28 if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) 36c2: 687b ldr r3, [r7, #4] 36c4: 4a0f ldr r2, [pc, #60] ; (3704 ) 36c6: 4293 cmp r3, r2 36c8: d00f beq.n 36ea 36ca: 687b ldr r3, [r7, #4] 36cc: 4a0e ldr r2, [pc, #56] ; (3708 ) 36ce: 4293 cmp r3, r2 36d0: d00b beq.n 36ea 36d2: 687b ldr r3, [r7, #4] 36d4: 4a12 ldr r2, [pc, #72] ; (3720 ) 36d6: 4293 cmp r3, r2 36d8: d007 beq.n 36ea 36da: 687b ldr r3, [r7, #4] 36dc: 4a11 ldr r2, [pc, #68] ; (3724 ) 36de: 4293 cmp r3, r2 36e0: d003 beq.n 36ea 36e2: 687b ldr r3, [r7, #4] 36e4: 4a10 ldr r2, [pc, #64] ; (3728 ) 36e6: 4293 cmp r3, r2 36e8: d104 bne.n 36f4 { /* Set the Repetition Counter value */ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; 36ea: 683b ldr r3, [r7, #0] 36ec: 7a1b ldrb r3, [r3, #8] 36ee: b29a uxth r2, r3 36f0: 687b ldr r3, [r7, #4] 36f2: 861a strh r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the Repetition counter values immediately */ TIMx->EGR = TIM_PSCReloadMode_Immediate; 36f4: 687b ldr r3, [r7, #4] 36f6: 2201 movs r2, #1 36f8: 829a strh r2, [r3, #20] } 36fa: bf00 nop 36fc: 3714 adds r7, #20 36fe: 46bd mov sp, r7 3700: bc80 pop {r7} 3702: 4770 bx lr 3704: 40012c00 .word 0x40012c00 3708: 40013400 .word 0x40013400 370c: 40000400 .word 0x40000400 3710: 40000800 .word 0x40000800 3714: 40000c00 .word 0x40000c00 3718: 40001000 .word 0x40001000 371c: 40001400 .word 0x40001400 3720: 40014000 .word 0x40014000 3724: 40014400 .word 0x40014400 3728: 40014800 .word 0x40014800 0000372c : * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { 372c: b480 push {r7} 372e: b085 sub sp, #20 3730: af00 add r7, sp, #0 3732: 6078 str r0, [r7, #4] 3734: 6039 str r1, [r7, #0] uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 3736: 2300 movs r3, #0 3738: 817b strh r3, [r7, #10] 373a: 2300 movs r3, #0 373c: 81fb strh r3, [r7, #14] 373e: 2300 movs r3, #0 3740: 81bb strh r3, [r7, #12] assert_param(IS_TIM_LIST8_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); 3742: 687b ldr r3, [r7, #4] 3744: 8c1b ldrh r3, [r3, #32] 3746: b29b uxth r3, r3 3748: f023 0301 bic.w r3, r3, #1 374c: b29a uxth r2, r3 374e: 687b ldr r3, [r7, #4] 3750: 841a strh r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 3752: 687b ldr r3, [r7, #4] 3754: 8c1b ldrh r3, [r3, #32] 3756: 81fb strh r3, [r7, #14] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 3758: 687b ldr r3, [r7, #4] 375a: 889b ldrh r3, [r3, #4] 375c: 81bb strh r3, [r7, #12] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 375e: 687b ldr r3, [r7, #4] 3760: 8b1b ldrh r3, [r3, #24] 3762: 817b strh r3, [r7, #10] /* Reset the Output Compare Mode Bits */ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); 3764: 897b ldrh r3, [r7, #10] 3766: f023 0370 bic.w r3, r3, #112 ; 0x70 376a: 817b strh r3, [r7, #10] tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); 376c: 897b ldrh r3, [r7, #10] 376e: f023 0303 bic.w r3, r3, #3 3772: 817b strh r3, [r7, #10] /* Select the Output Compare Mode */ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; 3774: 683b ldr r3, [r7, #0] 3776: 881a ldrh r2, [r3, #0] 3778: 897b ldrh r3, [r7, #10] 377a: 4313 orrs r3, r2 377c: 817b strh r3, [r7, #10] /* Reset the Output Polarity level */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); 377e: 89fb ldrh r3, [r7, #14] 3780: f023 0302 bic.w r3, r3, #2 3784: 81fb strh r3, [r7, #14] /* Set the Output Compare Polarity */ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; 3786: 683b ldr r3, [r7, #0] 3788: 891a ldrh r2, [r3, #8] 378a: 89fb ldrh r3, [r7, #14] 378c: 4313 orrs r3, r2 378e: 81fb strh r3, [r7, #14] /* Set the Output State */ tmpccer |= TIM_OCInitStruct->TIM_OutputState; 3790: 683b ldr r3, [r7, #0] 3792: 885a ldrh r2, [r3, #2] 3794: 89fb ldrh r3, [r7, #14] 3796: 4313 orrs r3, r2 3798: 81fb strh r3, [r7, #14] if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| 379a: 687b ldr r3, [r7, #4] 379c: 4a24 ldr r2, [pc, #144] ; (3830 ) 379e: 4293 cmp r3, r2 37a0: d00f beq.n 37c2 37a2: 687b ldr r3, [r7, #4] 37a4: 4a23 ldr r2, [pc, #140] ; (3834 ) 37a6: 4293 cmp r3, r2 37a8: d00b beq.n 37c2 37aa: 687b ldr r3, [r7, #4] 37ac: 4a22 ldr r2, [pc, #136] ; (3838 ) 37ae: 4293 cmp r3, r2 37b0: d007 beq.n 37c2 37b2: 687b ldr r3, [r7, #4] 37b4: 4a21 ldr r2, [pc, #132] ; (383c ) 37b6: 4293 cmp r3, r2 37b8: d003 beq.n 37c2 (TIMx == TIM16)|| (TIMx == TIM17)) 37ba: 687b ldr r3, [r7, #4] 37bc: 4a20 ldr r2, [pc, #128] ; (3840 ) 37be: 4293 cmp r3, r2 37c0: d123 bne.n 380a assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); 37c2: 89fb ldrh r3, [r7, #14] 37c4: f023 0308 bic.w r3, r3, #8 37c8: 81fb strh r3, [r7, #14] /* Set the Output N Polarity */ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; 37ca: 683b ldr r3, [r7, #0] 37cc: 895a ldrh r2, [r3, #10] 37ce: 89fb ldrh r3, [r7, #14] 37d0: 4313 orrs r3, r2 37d2: 81fb strh r3, [r7, #14] /* Reset the Output N State */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); 37d4: 89fb ldrh r3, [r7, #14] 37d6: f023 0304 bic.w r3, r3, #4 37da: 81fb strh r3, [r7, #14] /* Set the Output N State */ tmpccer |= TIM_OCInitStruct->TIM_OutputNState; 37dc: 683b ldr r3, [r7, #0] 37de: 889a ldrh r2, [r3, #4] 37e0: 89fb ldrh r3, [r7, #14] 37e2: 4313 orrs r3, r2 37e4: 81fb strh r3, [r7, #14] /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); 37e6: 89bb ldrh r3, [r7, #12] 37e8: f423 7380 bic.w r3, r3, #256 ; 0x100 37ec: 81bb strh r3, [r7, #12] tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); 37ee: 89bb ldrh r3, [r7, #12] 37f0: f423 7300 bic.w r3, r3, #512 ; 0x200 37f4: 81bb strh r3, [r7, #12] /* Set the Output Idle state */ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; 37f6: 683b ldr r3, [r7, #0] 37f8: 899a ldrh r2, [r3, #12] 37fa: 89bb ldrh r3, [r7, #12] 37fc: 4313 orrs r3, r2 37fe: 81bb strh r3, [r7, #12] /* Set the Output N Idle state */ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; 3800: 683b ldr r3, [r7, #0] 3802: 89da ldrh r2, [r3, #14] 3804: 89bb ldrh r3, [r7, #12] 3806: 4313 orrs r3, r2 3808: 81bb strh r3, [r7, #12] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 380a: 687b ldr r3, [r7, #4] 380c: 89ba ldrh r2, [r7, #12] 380e: 809a strh r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 3810: 687b ldr r3, [r7, #4] 3812: 897a ldrh r2, [r7, #10] 3814: 831a strh r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 3816: 683b ldr r3, [r7, #0] 3818: 88da ldrh r2, [r3, #6] 381a: 687b ldr r3, [r7, #4] 381c: 869a strh r2, [r3, #52] ; 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 381e: 687b ldr r3, [r7, #4] 3820: 89fa ldrh r2, [r7, #14] 3822: 841a strh r2, [r3, #32] } 3824: bf00 nop 3826: 3714 adds r7, #20 3828: 46bd mov sp, r7 382a: bc80 pop {r7} 382c: 4770 bx lr 382e: bf00 nop 3830: 40012c00 .word 0x40012c00 3834: 40013400 .word 0x40013400 3838: 40014000 .word 0x40014000 383c: 40014400 .word 0x40014400 3840: 40014800 .word 0x40014800 00003844 : * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { 3844: b480 push {r7} 3846: b085 sub sp, #20 3848: af00 add r7, sp, #0 384a: 6078 str r0, [r7, #4] 384c: 6039 str r1, [r7, #0] uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 384e: 2300 movs r3, #0 3850: 817b strh r3, [r7, #10] 3852: 2300 movs r3, #0 3854: 81fb strh r3, [r7, #14] 3856: 2300 movs r3, #0 3858: 81bb strh r3, [r7, #12] assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); 385a: 687b ldr r3, [r7, #4] 385c: 8c1b ldrh r3, [r3, #32] 385e: b29b uxth r3, r3 3860: f023 0310 bic.w r3, r3, #16 3864: b29a uxth r2, r3 3866: 687b ldr r3, [r7, #4] 3868: 841a strh r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 386a: 687b ldr r3, [r7, #4] 386c: 8c1b ldrh r3, [r3, #32] 386e: 81fb strh r3, [r7, #14] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 3870: 687b ldr r3, [r7, #4] 3872: 889b ldrh r3, [r3, #4] 3874: 81bb strh r3, [r7, #12] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 3876: 687b ldr r3, [r7, #4] 3878: 8b1b ldrh r3, [r3, #24] 387a: 817b strh r3, [r7, #10] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); 387c: 897b ldrh r3, [r7, #10] 387e: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 3882: 817b strh r3, [r7, #10] tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); 3884: 897b ldrh r3, [r7, #10] 3886: f423 7340 bic.w r3, r3, #768 ; 0x300 388a: 817b strh r3, [r7, #10] /* Select the Output Compare Mode */ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); 388c: 683b ldr r3, [r7, #0] 388e: 881b ldrh r3, [r3, #0] 3890: 021b lsls r3, r3, #8 3892: b29a uxth r2, r3 3894: 897b ldrh r3, [r7, #10] 3896: 4313 orrs r3, r2 3898: 817b strh r3, [r7, #10] /* Reset the Output Polarity level */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); 389a: 89fb ldrh r3, [r7, #14] 389c: f023 0320 bic.w r3, r3, #32 38a0: 81fb strh r3, [r7, #14] /* Set the Output Compare Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); 38a2: 683b ldr r3, [r7, #0] 38a4: 891b ldrh r3, [r3, #8] 38a6: 011b lsls r3, r3, #4 38a8: b29a uxth r2, r3 38aa: 89fb ldrh r3, [r7, #14] 38ac: 4313 orrs r3, r2 38ae: 81fb strh r3, [r7, #14] /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); 38b0: 683b ldr r3, [r7, #0] 38b2: 885b ldrh r3, [r3, #2] 38b4: 011b lsls r3, r3, #4 38b6: b29a uxth r2, r3 38b8: 89fb ldrh r3, [r7, #14] 38ba: 4313 orrs r3, r2 38bc: 81fb strh r3, [r7, #14] if((TIMx == TIM1) || (TIMx == TIM8)) 38be: 687b ldr r3, [r7, #4] 38c0: 4a22 ldr r2, [pc, #136] ; (394c ) 38c2: 4293 cmp r3, r2 38c4: d003 beq.n 38ce 38c6: 687b ldr r3, [r7, #4] 38c8: 4a21 ldr r2, [pc, #132] ; (3950 ) 38ca: 4293 cmp r3, r2 38cc: d12b bne.n 3926 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); 38ce: 89fb ldrh r3, [r7, #14] 38d0: f023 0380 bic.w r3, r3, #128 ; 0x80 38d4: 81fb strh r3, [r7, #14] /* Set the Output N Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); 38d6: 683b ldr r3, [r7, #0] 38d8: 895b ldrh r3, [r3, #10] 38da: 011b lsls r3, r3, #4 38dc: b29a uxth r2, r3 38de: 89fb ldrh r3, [r7, #14] 38e0: 4313 orrs r3, r2 38e2: 81fb strh r3, [r7, #14] /* Reset the Output N State */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); 38e4: 89fb ldrh r3, [r7, #14] 38e6: f023 0340 bic.w r3, r3, #64 ; 0x40 38ea: 81fb strh r3, [r7, #14] /* Set the Output N State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); 38ec: 683b ldr r3, [r7, #0] 38ee: 889b ldrh r3, [r3, #4] 38f0: 011b lsls r3, r3, #4 38f2: b29a uxth r2, r3 38f4: 89fb ldrh r3, [r7, #14] 38f6: 4313 orrs r3, r2 38f8: 81fb strh r3, [r7, #14] /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); 38fa: 89bb ldrh r3, [r7, #12] 38fc: f423 6380 bic.w r3, r3, #1024 ; 0x400 3900: 81bb strh r3, [r7, #12] tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); 3902: 89bb ldrh r3, [r7, #12] 3904: f423 6300 bic.w r3, r3, #2048 ; 0x800 3908: 81bb strh r3, [r7, #12] /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); 390a: 683b ldr r3, [r7, #0] 390c: 899b ldrh r3, [r3, #12] 390e: 009b lsls r3, r3, #2 3910: b29a uxth r2, r3 3912: 89bb ldrh r3, [r7, #12] 3914: 4313 orrs r3, r2 3916: 81bb strh r3, [r7, #12] /* Set the Output N Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); 3918: 683b ldr r3, [r7, #0] 391a: 89db ldrh r3, [r3, #14] 391c: 009b lsls r3, r3, #2 391e: b29a uxth r2, r3 3920: 89bb ldrh r3, [r7, #12] 3922: 4313 orrs r3, r2 3924: 81bb strh r3, [r7, #12] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 3926: 687b ldr r3, [r7, #4] 3928: 89ba ldrh r2, [r7, #12] 392a: 809a strh r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 392c: 687b ldr r3, [r7, #4] 392e: 897a ldrh r2, [r7, #10] 3930: 831a strh r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; 3932: 683b ldr r3, [r7, #0] 3934: 88da ldrh r2, [r3, #6] 3936: 687b ldr r3, [r7, #4] 3938: 871a strh r2, [r3, #56] ; 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 393a: 687b ldr r3, [r7, #4] 393c: 89fa ldrh r2, [r7, #14] 393e: 841a strh r2, [r3, #32] } 3940: bf00 nop 3942: 3714 adds r7, #20 3944: 46bd mov sp, r7 3946: bc80 pop {r7} 3948: 4770 bx lr 394a: bf00 nop 394c: 40012c00 .word 0x40012c00 3950: 40013400 .word 0x40013400 00003954 : * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { 3954: b480 push {r7} 3956: b085 sub sp, #20 3958: af00 add r7, sp, #0 395a: 6078 str r0, [r7, #4] 395c: 6039 str r1, [r7, #0] uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 395e: 2300 movs r3, #0 3960: 817b strh r3, [r7, #10] 3962: 2300 movs r3, #0 3964: 81fb strh r3, [r7, #14] 3966: 2300 movs r3, #0 3968: 81bb strh r3, [r7, #12] assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); 396a: 687b ldr r3, [r7, #4] 396c: 8c1b ldrh r3, [r3, #32] 396e: b29b uxth r3, r3 3970: f423 7380 bic.w r3, r3, #256 ; 0x100 3974: b29a uxth r2, r3 3976: 687b ldr r3, [r7, #4] 3978: 841a strh r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 397a: 687b ldr r3, [r7, #4] 397c: 8c1b ldrh r3, [r3, #32] 397e: 81fb strh r3, [r7, #14] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 3980: 687b ldr r3, [r7, #4] 3982: 889b ldrh r3, [r3, #4] 3984: 81bb strh r3, [r7, #12] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 3986: 687b ldr r3, [r7, #4] 3988: 8b9b ldrh r3, [r3, #28] 398a: 817b strh r3, [r7, #10] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); 398c: 897b ldrh r3, [r7, #10] 398e: f023 0370 bic.w r3, r3, #112 ; 0x70 3992: 817b strh r3, [r7, #10] tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); 3994: 897b ldrh r3, [r7, #10] 3996: f023 0303 bic.w r3, r3, #3 399a: 817b strh r3, [r7, #10] /* Select the Output Compare Mode */ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; 399c: 683b ldr r3, [r7, #0] 399e: 881a ldrh r2, [r3, #0] 39a0: 897b ldrh r3, [r7, #10] 39a2: 4313 orrs r3, r2 39a4: 817b strh r3, [r7, #10] /* Reset the Output Polarity level */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); 39a6: 89fb ldrh r3, [r7, #14] 39a8: f423 7300 bic.w r3, r3, #512 ; 0x200 39ac: 81fb strh r3, [r7, #14] /* Set the Output Compare Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); 39ae: 683b ldr r3, [r7, #0] 39b0: 891b ldrh r3, [r3, #8] 39b2: 021b lsls r3, r3, #8 39b4: b29a uxth r2, r3 39b6: 89fb ldrh r3, [r7, #14] 39b8: 4313 orrs r3, r2 39ba: 81fb strh r3, [r7, #14] /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); 39bc: 683b ldr r3, [r7, #0] 39be: 885b ldrh r3, [r3, #2] 39c0: 021b lsls r3, r3, #8 39c2: b29a uxth r2, r3 39c4: 89fb ldrh r3, [r7, #14] 39c6: 4313 orrs r3, r2 39c8: 81fb strh r3, [r7, #14] if((TIMx == TIM1) || (TIMx == TIM8)) 39ca: 687b ldr r3, [r7, #4] 39cc: 4a22 ldr r2, [pc, #136] ; (3a58 ) 39ce: 4293 cmp r3, r2 39d0: d003 beq.n 39da 39d2: 687b ldr r3, [r7, #4] 39d4: 4a21 ldr r2, [pc, #132] ; (3a5c ) 39d6: 4293 cmp r3, r2 39d8: d12b bne.n 3a32 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); 39da: 89fb ldrh r3, [r7, #14] 39dc: f423 6300 bic.w r3, r3, #2048 ; 0x800 39e0: 81fb strh r3, [r7, #14] /* Set the Output N Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); 39e2: 683b ldr r3, [r7, #0] 39e4: 895b ldrh r3, [r3, #10] 39e6: 021b lsls r3, r3, #8 39e8: b29a uxth r2, r3 39ea: 89fb ldrh r3, [r7, #14] 39ec: 4313 orrs r3, r2 39ee: 81fb strh r3, [r7, #14] /* Reset the Output N State */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); 39f0: 89fb ldrh r3, [r7, #14] 39f2: f423 6380 bic.w r3, r3, #1024 ; 0x400 39f6: 81fb strh r3, [r7, #14] /* Set the Output N State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); 39f8: 683b ldr r3, [r7, #0] 39fa: 889b ldrh r3, [r3, #4] 39fc: 021b lsls r3, r3, #8 39fe: b29a uxth r2, r3 3a00: 89fb ldrh r3, [r7, #14] 3a02: 4313 orrs r3, r2 3a04: 81fb strh r3, [r7, #14] /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); 3a06: 89bb ldrh r3, [r7, #12] 3a08: f423 5380 bic.w r3, r3, #4096 ; 0x1000 3a0c: 81bb strh r3, [r7, #12] tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); 3a0e: 89bb ldrh r3, [r7, #12] 3a10: f423 5300 bic.w r3, r3, #8192 ; 0x2000 3a14: 81bb strh r3, [r7, #12] /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); 3a16: 683b ldr r3, [r7, #0] 3a18: 899b ldrh r3, [r3, #12] 3a1a: 011b lsls r3, r3, #4 3a1c: b29a uxth r2, r3 3a1e: 89bb ldrh r3, [r7, #12] 3a20: 4313 orrs r3, r2 3a22: 81bb strh r3, [r7, #12] /* Set the Output N Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); 3a24: 683b ldr r3, [r7, #0] 3a26: 89db ldrh r3, [r3, #14] 3a28: 011b lsls r3, r3, #4 3a2a: b29a uxth r2, r3 3a2c: 89bb ldrh r3, [r7, #12] 3a2e: 4313 orrs r3, r2 3a30: 81bb strh r3, [r7, #12] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 3a32: 687b ldr r3, [r7, #4] 3a34: 89ba ldrh r2, [r7, #12] 3a36: 809a strh r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 3a38: 687b ldr r3, [r7, #4] 3a3a: 897a ldrh r2, [r7, #10] 3a3c: 839a strh r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; 3a3e: 683b ldr r3, [r7, #0] 3a40: 88da ldrh r2, [r3, #6] 3a42: 687b ldr r3, [r7, #4] 3a44: 879a strh r2, [r3, #60] ; 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 3a46: 687b ldr r3, [r7, #4] 3a48: 89fa ldrh r2, [r7, #14] 3a4a: 841a strh r2, [r3, #32] } 3a4c: bf00 nop 3a4e: 3714 adds r7, #20 3a50: 46bd mov sp, r7 3a52: bc80 pop {r7} 3a54: 4770 bx lr 3a56: bf00 nop 3a58: 40012c00 .word 0x40012c00 3a5c: 40013400 .word 0x40013400 00003a60 : * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { 3a60: b480 push {r7} 3a62: b085 sub sp, #20 3a64: af00 add r7, sp, #0 3a66: 6078 str r0, [r7, #4] 3a68: 6039 str r1, [r7, #0] uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 3a6a: 2300 movs r3, #0 3a6c: 81bb strh r3, [r7, #12] 3a6e: 2300 movs r3, #0 3a70: 817b strh r3, [r7, #10] 3a72: 2300 movs r3, #0 3a74: 81fb strh r3, [r7, #14] assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 2: Reset the CC4E Bit */ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); 3a76: 687b ldr r3, [r7, #4] 3a78: 8c1b ldrh r3, [r3, #32] 3a7a: b29b uxth r3, r3 3a7c: f423 5380 bic.w r3, r3, #4096 ; 0x1000 3a80: b29a uxth r2, r3 3a82: 687b ldr r3, [r7, #4] 3a84: 841a strh r2, [r3, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 3a86: 687b ldr r3, [r7, #4] 3a88: 8c1b ldrh r3, [r3, #32] 3a8a: 817b strh r3, [r7, #10] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 3a8c: 687b ldr r3, [r7, #4] 3a8e: 889b ldrh r3, [r3, #4] 3a90: 81fb strh r3, [r7, #14] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 3a92: 687b ldr r3, [r7, #4] 3a94: 8b9b ldrh r3, [r3, #28] 3a96: 81bb strh r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); 3a98: 89bb ldrh r3, [r7, #12] 3a9a: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 3a9e: 81bb strh r3, [r7, #12] tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); 3aa0: 89bb ldrh r3, [r7, #12] 3aa2: f423 7340 bic.w r3, r3, #768 ; 0x300 3aa6: 81bb strh r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); 3aa8: 683b ldr r3, [r7, #0] 3aaa: 881b ldrh r3, [r3, #0] 3aac: 021b lsls r3, r3, #8 3aae: b29a uxth r2, r3 3ab0: 89bb ldrh r3, [r7, #12] 3ab2: 4313 orrs r3, r2 3ab4: 81bb strh r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); 3ab6: 897b ldrh r3, [r7, #10] 3ab8: f423 5300 bic.w r3, r3, #8192 ; 0x2000 3abc: 817b strh r3, [r7, #10] /* Set the Output Compare Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); 3abe: 683b ldr r3, [r7, #0] 3ac0: 891b ldrh r3, [r3, #8] 3ac2: 031b lsls r3, r3, #12 3ac4: b29a uxth r2, r3 3ac6: 897b ldrh r3, [r7, #10] 3ac8: 4313 orrs r3, r2 3aca: 817b strh r3, [r7, #10] /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); 3acc: 683b ldr r3, [r7, #0] 3ace: 885b ldrh r3, [r3, #2] 3ad0: 031b lsls r3, r3, #12 3ad2: b29a uxth r2, r3 3ad4: 897b ldrh r3, [r7, #10] 3ad6: 4313 orrs r3, r2 3ad8: 817b strh r3, [r7, #10] if((TIMx == TIM1) || (TIMx == TIM8)) 3ada: 687b ldr r3, [r7, #4] 3adc: 4a12 ldr r2, [pc, #72] ; (3b28 ) 3ade: 4293 cmp r3, r2 3ae0: d003 beq.n 3aea 3ae2: 687b ldr r3, [r7, #4] 3ae4: 4a11 ldr r2, [pc, #68] ; (3b2c ) 3ae6: 4293 cmp r3, r2 3ae8: d10a bne.n 3b00 { assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); 3aea: 89fb ldrh r3, [r7, #14] 3aec: f423 4380 bic.w r3, r3, #16384 ; 0x4000 3af0: 81fb strh r3, [r7, #14] /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); 3af2: 683b ldr r3, [r7, #0] 3af4: 899b ldrh r3, [r3, #12] 3af6: 019b lsls r3, r3, #6 3af8: b29a uxth r2, r3 3afa: 89fb ldrh r3, [r7, #14] 3afc: 4313 orrs r3, r2 3afe: 81fb strh r3, [r7, #14] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 3b00: 687b ldr r3, [r7, #4] 3b02: 89fa ldrh r2, [r7, #14] 3b04: 809a strh r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 3b06: 687b ldr r3, [r7, #4] 3b08: 89ba ldrh r2, [r7, #12] 3b0a: 839a strh r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; 3b0c: 683b ldr r3, [r7, #0] 3b0e: 88da ldrh r2, [r3, #6] 3b10: 687b ldr r3, [r7, #4] 3b12: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 3b16: 687b ldr r3, [r7, #4] 3b18: 897a ldrh r2, [r7, #10] 3b1a: 841a strh r2, [r3, #32] } 3b1c: bf00 nop 3b1e: 3714 adds r7, #20 3b20: 46bd mov sp, r7 3b22: bc80 pop {r7} 3b24: 4770 bx lr 3b26: bf00 nop 3b28: 40012c00 .word 0x40012c00 3b2c: 40013400 .word 0x40013400 00003b30 : * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) { 3b30: b580 push {r7, lr} 3b32: b082 sub sp, #8 3b34: af00 add r7, sp, #0 3b36: 6078 str r0, [r7, #4] 3b38: 6039 str r1, [r7, #0] } else { assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); } if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) 3b3a: 683b ldr r3, [r7, #0] 3b3c: 881b ldrh r3, [r3, #0] 3b3e: 2b00 cmp r3, #0 3b40: d10f bne.n 3b62 { assert_param(IS_TIM_LIST8_PERIPH(TIMx)); /* TI1 Configuration */ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 3b42: 683b ldr r3, [r7, #0] 3b44: 8859 ldrh r1, [r3, #2] 3b46: 683b ldr r3, [r7, #0] 3b48: 889a ldrh r2, [r3, #4] 3b4a: 683b ldr r3, [r7, #0] 3b4c: 891b ldrh r3, [r3, #8] 3b4e: 6878 ldr r0, [r7, #4] 3b50: f001 f947 bl 4de2 TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 3b54: 683b ldr r3, [r7, #0] 3b56: 88db ldrh r3, [r3, #6] 3b58: 4619 mov r1, r3 3b5a: 6878 ldr r0, [r7, #4] 3b5c: f001 f809 bl 4b72 TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } } 3b60: e036 b.n 3bd0 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) 3b62: 683b ldr r3, [r7, #0] 3b64: 881b ldrh r3, [r3, #0] 3b66: 2b04 cmp r3, #4 3b68: d10f bne.n 3b8a TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 3b6a: 683b ldr r3, [r7, #0] 3b6c: 8859 ldrh r1, [r3, #2] 3b6e: 683b ldr r3, [r7, #0] 3b70: 889a ldrh r2, [r3, #4] 3b72: 683b ldr r3, [r7, #0] 3b74: 891b ldrh r3, [r3, #8] 3b76: 6878 ldr r0, [r7, #4] 3b78: f001 f9a4 bl 4ec4 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 3b7c: 683b ldr r3, [r7, #0] 3b7e: 88db ldrh r3, [r3, #6] 3b80: 4619 mov r1, r3 3b82: 6878 ldr r0, [r7, #4] 3b84: f001 f810 bl 4ba8 } 3b88: e022 b.n 3bd0 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) 3b8a: 683b ldr r3, [r7, #0] 3b8c: 881b ldrh r3, [r3, #0] 3b8e: 2b08 cmp r3, #8 3b90: d10f bne.n 3bb2 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 3b92: 683b ldr r3, [r7, #0] 3b94: 8859 ldrh r1, [r3, #2] 3b96: 683b ldr r3, [r7, #0] 3b98: 889a ldrh r2, [r3, #4] 3b9a: 683b ldr r3, [r7, #0] 3b9c: 891b ldrh r3, [r3, #8] 3b9e: 6878 ldr r0, [r7, #4] 3ba0: f001 fa0a bl 4fb8 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 3ba4: 683b ldr r3, [r7, #0] 3ba6: 88db ldrh r3, [r3, #6] 3ba8: 4619 mov r1, r3 3baa: 6878 ldr r0, [r7, #4] 3bac: f001 f819 bl 4be2 } 3bb0: e00e b.n 3bd0 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 3bb2: 683b ldr r3, [r7, #0] 3bb4: 8859 ldrh r1, [r3, #2] 3bb6: 683b ldr r3, [r7, #0] 3bb8: 889a ldrh r2, [r3, #4] 3bba: 683b ldr r3, [r7, #0] 3bbc: 891b ldrh r3, [r3, #8] 3bbe: 6878 ldr r0, [r7, #4] 3bc0: f001 fa70 bl 50a4 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 3bc4: 683b ldr r3, [r7, #0] 3bc6: 88db ldrh r3, [r3, #6] 3bc8: 4619 mov r1, r3 3bca: 6878 ldr r0, [r7, #4] 3bcc: f001 f824 bl 4c18 } 3bd0: bf00 nop 3bd2: 3708 adds r7, #8 3bd4: 46bd mov sp, r7 3bd6: bd80 pop {r7, pc} 00003bd8 : * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) { 3bd8: b580 push {r7, lr} 3bda: b084 sub sp, #16 3bdc: af00 add r7, sp, #0 3bde: 6078 str r0, [r7, #4] 3be0: 6039 str r1, [r7, #0] uint16_t icoppositepolarity = TIM_ICPolarity_Rising; 3be2: 2300 movs r3, #0 3be4: 81fb strh r3, [r7, #14] uint16_t icoppositeselection = TIM_ICSelection_DirectTI; 3be6: 2301 movs r3, #1 3be8: 81bb strh r3, [r7, #12] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); /* Select the Opposite Input Polarity */ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) 3bea: 683b ldr r3, [r7, #0] 3bec: 885b ldrh r3, [r3, #2] 3bee: 2b00 cmp r3, #0 3bf0: d102 bne.n 3bf8 { icoppositepolarity = TIM_ICPolarity_Falling; 3bf2: 2302 movs r3, #2 3bf4: 81fb strh r3, [r7, #14] 3bf6: e001 b.n 3bfc } else { icoppositepolarity = TIM_ICPolarity_Rising; 3bf8: 2300 movs r3, #0 3bfa: 81fb strh r3, [r7, #14] } /* Select the Opposite Input */ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) 3bfc: 683b ldr r3, [r7, #0] 3bfe: 889b ldrh r3, [r3, #4] 3c00: 2b01 cmp r3, #1 3c02: d102 bne.n 3c0a { icoppositeselection = TIM_ICSelection_IndirectTI; 3c04: 2302 movs r3, #2 3c06: 81bb strh r3, [r7, #12] 3c08: e001 b.n 3c0e } else { icoppositeselection = TIM_ICSelection_DirectTI; 3c0a: 2301 movs r3, #1 3c0c: 81bb strh r3, [r7, #12] } if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) 3c0e: 683b ldr r3, [r7, #0] 3c10: 881b ldrh r3, [r3, #0] 3c12: 2b00 cmp r3, #0 3c14: d11c bne.n 3c50 { /* TI1 Configuration */ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, 3c16: 683b ldr r3, [r7, #0] 3c18: 8859 ldrh r1, [r3, #2] 3c1a: 683b ldr r3, [r7, #0] 3c1c: 889a ldrh r2, [r3, #4] 3c1e: 683b ldr r3, [r7, #0] 3c20: 891b ldrh r3, [r3, #8] 3c22: 6878 ldr r0, [r7, #4] 3c24: f001 f8dd bl 4de2 TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 3c28: 683b ldr r3, [r7, #0] 3c2a: 88db ldrh r3, [r3, #6] 3c2c: 4619 mov r1, r3 3c2e: 6878 ldr r0, [r7, #4] 3c30: f000 ff9f bl 4b72 /* TI2 Configuration */ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); 3c34: 683b ldr r3, [r7, #0] 3c36: 891b ldrh r3, [r3, #8] 3c38: 89ba ldrh r2, [r7, #12] 3c3a: 89f9 ldrh r1, [r7, #14] 3c3c: 6878 ldr r0, [r7, #4] 3c3e: f001 f941 bl 4ec4 /* Set the Input Capture Prescaler value */ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 3c42: 683b ldr r3, [r7, #0] 3c44: 88db ldrh r3, [r3, #6] 3c46: 4619 mov r1, r3 3c48: 6878 ldr r0, [r7, #4] 3c4a: f000 ffad bl 4ba8 /* TI1 Configuration */ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } } 3c4e: e01b b.n 3c88 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, 3c50: 683b ldr r3, [r7, #0] 3c52: 8859 ldrh r1, [r3, #2] 3c54: 683b ldr r3, [r7, #0] 3c56: 889a ldrh r2, [r3, #4] 3c58: 683b ldr r3, [r7, #0] 3c5a: 891b ldrh r3, [r3, #8] 3c5c: 6878 ldr r0, [r7, #4] 3c5e: f001 f931 bl 4ec4 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 3c62: 683b ldr r3, [r7, #0] 3c64: 88db ldrh r3, [r3, #6] 3c66: 4619 mov r1, r3 3c68: 6878 ldr r0, [r7, #4] 3c6a: f000 ff9d bl 4ba8 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); 3c6e: 683b ldr r3, [r7, #0] 3c70: 891b ldrh r3, [r3, #8] 3c72: 89ba ldrh r2, [r7, #12] 3c74: 89f9 ldrh r1, [r7, #14] 3c76: 6878 ldr r0, [r7, #4] 3c78: f001 f8b3 bl 4de2 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 3c7c: 683b ldr r3, [r7, #0] 3c7e: 88db ldrh r3, [r3, #6] 3c80: 4619 mov r1, r3 3c82: 6878 ldr r0, [r7, #4] 3c84: f000 ff75 bl 4b72 } 3c88: bf00 nop 3c8a: 3710 adds r7, #16 3c8c: 46bd mov sp, r7 3c8e: bd80 pop {r7, pc} 00003c90 : * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval None */ void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) { 3c90: b480 push {r7} 3c92: b083 sub sp, #12 3c94: af00 add r7, sp, #0 3c96: 6078 str r0, [r7, #4] 3c98: 6039 str r1, [r7, #0] assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | 3c9a: 683b ldr r3, [r7, #0] 3c9c: 881a ldrh r2, [r3, #0] 3c9e: 683b ldr r3, [r7, #0] 3ca0: 885b ldrh r3, [r3, #2] 3ca2: 4313 orrs r3, r2 3ca4: b29a uxth r2, r3 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | 3ca6: 683b ldr r3, [r7, #0] 3ca8: 889b ldrh r3, [r3, #4] TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | 3caa: 4313 orrs r3, r2 3cac: b29a uxth r2, r3 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | 3cae: 683b ldr r3, [r7, #0] 3cb0: 88db ldrh r3, [r3, #6] TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | 3cb2: 4313 orrs r3, r2 3cb4: b29a uxth r2, r3 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | 3cb6: 683b ldr r3, [r7, #0] 3cb8: 891b ldrh r3, [r3, #8] TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | 3cba: 4313 orrs r3, r2 3cbc: b29a uxth r2, r3 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | 3cbe: 683b ldr r3, [r7, #0] 3cc0: 895b ldrh r3, [r3, #10] TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | 3cc2: 4313 orrs r3, r2 3cc4: b29a uxth r2, r3 TIM_BDTRInitStruct->TIM_AutomaticOutput; 3cc6: 683b ldr r3, [r7, #0] 3cc8: 899b ldrh r3, [r3, #12] TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | 3cca: 4313 orrs r3, r2 3ccc: b29a uxth r2, r3 3cce: 687b ldr r3, [r7, #4] 3cd0: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 } 3cd4: bf00 nop 3cd6: 370c adds r7, #12 3cd8: 46bd mov sp, r7 3cda: bc80 pop {r7} 3cdc: 4770 bx lr 00003cde : * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef * structure which will be initialized. * @retval None */ void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) { 3cde: b480 push {r7} 3ce0: b083 sub sp, #12 3ce2: af00 add r7, sp, #0 3ce4: 6078 str r0, [r7, #4] /* Set the default configuration */ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; 3ce6: 687b ldr r3, [r7, #4] 3ce8: f64f 72ff movw r2, #65535 ; 0xffff 3cec: 809a strh r2, [r3, #4] TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; 3cee: 687b ldr r3, [r7, #4] 3cf0: 2200 movs r2, #0 3cf2: 801a strh r2, [r3, #0] TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; 3cf4: 687b ldr r3, [r7, #4] 3cf6: 2200 movs r2, #0 3cf8: 80da strh r2, [r3, #6] TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; 3cfa: 687b ldr r3, [r7, #4] 3cfc: 2200 movs r2, #0 3cfe: 805a strh r2, [r3, #2] TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; 3d00: 687b ldr r3, [r7, #4] 3d02: 2200 movs r2, #0 3d04: 721a strb r2, [r3, #8] } 3d06: bf00 nop 3d08: 370c adds r7, #12 3d0a: 46bd mov sp, r7 3d0c: bc80 pop {r7} 3d0e: 4770 bx lr 00003d10 : * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will * be initialized. * @retval None */ void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) { 3d10: b480 push {r7} 3d12: b083 sub sp, #12 3d14: af00 add r7, sp, #0 3d16: 6078 str r0, [r7, #4] /* Set the default configuration */ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; 3d18: 687b ldr r3, [r7, #4] 3d1a: 2200 movs r2, #0 3d1c: 801a strh r2, [r3, #0] TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; 3d1e: 687b ldr r3, [r7, #4] 3d20: 2200 movs r2, #0 3d22: 805a strh r2, [r3, #2] TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; 3d24: 687b ldr r3, [r7, #4] 3d26: 2200 movs r2, #0 3d28: 809a strh r2, [r3, #4] TIM_OCInitStruct->TIM_Pulse = 0x0000; 3d2a: 687b ldr r3, [r7, #4] 3d2c: 2200 movs r2, #0 3d2e: 80da strh r2, [r3, #6] TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; 3d30: 687b ldr r3, [r7, #4] 3d32: 2200 movs r2, #0 3d34: 811a strh r2, [r3, #8] TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; 3d36: 687b ldr r3, [r7, #4] 3d38: 2200 movs r2, #0 3d3a: 815a strh r2, [r3, #10] TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; 3d3c: 687b ldr r3, [r7, #4] 3d3e: 2200 movs r2, #0 3d40: 819a strh r2, [r3, #12] TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; 3d42: 687b ldr r3, [r7, #4] 3d44: 2200 movs r2, #0 3d46: 81da strh r2, [r3, #14] } 3d48: bf00 nop 3d4a: 370c adds r7, #12 3d4c: 46bd mov sp, r7 3d4e: bc80 pop {r7} 3d50: 4770 bx lr 00003d52 : * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will * be initialized. * @retval None */ void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) { 3d52: b480 push {r7} 3d54: b083 sub sp, #12 3d56: af00 add r7, sp, #0 3d58: 6078 str r0, [r7, #4] /* Set the default configuration */ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; 3d5a: 687b ldr r3, [r7, #4] 3d5c: 2200 movs r2, #0 3d5e: 801a strh r2, [r3, #0] TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; 3d60: 687b ldr r3, [r7, #4] 3d62: 2200 movs r2, #0 3d64: 805a strh r2, [r3, #2] TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; 3d66: 687b ldr r3, [r7, #4] 3d68: 2201 movs r2, #1 3d6a: 809a strh r2, [r3, #4] TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; 3d6c: 687b ldr r3, [r7, #4] 3d6e: 2200 movs r2, #0 3d70: 80da strh r2, [r3, #6] TIM_ICInitStruct->TIM_ICFilter = 0x00; 3d72: 687b ldr r3, [r7, #4] 3d74: 2200 movs r2, #0 3d76: 811a strh r2, [r3, #8] } 3d78: bf00 nop 3d7a: 370c adds r7, #12 3d7c: 46bd mov sp, r7 3d7e: bc80 pop {r7} 3d80: 4770 bx lr 00003d82 : * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which * will be initialized. * @retval None */ void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) { 3d82: b480 push {r7} 3d84: b083 sub sp, #12 3d86: af00 add r7, sp, #0 3d88: 6078 str r0, [r7, #4] /* Set the default configuration */ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; 3d8a: 687b ldr r3, [r7, #4] 3d8c: 2200 movs r2, #0 3d8e: 801a strh r2, [r3, #0] TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; 3d90: 687b ldr r3, [r7, #4] 3d92: 2200 movs r2, #0 3d94: 805a strh r2, [r3, #2] TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; 3d96: 687b ldr r3, [r7, #4] 3d98: 2200 movs r2, #0 3d9a: 809a strh r2, [r3, #4] TIM_BDTRInitStruct->TIM_DeadTime = 0x00; 3d9c: 687b ldr r3, [r7, #4] 3d9e: 2200 movs r2, #0 3da0: 80da strh r2, [r3, #6] TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; 3da2: 687b ldr r3, [r7, #4] 3da4: 2200 movs r2, #0 3da6: 811a strh r2, [r3, #8] TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; 3da8: 687b ldr r3, [r7, #4] 3daa: 2200 movs r2, #0 3dac: 815a strh r2, [r3, #10] TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; 3dae: 687b ldr r3, [r7, #4] 3db0: 2200 movs r2, #0 3db2: 819a strh r2, [r3, #12] } 3db4: bf00 nop 3db6: 370c adds r7, #12 3db8: 46bd mov sp, r7 3dba: bc80 pop {r7} 3dbc: 4770 bx lr 00003dbe : * @param NewState: new state of the TIMx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) { 3dbe: b480 push {r7} 3dc0: b083 sub sp, #12 3dc2: af00 add r7, sp, #0 3dc4: 6078 str r0, [r7, #4] 3dc6: 460b mov r3, r1 3dc8: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 3dca: 78fb ldrb r3, [r7, #3] 3dcc: 2b00 cmp r3, #0 3dce: d008 beq.n 3de2 { /* Enable the TIM Counter */ TIMx->CR1 |= TIM_CR1_CEN; 3dd0: 687b ldr r3, [r7, #4] 3dd2: 881b ldrh r3, [r3, #0] 3dd4: b29b uxth r3, r3 3dd6: f043 0301 orr.w r3, r3, #1 3dda: b29a uxth r2, r3 3ddc: 687b ldr r3, [r7, #4] 3dde: 801a strh r2, [r3, #0] else { /* Disable the TIM Counter */ TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); } } 3de0: e007 b.n 3df2 TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); 3de2: 687b ldr r3, [r7, #4] 3de4: 881b ldrh r3, [r3, #0] 3de6: b29b uxth r3, r3 3de8: f023 0301 bic.w r3, r3, #1 3dec: b29a uxth r2, r3 3dee: 687b ldr r3, [r7, #4] 3df0: 801a strh r2, [r3, #0] } 3df2: bf00 nop 3df4: 370c adds r7, #12 3df6: 46bd mov sp, r7 3df8: bc80 pop {r7} 3dfa: 4770 bx lr 00003dfc : * @param NewState: new state of the TIM peripheral Main Outputs. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) { 3dfc: b480 push {r7} 3dfe: b083 sub sp, #12 3e00: af00 add r7, sp, #0 3e02: 6078 str r0, [r7, #4] 3e04: 460b mov r3, r1 3e06: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 3e08: 78fb ldrb r3, [r7, #3] 3e0a: 2b00 cmp r3, #0 3e0c: d00c beq.n 3e28 { /* Enable the TIM Main Output */ TIMx->BDTR |= TIM_BDTR_MOE; 3e0e: 687b ldr r3, [r7, #4] 3e10: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 3e14: b29b uxth r3, r3 3e16: ea6f 4343 mvn.w r3, r3, lsl #17 3e1a: ea6f 4353 mvn.w r3, r3, lsr #17 3e1e: b29a uxth r2, r3 3e20: 687b ldr r3, [r7, #4] 3e22: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 else { /* Disable the TIM Main Output */ TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); } } 3e26: e009 b.n 3e3c TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); 3e28: 687b ldr r3, [r7, #4] 3e2a: f8b3 3044 ldrh.w r3, [r3, #68] ; 0x44 3e2e: b29b uxth r3, r3 3e30: f3c3 030e ubfx r3, r3, #0, #15 3e34: b29a uxth r2, r3 3e36: 687b ldr r3, [r7, #4] 3e38: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 } 3e3c: bf00 nop 3e3e: 370c adds r7, #12 3e40: 46bd mov sp, r7 3e42: bc80 pop {r7} 3e44: 4770 bx lr 00003e46 : * @param NewState: new state of the TIM interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) { 3e46: b480 push {r7} 3e48: b083 sub sp, #12 3e4a: af00 add r7, sp, #0 3e4c: 6078 str r0, [r7, #4] 3e4e: 460b mov r3, r1 3e50: 807b strh r3, [r7, #2] 3e52: 4613 mov r3, r2 3e54: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_IT(TIM_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 3e56: 787b ldrb r3, [r7, #1] 3e58: 2b00 cmp r3, #0 3e5a: d008 beq.n 3e6e { /* Enable the Interrupt sources */ TIMx->DIER |= TIM_IT; 3e5c: 687b ldr r3, [r7, #4] 3e5e: 899b ldrh r3, [r3, #12] 3e60: b29a uxth r2, r3 3e62: 887b ldrh r3, [r7, #2] 3e64: 4313 orrs r3, r2 3e66: b29a uxth r2, r3 3e68: 687b ldr r3, [r7, #4] 3e6a: 819a strh r2, [r3, #12] else { /* Disable the Interrupt sources */ TIMx->DIER &= (uint16_t)~TIM_IT; } } 3e6c: e009 b.n 3e82 TIMx->DIER &= (uint16_t)~TIM_IT; 3e6e: 687b ldr r3, [r7, #4] 3e70: 899b ldrh r3, [r3, #12] 3e72: b29a uxth r2, r3 3e74: 887b ldrh r3, [r7, #2] 3e76: 43db mvns r3, r3 3e78: b29b uxth r3, r3 3e7a: 4013 ands r3, r2 3e7c: b29a uxth r2, r3 3e7e: 687b ldr r3, [r7, #4] 3e80: 819a strh r2, [r3, #12] } 3e82: bf00 nop 3e84: 370c adds r7, #12 3e86: 46bd mov sp, r7 3e88: bc80 pop {r7} 3e8a: 4770 bx lr 00003e8c : * - TIM6 and TIM7 can only generate an update event. * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. * @retval None */ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) { 3e8c: b480 push {r7} 3e8e: b083 sub sp, #12 3e90: af00 add r7, sp, #0 3e92: 6078 str r0, [r7, #4] 3e94: 460b mov r3, r1 3e96: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); /* Set the event sources */ TIMx->EGR = TIM_EventSource; 3e98: 687b ldr r3, [r7, #4] 3e9a: 887a ldrh r2, [r7, #2] 3e9c: 829a strh r2, [r3, #20] } 3e9e: bf00 nop 3ea0: 370c adds r7, #12 3ea2: 46bd mov sp, r7 3ea4: bc80 pop {r7} 3ea6: 4770 bx lr 00003ea8 : * This parameter can be one value between: * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval None */ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) { 3ea8: b480 push {r7} 3eaa: b083 sub sp, #12 3eac: af00 add r7, sp, #0 3eae: 6078 str r0, [r7, #4] 3eb0: 460b mov r3, r1 3eb2: 807b strh r3, [r7, #2] 3eb4: 4613 mov r3, r2 3eb6: 803b strh r3, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); /* Set the DMA Base and the DMA Burst Length */ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; 3eb8: 887a ldrh r2, [r7, #2] 3eba: 883b ldrh r3, [r7, #0] 3ebc: 4313 orrs r3, r2 3ebe: b29a uxth r2, r3 3ec0: 687b ldr r3, [r7, #4] 3ec2: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 } 3ec6: bf00 nop 3ec8: 370c adds r7, #12 3eca: 46bd mov sp, r7 3ecc: bc80 pop {r7} 3ece: 4770 bx lr 00003ed0 : * @param NewState: new state of the DMA Request sources. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) { 3ed0: b480 push {r7} 3ed2: b083 sub sp, #12 3ed4: af00 add r7, sp, #0 3ed6: 6078 str r0, [r7, #4] 3ed8: 460b mov r3, r1 3eda: 807b strh r3, [r7, #2] 3edc: 4613 mov r3, r2 3ede: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_TIM_LIST9_PERIPH(TIMx)); assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 3ee0: 787b ldrb r3, [r7, #1] 3ee2: 2b00 cmp r3, #0 3ee4: d008 beq.n 3ef8 { /* Enable the DMA sources */ TIMx->DIER |= TIM_DMASource; 3ee6: 687b ldr r3, [r7, #4] 3ee8: 899b ldrh r3, [r3, #12] 3eea: b29a uxth r2, r3 3eec: 887b ldrh r3, [r7, #2] 3eee: 4313 orrs r3, r2 3ef0: b29a uxth r2, r3 3ef2: 687b ldr r3, [r7, #4] 3ef4: 819a strh r2, [r3, #12] else { /* Disable the DMA sources */ TIMx->DIER &= (uint16_t)~TIM_DMASource; } } 3ef6: e009 b.n 3f0c TIMx->DIER &= (uint16_t)~TIM_DMASource; 3ef8: 687b ldr r3, [r7, #4] 3efa: 899b ldrh r3, [r3, #12] 3efc: b29a uxth r2, r3 3efe: 887b ldrh r3, [r7, #2] 3f00: 43db mvns r3, r3 3f02: b29b uxth r3, r3 3f04: 4013 ands r3, r2 3f06: b29a uxth r2, r3 3f08: 687b ldr r3, [r7, #4] 3f0a: 819a strh r2, [r3, #12] } 3f0c: bf00 nop 3f0e: 370c adds r7, #12 3f10: 46bd mov sp, r7 3f12: bc80 pop {r7} 3f14: 4770 bx lr 00003f16 : * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 * to select the TIM peripheral. * @retval None */ void TIM_InternalClockConfig(TIM_TypeDef* TIMx) { 3f16: b480 push {r7} 3f18: b083 sub sp, #12 3f1a: af00 add r7, sp, #0 3f1c: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); /* Disable slave mode to clock the prescaler directly with the internal clock */ TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); 3f1e: 687b ldr r3, [r7, #4] 3f20: 891b ldrh r3, [r3, #8] 3f22: b29b uxth r3, r3 3f24: f023 0307 bic.w r3, r3, #7 3f28: b29a uxth r2, r3 3f2a: 687b ldr r3, [r7, #4] 3f2c: 811a strh r2, [r3, #8] } 3f2e: bf00 nop 3f30: 370c adds r7, #12 3f32: 46bd mov sp, r7 3f34: bc80 pop {r7} 3f36: 4770 bx lr 00003f38 : * @param TIM_TS_ITR2: Internal Trigger 2 * @param TIM_TS_ITR3: Internal Trigger 3 * @retval None */ void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) { 3f38: b580 push {r7, lr} 3f3a: b082 sub sp, #8 3f3c: af00 add r7, sp, #0 3f3e: 6078 str r0, [r7, #4] 3f40: 460b mov r3, r1 3f42: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); /* Select the Internal Trigger */ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); 3f44: 887b ldrh r3, [r7, #2] 3f46: 4619 mov r1, r3 3f48: 6878 ldr r0, [r7, #4] 3f4a: f000 f8df bl 410c /* Select the External clock mode1 */ TIMx->SMCR |= TIM_SlaveMode_External1; 3f4e: 687b ldr r3, [r7, #4] 3f50: 891b ldrh r3, [r3, #8] 3f52: b29b uxth r3, r3 3f54: f043 0307 orr.w r3, r3, #7 3f58: b29a uxth r2, r3 3f5a: 687b ldr r3, [r7, #4] 3f5c: 811a strh r2, [r3, #8] } 3f5e: bf00 nop 3f60: 3708 adds r7, #8 3f62: 46bd mov sp, r7 3f64: bd80 pop {r7, pc} 00003f66 : * This parameter must be a value between 0x0 and 0xF. * @retval None */ void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter) { 3f66: b580 push {r7, lr} 3f68: b084 sub sp, #16 3f6a: af00 add r7, sp, #0 3f6c: 60f8 str r0, [r7, #12] 3f6e: 4608 mov r0, r1 3f70: 4611 mov r1, r2 3f72: 461a mov r2, r3 3f74: 4603 mov r3, r0 3f76: 817b strh r3, [r7, #10] 3f78: 460b mov r3, r1 3f7a: 813b strh r3, [r7, #8] 3f7c: 4613 mov r3, r2 3f7e: 80fb strh r3, [r7, #6] assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); assert_param(IS_TIM_IC_FILTER(ICFilter)); /* Configure the Timer Input Clock Source */ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) 3f80: 897b ldrh r3, [r7, #10] 3f82: 2b60 cmp r3, #96 ; 0x60 3f84: d106 bne.n 3f94 { TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); 3f86: 88fb ldrh r3, [r7, #6] 3f88: 8939 ldrh r1, [r7, #8] 3f8a: 2201 movs r2, #1 3f8c: 68f8 ldr r0, [r7, #12] 3f8e: f000 ff99 bl 4ec4 3f92: e005 b.n 3fa0 } else { TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); 3f94: 88fb ldrh r3, [r7, #6] 3f96: 8939 ldrh r1, [r7, #8] 3f98: 2201 movs r2, #1 3f9a: 68f8 ldr r0, [r7, #12] 3f9c: f000 ff21 bl 4de2 } /* Select the Trigger source */ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); 3fa0: 897b ldrh r3, [r7, #10] 3fa2: 4619 mov r1, r3 3fa4: 68f8 ldr r0, [r7, #12] 3fa6: f000 f8b1 bl 410c /* Select the External clock mode1 */ TIMx->SMCR |= TIM_SlaveMode_External1; 3faa: 68fb ldr r3, [r7, #12] 3fac: 891b ldrh r3, [r3, #8] 3fae: b29b uxth r3, r3 3fb0: f043 0307 orr.w r3, r3, #7 3fb4: b29a uxth r2, r3 3fb6: 68fb ldr r3, [r7, #12] 3fb8: 811a strh r2, [r3, #8] } 3fba: bf00 nop 3fbc: 3710 adds r7, #16 3fbe: 46bd mov sp, r7 3fc0: bd80 pop {r7, pc} 00003fc2 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) { 3fc2: b580 push {r7, lr} 3fc4: b086 sub sp, #24 3fc6: af00 add r7, sp, #0 3fc8: 60f8 str r0, [r7, #12] 3fca: 4608 mov r0, r1 3fcc: 4611 mov r1, r2 3fce: 461a mov r2, r3 3fd0: 4603 mov r3, r0 3fd2: 817b strh r3, [r7, #10] 3fd4: 460b mov r3, r1 3fd6: 813b strh r3, [r7, #8] 3fd8: 4613 mov r3, r2 3fda: 80fb strh r3, [r7, #6] uint16_t tmpsmcr = 0; 3fdc: 2300 movs r3, #0 3fde: 82fb strh r3, [r7, #22] assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); /* Configure the ETR Clock source */ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); 3fe0: 88fb ldrh r3, [r7, #6] 3fe2: 893a ldrh r2, [r7, #8] 3fe4: 8979 ldrh r1, [r7, #10] 3fe6: 68f8 ldr r0, [r7, #12] 3fe8: f000 f839 bl 405e /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 3fec: 68fb ldr r3, [r7, #12] 3fee: 891b ldrh r3, [r3, #8] 3ff0: 82fb strh r3, [r7, #22] /* Reset the SMS Bits */ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); 3ff2: 8afb ldrh r3, [r7, #22] 3ff4: f023 0307 bic.w r3, r3, #7 3ff8: 82fb strh r3, [r7, #22] /* Select the External clock mode1 */ tmpsmcr |= TIM_SlaveMode_External1; 3ffa: 8afb ldrh r3, [r7, #22] 3ffc: f043 0307 orr.w r3, r3, #7 4000: 82fb strh r3, [r7, #22] /* Select the Trigger selection : ETRF */ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); 4002: 8afb ldrh r3, [r7, #22] 4004: f023 0370 bic.w r3, r3, #112 ; 0x70 4008: 82fb strh r3, [r7, #22] tmpsmcr |= TIM_TS_ETRF; 400a: 8afb ldrh r3, [r7, #22] 400c: f043 0370 orr.w r3, r3, #112 ; 0x70 4010: 82fb strh r3, [r7, #22] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 4012: 68fb ldr r3, [r7, #12] 4014: 8afa ldrh r2, [r7, #22] 4016: 811a strh r2, [r3, #8] } 4018: bf00 nop 401a: 3718 adds r7, #24 401c: 46bd mov sp, r7 401e: bd80 pop {r7, pc} 00004020 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) { 4020: b580 push {r7, lr} 4022: b084 sub sp, #16 4024: af00 add r7, sp, #0 4026: 60f8 str r0, [r7, #12] 4028: 4608 mov r0, r1 402a: 4611 mov r1, r2 402c: 461a mov r2, r3 402e: 4603 mov r3, r0 4030: 817b strh r3, [r7, #10] 4032: 460b mov r3, r1 4034: 813b strh r3, [r7, #8] 4036: 4613 mov r3, r2 4038: 80fb strh r3, [r7, #6] assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); /* Configure the ETR Clock source */ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); 403a: 88fb ldrh r3, [r7, #6] 403c: 893a ldrh r2, [r7, #8] 403e: 8979 ldrh r1, [r7, #10] 4040: 68f8 ldr r0, [r7, #12] 4042: f000 f80c bl 405e /* Enable the External clock mode2 */ TIMx->SMCR |= TIM_SMCR_ECE; 4046: 68fb ldr r3, [r7, #12] 4048: 891b ldrh r3, [r3, #8] 404a: b29b uxth r3, r3 404c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 4050: b29a uxth r2, r3 4052: 68fb ldr r3, [r7, #12] 4054: 811a strh r2, [r3, #8] } 4056: bf00 nop 4058: 3710 adds r7, #16 405a: 46bd mov sp, r7 405c: bd80 pop {r7, pc} 0000405e : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) { 405e: b480 push {r7} 4060: b087 sub sp, #28 4062: af00 add r7, sp, #0 4064: 60f8 str r0, [r7, #12] 4066: 4608 mov r0, r1 4068: 4611 mov r1, r2 406a: 461a mov r2, r3 406c: 4603 mov r3, r0 406e: 817b strh r3, [r7, #10] 4070: 460b mov r3, r1 4072: 813b strh r3, [r7, #8] 4074: 4613 mov r3, r2 4076: 80fb strh r3, [r7, #6] uint16_t tmpsmcr = 0; 4078: 2300 movs r3, #0 407a: 82fb strh r3, [r7, #22] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); tmpsmcr = TIMx->SMCR; 407c: 68fb ldr r3, [r7, #12] 407e: 891b ldrh r3, [r3, #8] 4080: 82fb strh r3, [r7, #22] /* Reset the ETR Bits */ tmpsmcr &= SMCR_ETR_Mask; 4082: 8afb ldrh r3, [r7, #22] 4084: b2db uxtb r3, r3 4086: 82fb strh r3, [r7, #22] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); 4088: 88fb ldrh r3, [r7, #6] 408a: 021b lsls r3, r3, #8 408c: b29a uxth r2, r3 408e: 893b ldrh r3, [r7, #8] 4090: 4313 orrs r3, r2 4092: b29a uxth r2, r3 4094: 897b ldrh r3, [r7, #10] 4096: 4313 orrs r3, r2 4098: b29a uxth r2, r3 409a: 8afb ldrh r3, [r7, #22] 409c: 4313 orrs r3, r2 409e: 82fb strh r3, [r7, #22] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 40a0: 68fb ldr r3, [r7, #12] 40a2: 8afa ldrh r2, [r7, #22] 40a4: 811a strh r2, [r3, #8] } 40a6: bf00 nop 40a8: 371c adds r7, #28 40aa: 46bd mov sp, r7 40ac: bc80 pop {r7} 40ae: 4770 bx lr 000040b0 : * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. * @retval None */ void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) { 40b0: b480 push {r7} 40b2: b083 sub sp, #12 40b4: af00 add r7, sp, #0 40b6: 6078 str r0, [r7, #4] 40b8: 460b mov r3, r1 40ba: 807b strh r3, [r7, #2] 40bc: 4613 mov r3, r2 40be: 803b strh r3, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); /* Set the Prescaler value */ TIMx->PSC = Prescaler; 40c0: 687b ldr r3, [r7, #4] 40c2: 887a ldrh r2, [r7, #2] 40c4: 851a strh r2, [r3, #40] ; 0x28 /* Set or reset the UG Bit */ TIMx->EGR = TIM_PSCReloadMode; 40c6: 687b ldr r3, [r7, #4] 40c8: 883a ldrh r2, [r7, #0] 40ca: 829a strh r2, [r3, #20] } 40cc: bf00 nop 40ce: 370c adds r7, #12 40d0: 46bd mov sp, r7 40d2: bc80 pop {r7} 40d4: 4770 bx lr 000040d6 : * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 * @retval None */ void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) { 40d6: b480 push {r7} 40d8: b085 sub sp, #20 40da: af00 add r7, sp, #0 40dc: 6078 str r0, [r7, #4] 40de: 460b mov r3, r1 40e0: 807b strh r3, [r7, #2] uint16_t tmpcr1 = 0; 40e2: 2300 movs r3, #0 40e4: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); tmpcr1 = TIMx->CR1; 40e6: 687b ldr r3, [r7, #4] 40e8: 881b ldrh r3, [r3, #0] 40ea: 81fb strh r3, [r7, #14] /* Reset the CMS and DIR Bits */ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); 40ec: 89fb ldrh r3, [r7, #14] 40ee: f023 0370 bic.w r3, r3, #112 ; 0x70 40f2: 81fb strh r3, [r7, #14] /* Set the Counter Mode */ tmpcr1 |= TIM_CounterMode; 40f4: 89fa ldrh r2, [r7, #14] 40f6: 887b ldrh r3, [r7, #2] 40f8: 4313 orrs r3, r2 40fa: 81fb strh r3, [r7, #14] /* Write to TIMx CR1 register */ TIMx->CR1 = tmpcr1; 40fc: 687b ldr r3, [r7, #4] 40fe: 89fa ldrh r2, [r7, #14] 4100: 801a strh r2, [r3, #0] } 4102: bf00 nop 4104: 3714 adds r7, #20 4106: 46bd mov sp, r7 4108: bc80 pop {r7} 410a: 4770 bx lr 0000410c : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) { 410c: b480 push {r7} 410e: b085 sub sp, #20 4110: af00 add r7, sp, #0 4112: 6078 str r0, [r7, #4] 4114: 460b mov r3, r1 4116: 807b strh r3, [r7, #2] uint16_t tmpsmcr = 0; 4118: 2300 movs r3, #0 411a: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 411c: 687b ldr r3, [r7, #4] 411e: 891b ldrh r3, [r3, #8] 4120: 81fb strh r3, [r7, #14] /* Reset the TS Bits */ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); 4122: 89fb ldrh r3, [r7, #14] 4124: f023 0370 bic.w r3, r3, #112 ; 0x70 4128: 81fb strh r3, [r7, #14] /* Set the Input Trigger source */ tmpsmcr |= TIM_InputTriggerSource; 412a: 89fa ldrh r2, [r7, #14] 412c: 887b ldrh r3, [r7, #2] 412e: 4313 orrs r3, r2 4130: 81fb strh r3, [r7, #14] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 4132: 687b ldr r3, [r7, #4] 4134: 89fa ldrh r2, [r7, #14] 4136: 811a strh r2, [r3, #8] } 4138: bf00 nop 413a: 3714 adds r7, #20 413c: 46bd mov sp, r7 413e: bc80 pop {r7} 4140: 4770 bx lr 00004142 : * @arg TIM_ICPolarity_Rising: IC Rising edge. * @retval None */ void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) { 4142: b480 push {r7} 4144: b087 sub sp, #28 4146: af00 add r7, sp, #0 4148: 60f8 str r0, [r7, #12] 414a: 4608 mov r0, r1 414c: 4611 mov r1, r2 414e: 461a mov r2, r3 4150: 4603 mov r3, r0 4152: 817b strh r3, [r7, #10] 4154: 460b mov r3, r1 4156: 813b strh r3, [r7, #8] 4158: 4613 mov r3, r2 415a: 80fb strh r3, [r7, #6] uint16_t tmpsmcr = 0; 415c: 2300 movs r3, #0 415e: 82fb strh r3, [r7, #22] uint16_t tmpccmr1 = 0; 4160: 2300 movs r3, #0 4162: 82bb strh r3, [r7, #20] uint16_t tmpccer = 0; 4164: 2300 movs r3, #0 4166: 827b strh r3, [r7, #18] assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 4168: 68fb ldr r3, [r7, #12] 416a: 891b ldrh r3, [r3, #8] 416c: 82fb strh r3, [r7, #22] /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; 416e: 68fb ldr r3, [r7, #12] 4170: 8b1b ldrh r3, [r3, #24] 4172: 82bb strh r3, [r7, #20] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 4174: 68fb ldr r3, [r7, #12] 4176: 8c1b ldrh r3, [r3, #32] 4178: 827b strh r3, [r7, #18] /* Set the encoder Mode */ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); 417a: 8afb ldrh r3, [r7, #22] 417c: f023 0307 bic.w r3, r3, #7 4180: 82fb strh r3, [r7, #22] tmpsmcr |= TIM_EncoderMode; 4182: 8afa ldrh r2, [r7, #22] 4184: 897b ldrh r3, [r7, #10] 4186: 4313 orrs r3, r2 4188: 82fb strh r3, [r7, #22] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); 418a: 8abb ldrh r3, [r7, #20] 418c: f423 7340 bic.w r3, r3, #768 ; 0x300 4190: f023 0303 bic.w r3, r3, #3 4194: 82bb strh r3, [r7, #20] tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; 4196: 8abb ldrh r3, [r7, #20] 4198: f443 7380 orr.w r3, r3, #256 ; 0x100 419c: f043 0301 orr.w r3, r3, #1 41a0: 82bb strh r3, [r7, #20] /* Set the TI1 and the TI2 Polarities */ tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); 41a2: 8a7b ldrh r3, [r7, #18] 41a4: f023 0322 bic.w r3, r3, #34 ; 0x22 41a8: 827b strh r3, [r7, #18] tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); 41aa: 88fb ldrh r3, [r7, #6] 41ac: 011b lsls r3, r3, #4 41ae: b29a uxth r2, r3 41b0: 893b ldrh r3, [r7, #8] 41b2: 4313 orrs r3, r2 41b4: b29a uxth r2, r3 41b6: 8a7b ldrh r3, [r7, #18] 41b8: 4313 orrs r3, r2 41ba: 827b strh r3, [r7, #18] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 41bc: 68fb ldr r3, [r7, #12] 41be: 8afa ldrh r2, [r7, #22] 41c0: 811a strh r2, [r3, #8] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; 41c2: 68fb ldr r3, [r7, #12] 41c4: 8aba ldrh r2, [r7, #20] 41c6: 831a strh r2, [r3, #24] /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 41c8: 68fb ldr r3, [r7, #12] 41ca: 8a7a ldrh r2, [r7, #18] 41cc: 841a strh r2, [r3, #32] } 41ce: bf00 nop 41d0: 371c adds r7, #28 41d2: 46bd mov sp, r7 41d4: bc80 pop {r7} 41d6: 4770 bx lr 000041d8 : * @arg TIM_ForcedAction_Active: Force active level on OC1REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. * @retval None */ void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { 41d8: b480 push {r7} 41da: b085 sub sp, #20 41dc: af00 add r7, sp, #0 41de: 6078 str r0, [r7, #4] 41e0: 460b mov r3, r1 41e2: 807b strh r3, [r7, #2] uint16_t tmpccmr1 = 0; 41e4: 2300 movs r3, #0 41e6: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr1 = TIMx->CCMR1; 41e8: 687b ldr r3, [r7, #4] 41ea: 8b1b ldrh r3, [r3, #24] 41ec: 81fb strh r3, [r7, #14] /* Reset the OC1M Bits */ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); 41ee: 89fb ldrh r3, [r7, #14] 41f0: f023 0370 bic.w r3, r3, #112 ; 0x70 41f4: 81fb strh r3, [r7, #14] /* Configure The Forced output Mode */ tmpccmr1 |= TIM_ForcedAction; 41f6: 89fa ldrh r2, [r7, #14] 41f8: 887b ldrh r3, [r7, #2] 41fa: 4313 orrs r3, r2 41fc: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; 41fe: 687b ldr r3, [r7, #4] 4200: 89fa ldrh r2, [r7, #14] 4202: 831a strh r2, [r3, #24] } 4204: bf00 nop 4206: 3714 adds r7, #20 4208: 46bd mov sp, r7 420a: bc80 pop {r7} 420c: 4770 bx lr 0000420e : * @arg TIM_ForcedAction_Active: Force active level on OC2REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. * @retval None */ void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { 420e: b480 push {r7} 4210: b085 sub sp, #20 4212: af00 add r7, sp, #0 4214: 6078 str r0, [r7, #4] 4216: 460b mov r3, r1 4218: 807b strh r3, [r7, #2] uint16_t tmpccmr1 = 0; 421a: 2300 movs r3, #0 421c: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr1 = TIMx->CCMR1; 421e: 687b ldr r3, [r7, #4] 4220: 8b1b ldrh r3, [r3, #24] 4222: 81fb strh r3, [r7, #14] /* Reset the OC2M Bits */ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); 4224: 89fb ldrh r3, [r7, #14] 4226: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 422a: 81fb strh r3, [r7, #14] /* Configure The Forced output Mode */ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); 422c: 887b ldrh r3, [r7, #2] 422e: 021b lsls r3, r3, #8 4230: b29a uxth r2, r3 4232: 89fb ldrh r3, [r7, #14] 4234: 4313 orrs r3, r2 4236: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; 4238: 687b ldr r3, [r7, #4] 423a: 89fa ldrh r2, [r7, #14] 423c: 831a strh r2, [r3, #24] } 423e: bf00 nop 4240: 3714 adds r7, #20 4242: 46bd mov sp, r7 4244: bc80 pop {r7} 4246: 4770 bx lr 00004248 : * @arg TIM_ForcedAction_Active: Force active level on OC3REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. * @retval None */ void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { 4248: b480 push {r7} 424a: b085 sub sp, #20 424c: af00 add r7, sp, #0 424e: 6078 str r0, [r7, #4] 4250: 460b mov r3, r1 4252: 807b strh r3, [r7, #2] uint16_t tmpccmr2 = 0; 4254: 2300 movs r3, #0 4256: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr2 = TIMx->CCMR2; 4258: 687b ldr r3, [r7, #4] 425a: 8b9b ldrh r3, [r3, #28] 425c: 81fb strh r3, [r7, #14] /* Reset the OC1M Bits */ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); 425e: 89fb ldrh r3, [r7, #14] 4260: f023 0370 bic.w r3, r3, #112 ; 0x70 4264: 81fb strh r3, [r7, #14] /* Configure The Forced output Mode */ tmpccmr2 |= TIM_ForcedAction; 4266: 89fa ldrh r2, [r7, #14] 4268: 887b ldrh r3, [r7, #2] 426a: 4313 orrs r3, r2 426c: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; 426e: 687b ldr r3, [r7, #4] 4270: 89fa ldrh r2, [r7, #14] 4272: 839a strh r2, [r3, #28] } 4274: bf00 nop 4276: 3714 adds r7, #20 4278: 46bd mov sp, r7 427a: bc80 pop {r7} 427c: 4770 bx lr 0000427e : * @arg TIM_ForcedAction_Active: Force active level on OC4REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. * @retval None */ void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { 427e: b480 push {r7} 4280: b085 sub sp, #20 4282: af00 add r7, sp, #0 4284: 6078 str r0, [r7, #4] 4286: 460b mov r3, r1 4288: 807b strh r3, [r7, #2] uint16_t tmpccmr2 = 0; 428a: 2300 movs r3, #0 428c: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr2 = TIMx->CCMR2; 428e: 687b ldr r3, [r7, #4] 4290: 8b9b ldrh r3, [r3, #28] 4292: 81fb strh r3, [r7, #14] /* Reset the OC2M Bits */ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); 4294: 89fb ldrh r3, [r7, #14] 4296: f423 43e0 bic.w r3, r3, #28672 ; 0x7000 429a: 81fb strh r3, [r7, #14] /* Configure The Forced output Mode */ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); 429c: 887b ldrh r3, [r7, #2] 429e: 021b lsls r3, r3, #8 42a0: b29a uxth r2, r3 42a2: 89fb ldrh r3, [r7, #14] 42a4: 4313 orrs r3, r2 42a6: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; 42a8: 687b ldr r3, [r7, #4] 42aa: 89fa ldrh r2, [r7, #14] 42ac: 839a strh r2, [r3, #28] } 42ae: bf00 nop 42b0: 3714 adds r7, #20 42b2: 46bd mov sp, r7 42b4: bc80 pop {r7} 42b6: 4770 bx lr 000042b8 : * @param NewState: new state of the TIMx peripheral Preload register * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) { 42b8: b480 push {r7} 42ba: b083 sub sp, #12 42bc: af00 add r7, sp, #0 42be: 6078 str r0, [r7, #4] 42c0: 460b mov r3, r1 42c2: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 42c4: 78fb ldrb r3, [r7, #3] 42c6: 2b00 cmp r3, #0 42c8: d008 beq.n 42dc { /* Set the ARR Preload Bit */ TIMx->CR1 |= TIM_CR1_ARPE; 42ca: 687b ldr r3, [r7, #4] 42cc: 881b ldrh r3, [r3, #0] 42ce: b29b uxth r3, r3 42d0: f043 0380 orr.w r3, r3, #128 ; 0x80 42d4: b29a uxth r2, r3 42d6: 687b ldr r3, [r7, #4] 42d8: 801a strh r2, [r3, #0] else { /* Reset the ARR Preload Bit */ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); } } 42da: e007 b.n 42ec TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); 42dc: 687b ldr r3, [r7, #4] 42de: 881b ldrh r3, [r3, #0] 42e0: b29b uxth r3, r3 42e2: f023 0380 bic.w r3, r3, #128 ; 0x80 42e6: b29a uxth r2, r3 42e8: 687b ldr r3, [r7, #4] 42ea: 801a strh r2, [r3, #0] } 42ec: bf00 nop 42ee: 370c adds r7, #12 42f0: 46bd mov sp, r7 42f2: bc80 pop {r7} 42f4: 4770 bx lr 000042f6 : * @param NewState: new state of the Commutation event. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) { 42f6: b480 push {r7} 42f8: b083 sub sp, #12 42fa: af00 add r7, sp, #0 42fc: 6078 str r0, [r7, #4] 42fe: 460b mov r3, r1 4300: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 4302: 78fb ldrb r3, [r7, #3] 4304: 2b00 cmp r3, #0 4306: d008 beq.n 431a { /* Set the COM Bit */ TIMx->CR2 |= TIM_CR2_CCUS; 4308: 687b ldr r3, [r7, #4] 430a: 889b ldrh r3, [r3, #4] 430c: b29b uxth r3, r3 430e: f043 0304 orr.w r3, r3, #4 4312: b29a uxth r2, r3 4314: 687b ldr r3, [r7, #4] 4316: 809a strh r2, [r3, #4] else { /* Reset the COM Bit */ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); } } 4318: e007 b.n 432a TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); 431a: 687b ldr r3, [r7, #4] 431c: 889b ldrh r3, [r3, #4] 431e: b29b uxth r3, r3 4320: f023 0304 bic.w r3, r3, #4 4324: b29a uxth r2, r3 4326: 687b ldr r3, [r7, #4] 4328: 809a strh r2, [r3, #4] } 432a: bf00 nop 432c: 370c adds r7, #12 432e: 46bd mov sp, r7 4330: bc80 pop {r7} 4332: 4770 bx lr 00004334 : * @param NewState: new state of the Capture Compare DMA source * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) { 4334: b480 push {r7} 4336: b083 sub sp, #12 4338: af00 add r7, sp, #0 433a: 6078 str r0, [r7, #4] 433c: 460b mov r3, r1 433e: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 4340: 78fb ldrb r3, [r7, #3] 4342: 2b00 cmp r3, #0 4344: d008 beq.n 4358 { /* Set the CCDS Bit */ TIMx->CR2 |= TIM_CR2_CCDS; 4346: 687b ldr r3, [r7, #4] 4348: 889b ldrh r3, [r3, #4] 434a: b29b uxth r3, r3 434c: f043 0308 orr.w r3, r3, #8 4350: b29a uxth r2, r3 4352: 687b ldr r3, [r7, #4] 4354: 809a strh r2, [r3, #4] else { /* Reset the CCDS Bit */ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); } } 4356: e007 b.n 4368 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); 4358: 687b ldr r3, [r7, #4] 435a: 889b ldrh r3, [r3, #4] 435c: b29b uxth r3, r3 435e: f023 0308 bic.w r3, r3, #8 4362: b29a uxth r2, r3 4364: 687b ldr r3, [r7, #4] 4366: 809a strh r2, [r3, #4] } 4368: bf00 nop 436a: 370c adds r7, #12 436c: 46bd mov sp, r7 436e: bc80 pop {r7} 4370: 4770 bx lr 00004372 : * @param NewState: new state of the Capture Compare Preload Control bit * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) { 4372: b480 push {r7} 4374: b083 sub sp, #12 4376: af00 add r7, sp, #0 4378: 6078 str r0, [r7, #4] 437a: 460b mov r3, r1 437c: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_TIM_LIST5_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 437e: 78fb ldrb r3, [r7, #3] 4380: 2b00 cmp r3, #0 4382: d008 beq.n 4396 { /* Set the CCPC Bit */ TIMx->CR2 |= TIM_CR2_CCPC; 4384: 687b ldr r3, [r7, #4] 4386: 889b ldrh r3, [r3, #4] 4388: b29b uxth r3, r3 438a: f043 0301 orr.w r3, r3, #1 438e: b29a uxth r2, r3 4390: 687b ldr r3, [r7, #4] 4392: 809a strh r2, [r3, #4] else { /* Reset the CCPC Bit */ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); } } 4394: e007 b.n 43a6 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); 4396: 687b ldr r3, [r7, #4] 4398: 889b ldrh r3, [r3, #4] 439a: b29b uxth r3, r3 439c: f023 0301 bic.w r3, r3, #1 43a0: b29a uxth r2, r3 43a2: 687b ldr r3, [r7, #4] 43a4: 809a strh r2, [r3, #4] } 43a6: bf00 nop 43a8: 370c adds r7, #12 43aa: 46bd mov sp, r7 43ac: bc80 pop {r7} 43ae: 4770 bx lr 000043b0 : * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { 43b0: b480 push {r7} 43b2: b085 sub sp, #20 43b4: af00 add r7, sp, #0 43b6: 6078 str r0, [r7, #4] 43b8: 460b mov r3, r1 43ba: 807b strh r3, [r7, #2] uint16_t tmpccmr1 = 0; 43bc: 2300 movs r3, #0 43be: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr1 = TIMx->CCMR1; 43c0: 687b ldr r3, [r7, #4] 43c2: 8b1b ldrh r3, [r3, #24] 43c4: 81fb strh r3, [r7, #14] /* Reset the OC1PE Bit */ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); 43c6: 89fb ldrh r3, [r7, #14] 43c8: f023 0308 bic.w r3, r3, #8 43cc: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Preload feature */ tmpccmr1 |= TIM_OCPreload; 43ce: 89fa ldrh r2, [r7, #14] 43d0: 887b ldrh r3, [r7, #2] 43d2: 4313 orrs r3, r2 43d4: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; 43d6: 687b ldr r3, [r7, #4] 43d8: 89fa ldrh r2, [r7, #14] 43da: 831a strh r2, [r3, #24] } 43dc: bf00 nop 43de: 3714 adds r7, #20 43e0: 46bd mov sp, r7 43e2: bc80 pop {r7} 43e4: 4770 bx lr 000043e6 : * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { 43e6: b480 push {r7} 43e8: b085 sub sp, #20 43ea: af00 add r7, sp, #0 43ec: 6078 str r0, [r7, #4] 43ee: 460b mov r3, r1 43f0: 807b strh r3, [r7, #2] uint16_t tmpccmr1 = 0; 43f2: 2300 movs r3, #0 43f4: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr1 = TIMx->CCMR1; 43f6: 687b ldr r3, [r7, #4] 43f8: 8b1b ldrh r3, [r3, #24] 43fa: 81fb strh r3, [r7, #14] /* Reset the OC2PE Bit */ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); 43fc: 89fb ldrh r3, [r7, #14] 43fe: f423 6300 bic.w r3, r3, #2048 ; 0x800 4402: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Preload feature */ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); 4404: 887b ldrh r3, [r7, #2] 4406: 021b lsls r3, r3, #8 4408: b29a uxth r2, r3 440a: 89fb ldrh r3, [r7, #14] 440c: 4313 orrs r3, r2 440e: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; 4410: 687b ldr r3, [r7, #4] 4412: 89fa ldrh r2, [r7, #14] 4414: 831a strh r2, [r3, #24] } 4416: bf00 nop 4418: 3714 adds r7, #20 441a: 46bd mov sp, r7 441c: bc80 pop {r7} 441e: 4770 bx lr 00004420 : * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { 4420: b480 push {r7} 4422: b085 sub sp, #20 4424: af00 add r7, sp, #0 4426: 6078 str r0, [r7, #4] 4428: 460b mov r3, r1 442a: 807b strh r3, [r7, #2] uint16_t tmpccmr2 = 0; 442c: 2300 movs r3, #0 442e: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr2 = TIMx->CCMR2; 4430: 687b ldr r3, [r7, #4] 4432: 8b9b ldrh r3, [r3, #28] 4434: 81fb strh r3, [r7, #14] /* Reset the OC3PE Bit */ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); 4436: 89fb ldrh r3, [r7, #14] 4438: f023 0308 bic.w r3, r3, #8 443c: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Preload feature */ tmpccmr2 |= TIM_OCPreload; 443e: 89fa ldrh r2, [r7, #14] 4440: 887b ldrh r3, [r7, #2] 4442: 4313 orrs r3, r2 4444: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; 4446: 687b ldr r3, [r7, #4] 4448: 89fa ldrh r2, [r7, #14] 444a: 839a strh r2, [r3, #28] } 444c: bf00 nop 444e: 3714 adds r7, #20 4450: 46bd mov sp, r7 4452: bc80 pop {r7} 4454: 4770 bx lr 00004456 : * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { 4456: b480 push {r7} 4458: b085 sub sp, #20 445a: af00 add r7, sp, #0 445c: 6078 str r0, [r7, #4] 445e: 460b mov r3, r1 4460: 807b strh r3, [r7, #2] uint16_t tmpccmr2 = 0; 4462: 2300 movs r3, #0 4464: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr2 = TIMx->CCMR2; 4466: 687b ldr r3, [r7, #4] 4468: 8b9b ldrh r3, [r3, #28] 446a: 81fb strh r3, [r7, #14] /* Reset the OC4PE Bit */ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); 446c: 89fb ldrh r3, [r7, #14] 446e: f423 6300 bic.w r3, r3, #2048 ; 0x800 4472: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Preload feature */ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); 4474: 887b ldrh r3, [r7, #2] 4476: 021b lsls r3, r3, #8 4478: b29a uxth r2, r3 447a: 89fb ldrh r3, [r7, #14] 447c: 4313 orrs r3, r2 447e: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; 4480: 687b ldr r3, [r7, #4] 4482: 89fa ldrh r2, [r7, #14] 4484: 839a strh r2, [r3, #28] } 4486: bf00 nop 4488: 3714 adds r7, #20 448a: 46bd mov sp, r7 448c: bc80 pop {r7} 448e: 4770 bx lr 00004490 : * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { 4490: b480 push {r7} 4492: b085 sub sp, #20 4494: af00 add r7, sp, #0 4496: 6078 str r0, [r7, #4] 4498: 460b mov r3, r1 449a: 807b strh r3, [r7, #2] uint16_t tmpccmr1 = 0; 449c: 2300 movs r3, #0 449e: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; 44a0: 687b ldr r3, [r7, #4] 44a2: 8b1b ldrh r3, [r3, #24] 44a4: 81fb strh r3, [r7, #14] /* Reset the OC1FE Bit */ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); 44a6: 89fb ldrh r3, [r7, #14] 44a8: f023 0304 bic.w r3, r3, #4 44ac: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Fast Bit */ tmpccmr1 |= TIM_OCFast; 44ae: 89fa ldrh r2, [r7, #14] 44b0: 887b ldrh r3, [r7, #2] 44b2: 4313 orrs r3, r2 44b4: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; 44b6: 687b ldr r3, [r7, #4] 44b8: 89fa ldrh r2, [r7, #14] 44ba: 831a strh r2, [r3, #24] } 44bc: bf00 nop 44be: 3714 adds r7, #20 44c0: 46bd mov sp, r7 44c2: bc80 pop {r7} 44c4: 4770 bx lr 000044c6 : * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { 44c6: b480 push {r7} 44c8: b085 sub sp, #20 44ca: af00 add r7, sp, #0 44cc: 6078 str r0, [r7, #4] 44ce: 460b mov r3, r1 44d0: 807b strh r3, [r7, #2] uint16_t tmpccmr1 = 0; 44d2: 2300 movs r3, #0 44d4: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; 44d6: 687b ldr r3, [r7, #4] 44d8: 8b1b ldrh r3, [r3, #24] 44da: 81fb strh r3, [r7, #14] /* Reset the OC2FE Bit */ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); 44dc: 89fb ldrh r3, [r7, #14] 44de: f423 6380 bic.w r3, r3, #1024 ; 0x400 44e2: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Fast Bit */ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); 44e4: 887b ldrh r3, [r7, #2] 44e6: 021b lsls r3, r3, #8 44e8: b29a uxth r2, r3 44ea: 89fb ldrh r3, [r7, #14] 44ec: 4313 orrs r3, r2 44ee: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; 44f0: 687b ldr r3, [r7, #4] 44f2: 89fa ldrh r2, [r7, #14] 44f4: 831a strh r2, [r3, #24] } 44f6: bf00 nop 44f8: 3714 adds r7, #20 44fa: 46bd mov sp, r7 44fc: bc80 pop {r7} 44fe: 4770 bx lr 00004500 : * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { 4500: b480 push {r7} 4502: b085 sub sp, #20 4504: af00 add r7, sp, #0 4506: 6078 str r0, [r7, #4] 4508: 460b mov r3, r1 450a: 807b strh r3, [r7, #2] uint16_t tmpccmr2 = 0; 450c: 2300 movs r3, #0 450e: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; 4510: 687b ldr r3, [r7, #4] 4512: 8b9b ldrh r3, [r3, #28] 4514: 81fb strh r3, [r7, #14] /* Reset the OC3FE Bit */ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); 4516: 89fb ldrh r3, [r7, #14] 4518: f023 0304 bic.w r3, r3, #4 451c: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Fast Bit */ tmpccmr2 |= TIM_OCFast; 451e: 89fa ldrh r2, [r7, #14] 4520: 887b ldrh r3, [r7, #2] 4522: 4313 orrs r3, r2 4524: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmr2; 4526: 687b ldr r3, [r7, #4] 4528: 89fa ldrh r2, [r7, #14] 452a: 839a strh r2, [r3, #28] } 452c: bf00 nop 452e: 3714 adds r7, #20 4530: 46bd mov sp, r7 4532: bc80 pop {r7} 4534: 4770 bx lr 00004536 : * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { 4536: b480 push {r7} 4538: b085 sub sp, #20 453a: af00 add r7, sp, #0 453c: 6078 str r0, [r7, #4] 453e: 460b mov r3, r1 4540: 807b strh r3, [r7, #2] uint16_t tmpccmr2 = 0; 4542: 2300 movs r3, #0 4544: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; 4546: 687b ldr r3, [r7, #4] 4548: 8b9b ldrh r3, [r3, #28] 454a: 81fb strh r3, [r7, #14] /* Reset the OC4FE Bit */ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); 454c: 89fb ldrh r3, [r7, #14] 454e: f423 6380 bic.w r3, r3, #1024 ; 0x400 4552: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Fast Bit */ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); 4554: 887b ldrh r3, [r7, #2] 4556: 021b lsls r3, r3, #8 4558: b29a uxth r2, r3 455a: 89fb ldrh r3, [r7, #14] 455c: 4313 orrs r3, r2 455e: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmr2; 4560: 687b ldr r3, [r7, #4] 4562: 89fa ldrh r2, [r7, #14] 4564: 839a strh r2, [r3, #28] } 4566: bf00 nop 4568: 3714 adds r7, #20 456a: 46bd mov sp, r7 456c: bc80 pop {r7} 456e: 4770 bx lr 00004570 : * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { 4570: b480 push {r7} 4572: b085 sub sp, #20 4574: af00 add r7, sp, #0 4576: 6078 str r0, [r7, #4] 4578: 460b mov r3, r1 457a: 807b strh r3, [r7, #2] uint16_t tmpccmr1 = 0; 457c: 2300 movs r3, #0 457e: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr1 = TIMx->CCMR1; 4580: 687b ldr r3, [r7, #4] 4582: 8b1b ldrh r3, [r3, #24] 4584: 81fb strh r3, [r7, #14] /* Reset the OC1CE Bit */ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); 4586: 89fb ldrh r3, [r7, #14] 4588: f023 0380 bic.w r3, r3, #128 ; 0x80 458c: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Clear Bit */ tmpccmr1 |= TIM_OCClear; 458e: 89fa ldrh r2, [r7, #14] 4590: 887b ldrh r3, [r7, #2] 4592: 4313 orrs r3, r2 4594: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; 4596: 687b ldr r3, [r7, #4] 4598: 89fa ldrh r2, [r7, #14] 459a: 831a strh r2, [r3, #24] } 459c: bf00 nop 459e: 3714 adds r7, #20 45a0: 46bd mov sp, r7 45a2: bc80 pop {r7} 45a4: 4770 bx lr 000045a6 : * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { 45a6: b480 push {r7} 45a8: b085 sub sp, #20 45aa: af00 add r7, sp, #0 45ac: 6078 str r0, [r7, #4] 45ae: 460b mov r3, r1 45b0: 807b strh r3, [r7, #2] uint16_t tmpccmr1 = 0; 45b2: 2300 movs r3, #0 45b4: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr1 = TIMx->CCMR1; 45b6: 687b ldr r3, [r7, #4] 45b8: 8b1b ldrh r3, [r3, #24] 45ba: 81fb strh r3, [r7, #14] /* Reset the OC2CE Bit */ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); 45bc: 89fb ldrh r3, [r7, #14] 45be: f3c3 030e ubfx r3, r3, #0, #15 45c2: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Clear Bit */ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); 45c4: 887b ldrh r3, [r7, #2] 45c6: 021b lsls r3, r3, #8 45c8: b29a uxth r2, r3 45ca: 89fb ldrh r3, [r7, #14] 45cc: 4313 orrs r3, r2 45ce: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; 45d0: 687b ldr r3, [r7, #4] 45d2: 89fa ldrh r2, [r7, #14] 45d4: 831a strh r2, [r3, #24] } 45d6: bf00 nop 45d8: 3714 adds r7, #20 45da: 46bd mov sp, r7 45dc: bc80 pop {r7} 45de: 4770 bx lr 000045e0 : * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { 45e0: b480 push {r7} 45e2: b085 sub sp, #20 45e4: af00 add r7, sp, #0 45e6: 6078 str r0, [r7, #4] 45e8: 460b mov r3, r1 45ea: 807b strh r3, [r7, #2] uint16_t tmpccmr2 = 0; 45ec: 2300 movs r3, #0 45ee: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr2 = TIMx->CCMR2; 45f0: 687b ldr r3, [r7, #4] 45f2: 8b9b ldrh r3, [r3, #28] 45f4: 81fb strh r3, [r7, #14] /* Reset the OC3CE Bit */ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); 45f6: 89fb ldrh r3, [r7, #14] 45f8: f023 0380 bic.w r3, r3, #128 ; 0x80 45fc: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Clear Bit */ tmpccmr2 |= TIM_OCClear; 45fe: 89fa ldrh r2, [r7, #14] 4600: 887b ldrh r3, [r7, #2] 4602: 4313 orrs r3, r2 4604: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; 4606: 687b ldr r3, [r7, #4] 4608: 89fa ldrh r2, [r7, #14] 460a: 839a strh r2, [r3, #28] } 460c: bf00 nop 460e: 3714 adds r7, #20 4610: 46bd mov sp, r7 4612: bc80 pop {r7} 4614: 4770 bx lr 00004616 : * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { 4616: b480 push {r7} 4618: b085 sub sp, #20 461a: af00 add r7, sp, #0 461c: 6078 str r0, [r7, #4] 461e: 460b mov r3, r1 4620: 807b strh r3, [r7, #2] uint16_t tmpccmr2 = 0; 4622: 2300 movs r3, #0 4624: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr2 = TIMx->CCMR2; 4626: 687b ldr r3, [r7, #4] 4628: 8b9b ldrh r3, [r3, #28] 462a: 81fb strh r3, [r7, #14] /* Reset the OC4CE Bit */ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); 462c: 89fb ldrh r3, [r7, #14] 462e: f3c3 030e ubfx r3, r3, #0, #15 4632: 81fb strh r3, [r7, #14] /* Enable or Disable the Output Compare Clear Bit */ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); 4634: 887b ldrh r3, [r7, #2] 4636: 021b lsls r3, r3, #8 4638: b29a uxth r2, r3 463a: 89fb ldrh r3, [r7, #14] 463c: 4313 orrs r3, r2 463e: 81fb strh r3, [r7, #14] /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; 4640: 687b ldr r3, [r7, #4] 4642: 89fa ldrh r2, [r7, #14] 4644: 839a strh r2, [r3, #28] } 4646: bf00 nop 4648: 3714 adds r7, #20 464a: 46bd mov sp, r7 464c: bc80 pop {r7} 464e: 4770 bx lr 00004650 : * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { 4650: b480 push {r7} 4652: b085 sub sp, #20 4654: af00 add r7, sp, #0 4656: 6078 str r0, [r7, #4] 4658: 460b mov r3, r1 465a: 807b strh r3, [r7, #2] uint16_t tmpccer = 0; 465c: 2300 movs r3, #0 465e: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; 4660: 687b ldr r3, [r7, #4] 4662: 8c1b ldrh r3, [r3, #32] 4664: 81fb strh r3, [r7, #14] /* Set or Reset the CC1P Bit */ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); 4666: 89fb ldrh r3, [r7, #14] 4668: f023 0302 bic.w r3, r3, #2 466c: 81fb strh r3, [r7, #14] tmpccer |= TIM_OCPolarity; 466e: 89fa ldrh r2, [r7, #14] 4670: 887b ldrh r3, [r7, #2] 4672: 4313 orrs r3, r2 4674: 81fb strh r3, [r7, #14] /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; 4676: 687b ldr r3, [r7, #4] 4678: 89fa ldrh r2, [r7, #14] 467a: 841a strh r2, [r3, #32] } 467c: bf00 nop 467e: 3714 adds r7, #20 4680: 46bd mov sp, r7 4682: bc80 pop {r7} 4684: 4770 bx lr 00004686 : * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None */ void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { 4686: b480 push {r7} 4688: b085 sub sp, #20 468a: af00 add r7, sp, #0 468c: 6078 str r0, [r7, #4] 468e: 460b mov r3, r1 4690: 807b strh r3, [r7, #2] uint16_t tmpccer = 0; 4692: 2300 movs r3, #0 4694: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; 4696: 687b ldr r3, [r7, #4] 4698: 8c1b ldrh r3, [r3, #32] 469a: 81fb strh r3, [r7, #14] /* Set or Reset the CC1NP Bit */ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); 469c: 89fb ldrh r3, [r7, #14] 469e: f023 0308 bic.w r3, r3, #8 46a2: 81fb strh r3, [r7, #14] tmpccer |= TIM_OCNPolarity; 46a4: 89fa ldrh r2, [r7, #14] 46a6: 887b ldrh r3, [r7, #2] 46a8: 4313 orrs r3, r2 46aa: 81fb strh r3, [r7, #14] /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; 46ac: 687b ldr r3, [r7, #4] 46ae: 89fa ldrh r2, [r7, #14] 46b0: 841a strh r2, [r3, #32] } 46b2: bf00 nop 46b4: 3714 adds r7, #20 46b6: 46bd mov sp, r7 46b8: bc80 pop {r7} 46ba: 4770 bx lr 000046bc : * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { 46bc: b480 push {r7} 46be: b085 sub sp, #20 46c0: af00 add r7, sp, #0 46c2: 6078 str r0, [r7, #4] 46c4: 460b mov r3, r1 46c6: 807b strh r3, [r7, #2] uint16_t tmpccer = 0; 46c8: 2300 movs r3, #0 46ca: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; 46cc: 687b ldr r3, [r7, #4] 46ce: 8c1b ldrh r3, [r3, #32] 46d0: 81fb strh r3, [r7, #14] /* Set or Reset the CC2P Bit */ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); 46d2: 89fb ldrh r3, [r7, #14] 46d4: f023 0320 bic.w r3, r3, #32 46d8: 81fb strh r3, [r7, #14] tmpccer |= (uint16_t)(TIM_OCPolarity << 4); 46da: 887b ldrh r3, [r7, #2] 46dc: 011b lsls r3, r3, #4 46de: b29a uxth r2, r3 46e0: 89fb ldrh r3, [r7, #14] 46e2: 4313 orrs r3, r2 46e4: 81fb strh r3, [r7, #14] /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; 46e6: 687b ldr r3, [r7, #4] 46e8: 89fa ldrh r2, [r7, #14] 46ea: 841a strh r2, [r3, #32] } 46ec: bf00 nop 46ee: 3714 adds r7, #20 46f0: 46bd mov sp, r7 46f2: bc80 pop {r7} 46f4: 4770 bx lr 000046f6 : * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None */ void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { 46f6: b480 push {r7} 46f8: b085 sub sp, #20 46fa: af00 add r7, sp, #0 46fc: 6078 str r0, [r7, #4] 46fe: 460b mov r3, r1 4700: 807b strh r3, [r7, #2] uint16_t tmpccer = 0; 4702: 2300 movs r3, #0 4704: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; 4706: 687b ldr r3, [r7, #4] 4708: 8c1b ldrh r3, [r3, #32] 470a: 81fb strh r3, [r7, #14] /* Set or Reset the CC2NP Bit */ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); 470c: 89fb ldrh r3, [r7, #14] 470e: f023 0380 bic.w r3, r3, #128 ; 0x80 4712: 81fb strh r3, [r7, #14] tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); 4714: 887b ldrh r3, [r7, #2] 4716: 011b lsls r3, r3, #4 4718: b29a uxth r2, r3 471a: 89fb ldrh r3, [r7, #14] 471c: 4313 orrs r3, r2 471e: 81fb strh r3, [r7, #14] /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; 4720: 687b ldr r3, [r7, #4] 4722: 89fa ldrh r2, [r7, #14] 4724: 841a strh r2, [r3, #32] } 4726: bf00 nop 4728: 3714 adds r7, #20 472a: 46bd mov sp, r7 472c: bc80 pop {r7} 472e: 4770 bx lr 00004730 : * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { 4730: b480 push {r7} 4732: b085 sub sp, #20 4734: af00 add r7, sp, #0 4736: 6078 str r0, [r7, #4] 4738: 460b mov r3, r1 473a: 807b strh r3, [r7, #2] uint16_t tmpccer = 0; 473c: 2300 movs r3, #0 473e: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; 4740: 687b ldr r3, [r7, #4] 4742: 8c1b ldrh r3, [r3, #32] 4744: 81fb strh r3, [r7, #14] /* Set or Reset the CC3P Bit */ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); 4746: 89fb ldrh r3, [r7, #14] 4748: f423 7300 bic.w r3, r3, #512 ; 0x200 474c: 81fb strh r3, [r7, #14] tmpccer |= (uint16_t)(TIM_OCPolarity << 8); 474e: 887b ldrh r3, [r7, #2] 4750: 021b lsls r3, r3, #8 4752: b29a uxth r2, r3 4754: 89fb ldrh r3, [r7, #14] 4756: 4313 orrs r3, r2 4758: 81fb strh r3, [r7, #14] /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; 475a: 687b ldr r3, [r7, #4] 475c: 89fa ldrh r2, [r7, #14] 475e: 841a strh r2, [r3, #32] } 4760: bf00 nop 4762: 3714 adds r7, #20 4764: 46bd mov sp, r7 4766: bc80 pop {r7} 4768: 4770 bx lr 0000476a : * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None */ void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { 476a: b480 push {r7} 476c: b085 sub sp, #20 476e: af00 add r7, sp, #0 4770: 6078 str r0, [r7, #4] 4772: 460b mov r3, r1 4774: 807b strh r3, [r7, #2] uint16_t tmpccer = 0; 4776: 2300 movs r3, #0 4778: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; 477a: 687b ldr r3, [r7, #4] 477c: 8c1b ldrh r3, [r3, #32] 477e: 81fb strh r3, [r7, #14] /* Set or Reset the CC3NP Bit */ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); 4780: 89fb ldrh r3, [r7, #14] 4782: f423 6300 bic.w r3, r3, #2048 ; 0x800 4786: 81fb strh r3, [r7, #14] tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); 4788: 887b ldrh r3, [r7, #2] 478a: 021b lsls r3, r3, #8 478c: b29a uxth r2, r3 478e: 89fb ldrh r3, [r7, #14] 4790: 4313 orrs r3, r2 4792: 81fb strh r3, [r7, #14] /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; 4794: 687b ldr r3, [r7, #4] 4796: 89fa ldrh r2, [r7, #14] 4798: 841a strh r2, [r3, #32] } 479a: bf00 nop 479c: 3714 adds r7, #20 479e: 46bd mov sp, r7 47a0: bc80 pop {r7} 47a2: 4770 bx lr 000047a4 : * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { 47a4: b480 push {r7} 47a6: b085 sub sp, #20 47a8: af00 add r7, sp, #0 47aa: 6078 str r0, [r7, #4] 47ac: 460b mov r3, r1 47ae: 807b strh r3, [r7, #2] uint16_t tmpccer = 0; 47b0: 2300 movs r3, #0 47b2: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; 47b4: 687b ldr r3, [r7, #4] 47b6: 8c1b ldrh r3, [r3, #32] 47b8: 81fb strh r3, [r7, #14] /* Set or Reset the CC4P Bit */ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); 47ba: 89fb ldrh r3, [r7, #14] 47bc: f423 5300 bic.w r3, r3, #8192 ; 0x2000 47c0: 81fb strh r3, [r7, #14] tmpccer |= (uint16_t)(TIM_OCPolarity << 12); 47c2: 887b ldrh r3, [r7, #2] 47c4: 031b lsls r3, r3, #12 47c6: b29a uxth r2, r3 47c8: 89fb ldrh r3, [r7, #14] 47ca: 4313 orrs r3, r2 47cc: 81fb strh r3, [r7, #14] /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; 47ce: 687b ldr r3, [r7, #4] 47d0: 89fa ldrh r2, [r7, #14] 47d2: 841a strh r2, [r3, #32] } 47d4: bf00 nop 47d6: 3714 adds r7, #20 47d8: 46bd mov sp, r7 47da: bc80 pop {r7} 47dc: 4770 bx lr 000047de : * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. * @retval None */ void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) { 47de: b480 push {r7} 47e0: b085 sub sp, #20 47e2: af00 add r7, sp, #0 47e4: 6078 str r0, [r7, #4] 47e6: 460b mov r3, r1 47e8: 807b strh r3, [r7, #2] 47ea: 4613 mov r3, r2 47ec: 803b strh r3, [r7, #0] uint16_t tmp = 0; 47ee: 2300 movs r3, #0 47f0: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); assert_param(IS_TIM_CHANNEL(TIM_Channel)); assert_param(IS_TIM_CCX(TIM_CCx)); tmp = CCER_CCE_Set << TIM_Channel; 47f2: 887b ldrh r3, [r7, #2] 47f4: 2201 movs r2, #1 47f6: fa02 f303 lsl.w r3, r2, r3 47fa: 81fb strh r3, [r7, #14] /* Reset the CCxE Bit */ TIMx->CCER &= (uint16_t)~ tmp; 47fc: 687b ldr r3, [r7, #4] 47fe: 8c1b ldrh r3, [r3, #32] 4800: b29a uxth r2, r3 4802: 89fb ldrh r3, [r7, #14] 4804: 43db mvns r3, r3 4806: b29b uxth r3, r3 4808: 4013 ands r3, r2 480a: b29a uxth r2, r3 480c: 687b ldr r3, [r7, #4] 480e: 841a strh r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); 4810: 687b ldr r3, [r7, #4] 4812: 8c1b ldrh r3, [r3, #32] 4814: b29a uxth r2, r3 4816: 8839 ldrh r1, [r7, #0] 4818: 887b ldrh r3, [r7, #2] 481a: fa01 f303 lsl.w r3, r1, r3 481e: b29b uxth r3, r3 4820: 4313 orrs r3, r2 4822: b29a uxth r2, r3 4824: 687b ldr r3, [r7, #4] 4826: 841a strh r2, [r3, #32] } 4828: bf00 nop 482a: 3714 adds r7, #20 482c: 46bd mov sp, r7 482e: bc80 pop {r7} 4830: 4770 bx lr 00004832 : * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. * @retval None */ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) { 4832: b480 push {r7} 4834: b085 sub sp, #20 4836: af00 add r7, sp, #0 4838: 6078 str r0, [r7, #4] 483a: 460b mov r3, r1 483c: 807b strh r3, [r7, #2] 483e: 4613 mov r3, r2 4840: 803b strh r3, [r7, #0] uint16_t tmp = 0; 4842: 2300 movs r3, #0 4844: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); assert_param(IS_TIM_CCXN(TIM_CCxN)); tmp = CCER_CCNE_Set << TIM_Channel; 4846: 887b ldrh r3, [r7, #2] 4848: 2204 movs r2, #4 484a: fa02 f303 lsl.w r3, r2, r3 484e: 81fb strh r3, [r7, #14] /* Reset the CCxNE Bit */ TIMx->CCER &= (uint16_t) ~tmp; 4850: 687b ldr r3, [r7, #4] 4852: 8c1b ldrh r3, [r3, #32] 4854: b29a uxth r2, r3 4856: 89fb ldrh r3, [r7, #14] 4858: 43db mvns r3, r3 485a: b29b uxth r3, r3 485c: 4013 ands r3, r2 485e: b29a uxth r2, r3 4860: 687b ldr r3, [r7, #4] 4862: 841a strh r2, [r3, #32] /* Set or reset the CCxNE Bit */ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); 4864: 687b ldr r3, [r7, #4] 4866: 8c1b ldrh r3, [r3, #32] 4868: b29a uxth r2, r3 486a: 8839 ldrh r1, [r7, #0] 486c: 887b ldrh r3, [r7, #2] 486e: fa01 f303 lsl.w r3, r1, r3 4872: b29b uxth r3, r3 4874: 4313 orrs r3, r2 4876: b29a uxth r2, r3 4878: 687b ldr r3, [r7, #4] 487a: 841a strh r2, [r3, #32] } 487c: bf00 nop 487e: 3714 adds r7, #20 4880: 46bd mov sp, r7 4882: bc80 pop {r7} 4884: 4770 bx lr 00004886 : * @arg TIM_ForcedAction_Active * @arg TIM_ForcedAction_InActive * @retval None */ void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) { 4886: b480 push {r7} 4888: b085 sub sp, #20 488a: af00 add r7, sp, #0 488c: 6078 str r0, [r7, #4] 488e: 460b mov r3, r1 4890: 807b strh r3, [r7, #2] 4892: 4613 mov r3, r2 4894: 803b strh r3, [r7, #0] uint32_t tmp = 0; 4896: 2300 movs r3, #0 4898: 60fb str r3, [r7, #12] uint16_t tmp1 = 0; 489a: 2300 movs r3, #0 489c: 817b strh r3, [r7, #10] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); assert_param(IS_TIM_CHANNEL(TIM_Channel)); assert_param(IS_TIM_OCM(TIM_OCMode)); tmp = (uint32_t) TIMx; 489e: 687b ldr r3, [r7, #4] 48a0: 60fb str r3, [r7, #12] tmp += CCMR_Offset; 48a2: 68fb ldr r3, [r7, #12] 48a4: 3318 adds r3, #24 48a6: 60fb str r3, [r7, #12] tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; 48a8: 887b ldrh r3, [r7, #2] 48aa: 2201 movs r2, #1 48ac: fa02 f303 lsl.w r3, r2, r3 48b0: 817b strh r3, [r7, #10] /* Disable the Channel: Reset the CCxE Bit */ TIMx->CCER &= (uint16_t) ~tmp1; 48b2: 687b ldr r3, [r7, #4] 48b4: 8c1b ldrh r3, [r3, #32] 48b6: b29a uxth r2, r3 48b8: 897b ldrh r3, [r7, #10] 48ba: 43db mvns r3, r3 48bc: b29b uxth r3, r3 48be: 4013 ands r3, r2 48c0: b29a uxth r2, r3 48c2: 687b ldr r3, [r7, #4] 48c4: 841a strh r2, [r3, #32] if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) 48c6: 887b ldrh r3, [r7, #2] 48c8: 2b00 cmp r3, #0 48ca: d002 beq.n 48d2 48cc: 887b ldrh r3, [r7, #2] 48ce: 2b08 cmp r3, #8 48d0: d113 bne.n 48fa { tmp += (TIM_Channel>>1); 48d2: 887b ldrh r3, [r7, #2] 48d4: 085b lsrs r3, r3, #1 48d6: b29b uxth r3, r3 48d8: 461a mov r2, r3 48da: 68fb ldr r3, [r7, #12] 48dc: 4413 add r3, r2 48de: 60fb str r3, [r7, #12] /* Reset the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); 48e0: 68fb ldr r3, [r7, #12] 48e2: 681a ldr r2, [r3, #0] 48e4: 68fb ldr r3, [r7, #12] 48e6: f022 0270 bic.w r2, r2, #112 ; 0x70 48ea: 601a str r2, [r3, #0] /* Configure the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp |= TIM_OCMode; 48ec: 68fb ldr r3, [r7, #12] 48ee: 6819 ldr r1, [r3, #0] 48f0: 883a ldrh r2, [r7, #0] 48f2: 68fb ldr r3, [r7, #12] 48f4: 430a orrs r2, r1 48f6: 601a str r2, [r3, #0] 48f8: e018 b.n 492c } else { tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; 48fa: 887b ldrh r3, [r7, #2] 48fc: 3b04 subs r3, #4 48fe: b29b uxth r3, r3 4900: 085b lsrs r3, r3, #1 4902: b29b uxth r3, r3 4904: 461a mov r2, r3 4906: 68fb ldr r3, [r7, #12] 4908: 4413 add r3, r2 490a: 60fb str r3, [r7, #12] /* Reset the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); 490c: 68fb ldr r3, [r7, #12] 490e: 681a ldr r2, [r3, #0] 4910: 68fb ldr r3, [r7, #12] 4912: f422 42e0 bic.w r2, r2, #28672 ; 0x7000 4916: 601a str r2, [r3, #0] /* Configure the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); 4918: 68fb ldr r3, [r7, #12] 491a: 681a ldr r2, [r3, #0] 491c: 883b ldrh r3, [r7, #0] 491e: 021b lsls r3, r3, #8 4920: b29b uxth r3, r3 4922: 4619 mov r1, r3 4924: 68fb ldr r3, [r7, #12] 4926: 430a orrs r2, r1 4928: 601a str r2, [r3, #0] } } 492a: bf00 nop 492c: bf00 nop 492e: 3714 adds r7, #20 4930: 46bd mov sp, r7 4932: bc80 pop {r7} 4934: 4770 bx lr 00004936 : * @param NewState: new state of the TIMx UDIS bit * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) { 4936: b480 push {r7} 4938: b083 sub sp, #12 493a: af00 add r7, sp, #0 493c: 6078 str r0, [r7, #4] 493e: 460b mov r3, r1 4940: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 4942: 78fb ldrb r3, [r7, #3] 4944: 2b00 cmp r3, #0 4946: d008 beq.n 495a { /* Set the Update Disable Bit */ TIMx->CR1 |= TIM_CR1_UDIS; 4948: 687b ldr r3, [r7, #4] 494a: 881b ldrh r3, [r3, #0] 494c: b29b uxth r3, r3 494e: f043 0302 orr.w r3, r3, #2 4952: b29a uxth r2, r3 4954: 687b ldr r3, [r7, #4] 4956: 801a strh r2, [r3, #0] else { /* Reset the Update Disable Bit */ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); } } 4958: e007 b.n 496a TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); 495a: 687b ldr r3, [r7, #4] 495c: 881b ldrh r3, [r3, #0] 495e: b29b uxth r3, r3 4960: f023 0302 bic.w r3, r3, #2 4964: b29a uxth r2, r3 4966: 687b ldr r3, [r7, #4] 4968: 801a strh r2, [r3, #0] } 496a: bf00 nop 496c: 370c adds r7, #12 496e: 46bd mov sp, r7 4970: bc80 pop {r7} 4972: 4770 bx lr 00004974 : through the slave mode controller. * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. * @retval None */ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) { 4974: b480 push {r7} 4976: b083 sub sp, #12 4978: af00 add r7, sp, #0 497a: 6078 str r0, [r7, #4] 497c: 460b mov r3, r1 497e: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); if (TIM_UpdateSource != TIM_UpdateSource_Global) 4980: 887b ldrh r3, [r7, #2] 4982: 2b00 cmp r3, #0 4984: d008 beq.n 4998 { /* Set the URS Bit */ TIMx->CR1 |= TIM_CR1_URS; 4986: 687b ldr r3, [r7, #4] 4988: 881b ldrh r3, [r3, #0] 498a: b29b uxth r3, r3 498c: f043 0304 orr.w r3, r3, #4 4990: b29a uxth r2, r3 4992: 687b ldr r3, [r7, #4] 4994: 801a strh r2, [r3, #0] else { /* Reset the URS Bit */ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); } } 4996: e007 b.n 49a8 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); 4998: 687b ldr r3, [r7, #4] 499a: 881b ldrh r3, [r3, #0] 499c: b29b uxth r3, r3 499e: f023 0304 bic.w r3, r3, #4 49a2: b29a uxth r2, r3 49a4: 687b ldr r3, [r7, #4] 49a6: 801a strh r2, [r3, #0] } 49a8: bf00 nop 49aa: 370c adds r7, #12 49ac: 46bd mov sp, r7 49ae: bc80 pop {r7} 49b0: 4770 bx lr 000049b2 : * @param NewState: new state of the TIMx Hall sensor interface. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) { 49b2: b480 push {r7} 49b4: b083 sub sp, #12 49b6: af00 add r7, sp, #0 49b8: 6078 str r0, [r7, #4] 49ba: 460b mov r3, r1 49bc: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 49be: 78fb ldrb r3, [r7, #3] 49c0: 2b00 cmp r3, #0 49c2: d008 beq.n 49d6 { /* Set the TI1S Bit */ TIMx->CR2 |= TIM_CR2_TI1S; 49c4: 687b ldr r3, [r7, #4] 49c6: 889b ldrh r3, [r3, #4] 49c8: b29b uxth r3, r3 49ca: f043 0380 orr.w r3, r3, #128 ; 0x80 49ce: b29a uxth r2, r3 49d0: 687b ldr r3, [r7, #4] 49d2: 809a strh r2, [r3, #4] else { /* Reset the TI1S Bit */ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); } } 49d4: e007 b.n 49e6 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); 49d6: 687b ldr r3, [r7, #4] 49d8: 889b ldrh r3, [r3, #4] 49da: b29b uxth r3, r3 49dc: f023 0380 bic.w r3, r3, #128 ; 0x80 49e0: b29a uxth r2, r3 49e2: 687b ldr r3, [r7, #4] 49e4: 809a strh r2, [r3, #4] } 49e6: bf00 nop 49e8: 370c adds r7, #12 49ea: 46bd mov sp, r7 49ec: bc80 pop {r7} 49ee: 4770 bx lr 000049f0 : * @arg TIM_OPMode_Single * @arg TIM_OPMode_Repetitive * @retval None */ void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) { 49f0: b480 push {r7} 49f2: b083 sub sp, #12 49f4: af00 add r7, sp, #0 49f6: 6078 str r0, [r7, #4] 49f8: 460b mov r3, r1 49fa: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); /* Reset the OPM Bit */ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); 49fc: 687b ldr r3, [r7, #4] 49fe: 881b ldrh r3, [r3, #0] 4a00: b29b uxth r3, r3 4a02: f023 0308 bic.w r3, r3, #8 4a06: b29a uxth r2, r3 4a08: 687b ldr r3, [r7, #4] 4a0a: 801a strh r2, [r3, #0] /* Configure the OPM Mode */ TIMx->CR1 |= TIM_OPMode; 4a0c: 687b ldr r3, [r7, #4] 4a0e: 881b ldrh r3, [r3, #0] 4a10: b29a uxth r2, r3 4a12: 887b ldrh r3, [r7, #2] 4a14: 4313 orrs r3, r2 4a16: b29a uxth r2, r3 4a18: 687b ldr r3, [r7, #4] 4a1a: 801a strh r2, [r3, #0] } 4a1c: bf00 nop 4a1e: 370c adds r7, #12 4a20: 46bd mov sp, r7 4a22: bc80 pop {r7} 4a24: 4770 bx lr 00004a26 : * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). * * @retval None */ void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) { 4a26: b480 push {r7} 4a28: b083 sub sp, #12 4a2a: af00 add r7, sp, #0 4a2c: 6078 str r0, [r7, #4] 4a2e: 460b mov r3, r1 4a30: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST7_PERIPH(TIMx)); assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); /* Reset the MMS Bits */ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); 4a32: 687b ldr r3, [r7, #4] 4a34: 889b ldrh r3, [r3, #4] 4a36: b29b uxth r3, r3 4a38: f023 0370 bic.w r3, r3, #112 ; 0x70 4a3c: b29a uxth r2, r3 4a3e: 687b ldr r3, [r7, #4] 4a40: 809a strh r2, [r3, #4] /* Select the TRGO source */ TIMx->CR2 |= TIM_TRGOSource; 4a42: 687b ldr r3, [r7, #4] 4a44: 889b ldrh r3, [r3, #4] 4a46: b29a uxth r2, r3 4a48: 887b ldrh r3, [r7, #2] 4a4a: 4313 orrs r3, r2 4a4c: b29a uxth r2, r3 4a4e: 687b ldr r3, [r7, #4] 4a50: 809a strh r2, [r3, #4] } 4a52: bf00 nop 4a54: 370c adds r7, #12 4a56: 46bd mov sp, r7 4a58: bc80 pop {r7} 4a5a: 4770 bx lr 00004a5c : * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. * @retval None */ void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) { 4a5c: b480 push {r7} 4a5e: b083 sub sp, #12 4a60: af00 add r7, sp, #0 4a62: 6078 str r0, [r7, #4] 4a64: 460b mov r3, r1 4a66: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); /* Reset the SMS Bits */ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); 4a68: 687b ldr r3, [r7, #4] 4a6a: 891b ldrh r3, [r3, #8] 4a6c: b29b uxth r3, r3 4a6e: f023 0307 bic.w r3, r3, #7 4a72: b29a uxth r2, r3 4a74: 687b ldr r3, [r7, #4] 4a76: 811a strh r2, [r3, #8] /* Select the Slave Mode */ TIMx->SMCR |= TIM_SlaveMode; 4a78: 687b ldr r3, [r7, #4] 4a7a: 891b ldrh r3, [r3, #8] 4a7c: b29a uxth r2, r3 4a7e: 887b ldrh r3, [r7, #2] 4a80: 4313 orrs r3, r2 4a82: b29a uxth r2, r3 4a84: 687b ldr r3, [r7, #4] 4a86: 811a strh r2, [r3, #8] } 4a88: bf00 nop 4a8a: 370c adds r7, #12 4a8c: 46bd mov sp, r7 4a8e: bc80 pop {r7} 4a90: 4770 bx lr 00004a92 : * and its slaves (through TRGO). * @arg TIM_MasterSlaveMode_Disable: No action * @retval None */ void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) { 4a92: b480 push {r7} 4a94: b083 sub sp, #12 4a96: af00 add r7, sp, #0 4a98: 6078 str r0, [r7, #4] 4a9a: 460b mov r3, r1 4a9c: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); /* Reset the MSM Bit */ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); 4a9e: 687b ldr r3, [r7, #4] 4aa0: 891b ldrh r3, [r3, #8] 4aa2: b29b uxth r3, r3 4aa4: f023 0380 bic.w r3, r3, #128 ; 0x80 4aa8: b29a uxth r2, r3 4aaa: 687b ldr r3, [r7, #4] 4aac: 811a strh r2, [r3, #8] /* Set or Reset the MSM Bit */ TIMx->SMCR |= TIM_MasterSlaveMode; 4aae: 687b ldr r3, [r7, #4] 4ab0: 891b ldrh r3, [r3, #8] 4ab2: b29a uxth r2, r3 4ab4: 887b ldrh r3, [r7, #2] 4ab6: 4313 orrs r3, r2 4ab8: b29a uxth r2, r3 4aba: 687b ldr r3, [r7, #4] 4abc: 811a strh r2, [r3, #8] } 4abe: bf00 nop 4ac0: 370c adds r7, #12 4ac2: 46bd mov sp, r7 4ac4: bc80 pop {r7} 4ac6: 4770 bx lr 00004ac8 : * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. * @param Counter: specifies the Counter register new value. * @retval None */ void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) { 4ac8: b480 push {r7} 4aca: b083 sub sp, #12 4acc: af00 add r7, sp, #0 4ace: 6078 str r0, [r7, #4] 4ad0: 460b mov r3, r1 4ad2: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Set the Counter Register value */ TIMx->CNT = Counter; 4ad4: 687b ldr r3, [r7, #4] 4ad6: 887a ldrh r2, [r7, #2] 4ad8: 849a strh r2, [r3, #36] ; 0x24 } 4ada: bf00 nop 4adc: 370c adds r7, #12 4ade: 46bd mov sp, r7 4ae0: bc80 pop {r7} 4ae2: 4770 bx lr 00004ae4 : * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. * @param Autoreload: specifies the Autoreload register new value. * @retval None */ void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) { 4ae4: b480 push {r7} 4ae6: b083 sub sp, #12 4ae8: af00 add r7, sp, #0 4aea: 6078 str r0, [r7, #4] 4aec: 460b mov r3, r1 4aee: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Set the Autoreload Register value */ TIMx->ARR = Autoreload; 4af0: 687b ldr r3, [r7, #4] 4af2: 887a ldrh r2, [r7, #2] 4af4: 859a strh r2, [r3, #44] ; 0x2c } 4af6: bf00 nop 4af8: 370c adds r7, #12 4afa: 46bd mov sp, r7 4afc: bc80 pop {r7} 4afe: 4770 bx lr 00004b00 : * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. * @param Compare1: specifies the Capture Compare1 register new value. * @retval None */ void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) { 4b00: b480 push {r7} 4b02: b083 sub sp, #12 4b04: af00 add r7, sp, #0 4b06: 6078 str r0, [r7, #4] 4b08: 460b mov r3, r1 4b0a: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); /* Set the Capture Compare1 Register value */ TIMx->CCR1 = Compare1; 4b0c: 687b ldr r3, [r7, #4] 4b0e: 887a ldrh r2, [r7, #2] 4b10: 869a strh r2, [r3, #52] ; 0x34 } 4b12: bf00 nop 4b14: 370c adds r7, #12 4b16: 46bd mov sp, r7 4b18: bc80 pop {r7} 4b1a: 4770 bx lr 00004b1c : * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. * @param Compare2: specifies the Capture Compare2 register new value. * @retval None */ void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) { 4b1c: b480 push {r7} 4b1e: b083 sub sp, #12 4b20: af00 add r7, sp, #0 4b22: 6078 str r0, [r7, #4] 4b24: 460b mov r3, r1 4b26: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); /* Set the Capture Compare2 Register value */ TIMx->CCR2 = Compare2; 4b28: 687b ldr r3, [r7, #4] 4b2a: 887a ldrh r2, [r7, #2] 4b2c: 871a strh r2, [r3, #56] ; 0x38 } 4b2e: bf00 nop 4b30: 370c adds r7, #12 4b32: 46bd mov sp, r7 4b34: bc80 pop {r7} 4b36: 4770 bx lr 00004b38 : * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param Compare3: specifies the Capture Compare3 register new value. * @retval None */ void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) { 4b38: b480 push {r7} 4b3a: b083 sub sp, #12 4b3c: af00 add r7, sp, #0 4b3e: 6078 str r0, [r7, #4] 4b40: 460b mov r3, r1 4b42: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Set the Capture Compare3 Register value */ TIMx->CCR3 = Compare3; 4b44: 687b ldr r3, [r7, #4] 4b46: 887a ldrh r2, [r7, #2] 4b48: 879a strh r2, [r3, #60] ; 0x3c } 4b4a: bf00 nop 4b4c: 370c adds r7, #12 4b4e: 46bd mov sp, r7 4b50: bc80 pop {r7} 4b52: 4770 bx lr 00004b54 : * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param Compare4: specifies the Capture Compare4 register new value. * @retval None */ void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) { 4b54: b480 push {r7} 4b56: b083 sub sp, #12 4b58: af00 add r7, sp, #0 4b5a: 6078 str r0, [r7, #4] 4b5c: 460b mov r3, r1 4b5e: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Set the Capture Compare4 Register value */ TIMx->CCR4 = Compare4; 4b60: 687b ldr r3, [r7, #4] 4b62: 887a ldrh r2, [r7, #2] 4b64: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 } 4b68: bf00 nop 4b6a: 370c adds r7, #12 4b6c: 46bd mov sp, r7 4b6e: bc80 pop {r7} 4b70: 4770 bx lr 00004b72 : * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { 4b72: b480 push {r7} 4b74: b083 sub sp, #12 4b76: af00 add r7, sp, #0 4b78: 6078 str r0, [r7, #4] 4b7a: 460b mov r3, r1 4b7c: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC1PSC Bits */ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); 4b7e: 687b ldr r3, [r7, #4] 4b80: 8b1b ldrh r3, [r3, #24] 4b82: b29b uxth r3, r3 4b84: f023 030c bic.w r3, r3, #12 4b88: b29a uxth r2, r3 4b8a: 687b ldr r3, [r7, #4] 4b8c: 831a strh r2, [r3, #24] /* Set the IC1PSC value */ TIMx->CCMR1 |= TIM_ICPSC; 4b8e: 687b ldr r3, [r7, #4] 4b90: 8b1b ldrh r3, [r3, #24] 4b92: b29a uxth r2, r3 4b94: 887b ldrh r3, [r7, #2] 4b96: 4313 orrs r3, r2 4b98: b29a uxth r2, r3 4b9a: 687b ldr r3, [r7, #4] 4b9c: 831a strh r2, [r3, #24] } 4b9e: bf00 nop 4ba0: 370c adds r7, #12 4ba2: 46bd mov sp, r7 4ba4: bc80 pop {r7} 4ba6: 4770 bx lr 00004ba8 : * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { 4ba8: b480 push {r7} 4baa: b083 sub sp, #12 4bac: af00 add r7, sp, #0 4bae: 6078 str r0, [r7, #4] 4bb0: 460b mov r3, r1 4bb2: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC2PSC Bits */ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); 4bb4: 687b ldr r3, [r7, #4] 4bb6: 8b1b ldrh r3, [r3, #24] 4bb8: b29b uxth r3, r3 4bba: f423 6340 bic.w r3, r3, #3072 ; 0xc00 4bbe: b29a uxth r2, r3 4bc0: 687b ldr r3, [r7, #4] 4bc2: 831a strh r2, [r3, #24] /* Set the IC2PSC value */ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); 4bc4: 687b ldr r3, [r7, #4] 4bc6: 8b1b ldrh r3, [r3, #24] 4bc8: b29a uxth r2, r3 4bca: 887b ldrh r3, [r7, #2] 4bcc: 021b lsls r3, r3, #8 4bce: b29b uxth r3, r3 4bd0: 4313 orrs r3, r2 4bd2: b29a uxth r2, r3 4bd4: 687b ldr r3, [r7, #4] 4bd6: 831a strh r2, [r3, #24] } 4bd8: bf00 nop 4bda: 370c adds r7, #12 4bdc: 46bd mov sp, r7 4bde: bc80 pop {r7} 4be0: 4770 bx lr 00004be2 : * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { 4be2: b480 push {r7} 4be4: b083 sub sp, #12 4be6: af00 add r7, sp, #0 4be8: 6078 str r0, [r7, #4] 4bea: 460b mov r3, r1 4bec: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC3PSC Bits */ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); 4bee: 687b ldr r3, [r7, #4] 4bf0: 8b9b ldrh r3, [r3, #28] 4bf2: b29b uxth r3, r3 4bf4: f023 030c bic.w r3, r3, #12 4bf8: b29a uxth r2, r3 4bfa: 687b ldr r3, [r7, #4] 4bfc: 839a strh r2, [r3, #28] /* Set the IC3PSC value */ TIMx->CCMR2 |= TIM_ICPSC; 4bfe: 687b ldr r3, [r7, #4] 4c00: 8b9b ldrh r3, [r3, #28] 4c02: b29a uxth r2, r3 4c04: 887b ldrh r3, [r7, #2] 4c06: 4313 orrs r3, r2 4c08: b29a uxth r2, r3 4c0a: 687b ldr r3, [r7, #4] 4c0c: 839a strh r2, [r3, #28] } 4c0e: bf00 nop 4c10: 370c adds r7, #12 4c12: 46bd mov sp, r7 4c14: bc80 pop {r7} 4c16: 4770 bx lr 00004c18 : * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { 4c18: b480 push {r7} 4c1a: b083 sub sp, #12 4c1c: af00 add r7, sp, #0 4c1e: 6078 str r0, [r7, #4] 4c20: 460b mov r3, r1 4c22: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC4PSC Bits */ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); 4c24: 687b ldr r3, [r7, #4] 4c26: 8b9b ldrh r3, [r3, #28] 4c28: b29b uxth r3, r3 4c2a: f423 6340 bic.w r3, r3, #3072 ; 0xc00 4c2e: b29a uxth r2, r3 4c30: 687b ldr r3, [r7, #4] 4c32: 839a strh r2, [r3, #28] /* Set the IC4PSC value */ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); 4c34: 687b ldr r3, [r7, #4] 4c36: 8b9b ldrh r3, [r3, #28] 4c38: b29a uxth r2, r3 4c3a: 887b ldrh r3, [r7, #2] 4c3c: 021b lsls r3, r3, #8 4c3e: b29b uxth r3, r3 4c40: 4313 orrs r3, r2 4c42: b29a uxth r2, r3 4c44: 687b ldr r3, [r7, #4] 4c46: 839a strh r2, [r3, #28] } 4c48: bf00 nop 4c4a: 370c adds r7, #12 4c4c: 46bd mov sp, r7 4c4e: bc80 pop {r7} 4c50: 4770 bx lr 00004c52 : * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim * @retval None */ void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) { 4c52: b480 push {r7} 4c54: b083 sub sp, #12 4c56: af00 add r7, sp, #0 4c58: 6078 str r0, [r7, #4] 4c5a: 460b mov r3, r1 4c5c: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); assert_param(IS_TIM_CKD_DIV(TIM_CKD)); /* Reset the CKD Bits */ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); 4c5e: 687b ldr r3, [r7, #4] 4c60: 881b ldrh r3, [r3, #0] 4c62: b29b uxth r3, r3 4c64: f423 7340 bic.w r3, r3, #768 ; 0x300 4c68: b29a uxth r2, r3 4c6a: 687b ldr r3, [r7, #4] 4c6c: 801a strh r2, [r3, #0] /* Set the CKD value */ TIMx->CR1 |= TIM_CKD; 4c6e: 687b ldr r3, [r7, #4] 4c70: 881b ldrh r3, [r3, #0] 4c72: b29a uxth r2, r3 4c74: 887b ldrh r3, [r7, #2] 4c76: 4313 orrs r3, r2 4c78: b29a uxth r2, r3 4c7a: 687b ldr r3, [r7, #4] 4c7c: 801a strh r2, [r3, #0] } 4c7e: bf00 nop 4c80: 370c adds r7, #12 4c82: 46bd mov sp, r7 4c84: bc80 pop {r7} 4c86: 4770 bx lr 00004c88 : * @brief Gets the TIMx Input Capture 1 value. * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. * @retval Capture Compare 1 Register value. */ uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) { 4c88: b480 push {r7} 4c8a: b083 sub sp, #12 4c8c: af00 add r7, sp, #0 4c8e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_LIST8_PERIPH(TIMx)); /* Get the Capture 1 Register value */ return TIMx->CCR1; 4c90: 687b ldr r3, [r7, #4] 4c92: 8e9b ldrh r3, [r3, #52] ; 0x34 4c94: b29b uxth r3, r3 } 4c96: 4618 mov r0, r3 4c98: 370c adds r7, #12 4c9a: 46bd mov sp, r7 4c9c: bc80 pop {r7} 4c9e: 4770 bx lr 00004ca0 : * @brief Gets the TIMx Input Capture 2 value. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. * @retval Capture Compare 2 Register value. */ uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) { 4ca0: b480 push {r7} 4ca2: b083 sub sp, #12 4ca4: af00 add r7, sp, #0 4ca6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); /* Get the Capture 2 Register value */ return TIMx->CCR2; 4ca8: 687b ldr r3, [r7, #4] 4caa: 8f1b ldrh r3, [r3, #56] ; 0x38 4cac: b29b uxth r3, r3 } 4cae: 4618 mov r0, r3 4cb0: 370c adds r7, #12 4cb2: 46bd mov sp, r7 4cb4: bc80 pop {r7} 4cb6: 4770 bx lr 00004cb8 : * @brief Gets the TIMx Input Capture 3 value. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @retval Capture Compare 3 Register value. */ uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) { 4cb8: b480 push {r7} 4cba: b083 sub sp, #12 4cbc: af00 add r7, sp, #0 4cbe: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Get the Capture 3 Register value */ return TIMx->CCR3; 4cc0: 687b ldr r3, [r7, #4] 4cc2: 8f9b ldrh r3, [r3, #60] ; 0x3c 4cc4: b29b uxth r3, r3 } 4cc6: 4618 mov r0, r3 4cc8: 370c adds r7, #12 4cca: 46bd mov sp, r7 4ccc: bc80 pop {r7} 4cce: 4770 bx lr 00004cd0 : * @brief Gets the TIMx Input Capture 4 value. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @retval Capture Compare 4 Register value. */ uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) { 4cd0: b480 push {r7} 4cd2: b083 sub sp, #12 4cd4: af00 add r7, sp, #0 4cd6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Get the Capture 4 Register value */ return TIMx->CCR4; 4cd8: 687b ldr r3, [r7, #4] 4cda: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40 4cde: b29b uxth r3, r3 } 4ce0: 4618 mov r0, r3 4ce2: 370c adds r7, #12 4ce4: 46bd mov sp, r7 4ce6: bc80 pop {r7} 4ce8: 4770 bx lr 00004cea : * @brief Gets the TIMx Counter value. * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. * @retval Counter Register value. */ uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) { 4cea: b480 push {r7} 4cec: b083 sub sp, #12 4cee: af00 add r7, sp, #0 4cf0: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Get the Counter Register value */ return TIMx->CNT; 4cf2: 687b ldr r3, [r7, #4] 4cf4: 8c9b ldrh r3, [r3, #36] ; 0x24 4cf6: b29b uxth r3, r3 } 4cf8: 4618 mov r0, r3 4cfa: 370c adds r7, #12 4cfc: 46bd mov sp, r7 4cfe: bc80 pop {r7} 4d00: 4770 bx lr 00004d02 : * @brief Gets the TIMx Prescaler value. * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. * @retval Prescaler Register value. */ uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) { 4d02: b480 push {r7} 4d04: b083 sub sp, #12 4d06: af00 add r7, sp, #0 4d08: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Get the Prescaler Register value */ return TIMx->PSC; 4d0a: 687b ldr r3, [r7, #4] 4d0c: 8d1b ldrh r3, [r3, #40] ; 0x28 4d0e: b29b uxth r3, r3 } 4d10: 4618 mov r0, r3 4d12: 370c adds r7, #12 4d14: 46bd mov sp, r7 4d16: bc80 pop {r7} 4d18: 4770 bx lr 00004d1a : * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. * @retval The new state of TIM_FLAG (SET or RESET). */ FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) { 4d1a: b480 push {r7} 4d1c: b085 sub sp, #20 4d1e: af00 add r7, sp, #0 4d20: 6078 str r0, [r7, #4] 4d22: 460b mov r3, r1 4d24: 807b strh r3, [r7, #2] ITStatus bitstatus = RESET; 4d26: 2300 movs r3, #0 4d28: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) 4d2a: 687b ldr r3, [r7, #4] 4d2c: 8a1b ldrh r3, [r3, #16] 4d2e: b29a uxth r2, r3 4d30: 887b ldrh r3, [r7, #2] 4d32: 4013 ands r3, r2 4d34: b29b uxth r3, r3 4d36: 2b00 cmp r3, #0 4d38: d002 beq.n 4d40 { bitstatus = SET; 4d3a: 2301 movs r3, #1 4d3c: 73fb strb r3, [r7, #15] 4d3e: e001 b.n 4d44 } else { bitstatus = RESET; 4d40: 2300 movs r3, #0 4d42: 73fb strb r3, [r7, #15] } return bitstatus; 4d44: 7bfb ldrb r3, [r7, #15] } 4d46: 4618 mov r0, r3 4d48: 3714 adds r7, #20 4d4a: 46bd mov sp, r7 4d4c: bc80 pop {r7} 4d4e: 4770 bx lr 00004d50 : * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. * @retval None */ void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) { 4d50: b480 push {r7} 4d52: b083 sub sp, #12 4d54: af00 add r7, sp, #0 4d56: 6078 str r0, [r7, #4] 4d58: 460b mov r3, r1 4d5a: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); /* Clear the flags */ TIMx->SR = (uint16_t)~TIM_FLAG; 4d5c: 887b ldrh r3, [r7, #2] 4d5e: 43db mvns r3, r3 4d60: b29a uxth r2, r3 4d62: 687b ldr r3, [r7, #4] 4d64: 821a strh r2, [r3, #16] } 4d66: bf00 nop 4d68: 370c adds r7, #12 4d6a: 46bd mov sp, r7 4d6c: bc80 pop {r7} 4d6e: 4770 bx lr 00004d70 : * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. * @retval The new state of the TIM_IT(SET or RESET). */ ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) { 4d70: b480 push {r7} 4d72: b085 sub sp, #20 4d74: af00 add r7, sp, #0 4d76: 6078 str r0, [r7, #4] 4d78: 460b mov r3, r1 4d7a: 807b strh r3, [r7, #2] ITStatus bitstatus = RESET; 4d7c: 2300 movs r3, #0 4d7e: 73fb strb r3, [r7, #15] uint16_t itstatus = 0x0, itenable = 0x0; 4d80: 2300 movs r3, #0 4d82: 81bb strh r3, [r7, #12] 4d84: 2300 movs r3, #0 4d86: 817b strh r3, [r7, #10] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_GET_IT(TIM_IT)); itstatus = TIMx->SR & TIM_IT; 4d88: 687b ldr r3, [r7, #4] 4d8a: 8a1b ldrh r3, [r3, #16] 4d8c: b29a uxth r2, r3 4d8e: 887b ldrh r3, [r7, #2] 4d90: 4013 ands r3, r2 4d92: 81bb strh r3, [r7, #12] itenable = TIMx->DIER & TIM_IT; 4d94: 687b ldr r3, [r7, #4] 4d96: 899b ldrh r3, [r3, #12] 4d98: b29a uxth r2, r3 4d9a: 887b ldrh r3, [r7, #2] 4d9c: 4013 ands r3, r2 4d9e: 817b strh r3, [r7, #10] if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) 4da0: 89bb ldrh r3, [r7, #12] 4da2: 2b00 cmp r3, #0 4da4: d005 beq.n 4db2 4da6: 897b ldrh r3, [r7, #10] 4da8: 2b00 cmp r3, #0 4daa: d002 beq.n 4db2 { bitstatus = SET; 4dac: 2301 movs r3, #1 4dae: 73fb strb r3, [r7, #15] 4db0: e001 b.n 4db6 } else { bitstatus = RESET; 4db2: 2300 movs r3, #0 4db4: 73fb strb r3, [r7, #15] } return bitstatus; 4db6: 7bfb ldrb r3, [r7, #15] } 4db8: 4618 mov r0, r3 4dba: 3714 adds r7, #20 4dbc: 46bd mov sp, r7 4dbe: bc80 pop {r7} 4dc0: 4770 bx lr 00004dc2 : * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. * @retval None */ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) { 4dc2: b480 push {r7} 4dc4: b083 sub sp, #12 4dc6: af00 add r7, sp, #0 4dc8: 6078 str r0, [r7, #4] 4dca: 460b mov r3, r1 4dcc: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_IT(TIM_IT)); /* Clear the IT pending Bit */ TIMx->SR = (uint16_t)~TIM_IT; 4dce: 887b ldrh r3, [r7, #2] 4dd0: 43db mvns r3, r3 4dd2: b29a uxth r2, r3 4dd4: 687b ldr r3, [r7, #4] 4dd6: 821a strh r2, [r3, #16] } 4dd8: bf00 nop 4dda: 370c adds r7, #12 4ddc: 46bd mov sp, r7 4dde: bc80 pop {r7} 4de0: 4770 bx lr 00004de2 : * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { 4de2: b480 push {r7} 4de4: b087 sub sp, #28 4de6: af00 add r7, sp, #0 4de8: 60f8 str r0, [r7, #12] 4dea: 4608 mov r0, r1 4dec: 4611 mov r1, r2 4dee: 461a mov r2, r3 4df0: 4603 mov r3, r0 4df2: 817b strh r3, [r7, #10] 4df4: 460b mov r3, r1 4df6: 813b strh r3, [r7, #8] 4df8: 4613 mov r3, r2 4dfa: 80fb strh r3, [r7, #6] uint16_t tmpccmr1 = 0, tmpccer = 0; 4dfc: 2300 movs r3, #0 4dfe: 82bb strh r3, [r7, #20] 4e00: 2300 movs r3, #0 4e02: 82fb strh r3, [r7, #22] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); 4e04: 68fb ldr r3, [r7, #12] 4e06: 8c1b ldrh r3, [r3, #32] 4e08: b29b uxth r3, r3 4e0a: f023 0301 bic.w r3, r3, #1 4e0e: b29a uxth r2, r3 4e10: 68fb ldr r3, [r7, #12] 4e12: 841a strh r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 4e14: 68fb ldr r3, [r7, #12] 4e16: 8b1b ldrh r3, [r3, #24] 4e18: 82bb strh r3, [r7, #20] tmpccer = TIMx->CCER; 4e1a: 68fb ldr r3, [r7, #12] 4e1c: 8c1b ldrh r3, [r3, #32] 4e1e: 82fb strh r3, [r7, #22] /* Select the Input and set the filter */ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); 4e20: 8abb ldrh r3, [r7, #20] 4e22: f023 03f3 bic.w r3, r3, #243 ; 0xf3 4e26: 82bb strh r3, [r7, #20] tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); 4e28: 88fb ldrh r3, [r7, #6] 4e2a: 011b lsls r3, r3, #4 4e2c: b29a uxth r2, r3 4e2e: 893b ldrh r3, [r7, #8] 4e30: 4313 orrs r3, r2 4e32: b29a uxth r2, r3 4e34: 8abb ldrh r3, [r7, #20] 4e36: 4313 orrs r3, r2 4e38: 82bb strh r3, [r7, #20] if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 4e3a: 68fb ldr r3, [r7, #12] 4e3c: 4a1c ldr r2, [pc, #112] ; (4eb0 ) 4e3e: 4293 cmp r3, r2 4e40: d013 beq.n 4e6a 4e42: 68fb ldr r3, [r7, #12] 4e44: 4a1b ldr r2, [pc, #108] ; (4eb4 ) 4e46: 4293 cmp r3, r2 4e48: d00f beq.n 4e6a 4e4a: 68fb ldr r3, [r7, #12] 4e4c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 4e50: d00b beq.n 4e6a 4e52: 68fb ldr r3, [r7, #12] 4e54: 4a18 ldr r2, [pc, #96] ; (4eb8 ) 4e56: 4293 cmp r3, r2 4e58: d007 beq.n 4e6a 4e5a: 68fb ldr r3, [r7, #12] 4e5c: 4a17 ldr r2, [pc, #92] ; (4ebc ) 4e5e: 4293 cmp r3, r2 4e60: d003 beq.n 4e6a (TIMx == TIM4) ||(TIMx == TIM5)) 4e62: 68fb ldr r3, [r7, #12] 4e64: 4a16 ldr r2, [pc, #88] ; (4ec0 ) 4e66: 4293 cmp r3, r2 4e68: d10b bne.n 4e82 { /* Select the Polarity and set the CC1E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); 4e6a: 8afb ldrh r3, [r7, #22] 4e6c: f023 0302 bic.w r3, r3, #2 4e70: 82fb strh r3, [r7, #22] tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); 4e72: 897a ldrh r2, [r7, #10] 4e74: 8afb ldrh r3, [r7, #22] 4e76: 4313 orrs r3, r2 4e78: b29b uxth r3, r3 4e7a: f043 0301 orr.w r3, r3, #1 4e7e: 82fb strh r3, [r7, #22] 4e80: e00a b.n 4e98 } else { /* Select the Polarity and set the CC1E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); 4e82: 8afb ldrh r3, [r7, #22] 4e84: f023 030a bic.w r3, r3, #10 4e88: 82fb strh r3, [r7, #22] tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); 4e8a: 897a ldrh r2, [r7, #10] 4e8c: 8afb ldrh r3, [r7, #22] 4e8e: 4313 orrs r3, r2 4e90: b29b uxth r3, r3 4e92: f043 0301 orr.w r3, r3, #1 4e96: 82fb strh r3, [r7, #22] } /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 4e98: 68fb ldr r3, [r7, #12] 4e9a: 8aba ldrh r2, [r7, #20] 4e9c: 831a strh r2, [r3, #24] TIMx->CCER = tmpccer; 4e9e: 68fb ldr r3, [r7, #12] 4ea0: 8afa ldrh r2, [r7, #22] 4ea2: 841a strh r2, [r3, #32] } 4ea4: bf00 nop 4ea6: 371c adds r7, #28 4ea8: 46bd mov sp, r7 4eaa: bc80 pop {r7} 4eac: 4770 bx lr 4eae: bf00 nop 4eb0: 40012c00 .word 0x40012c00 4eb4: 40013400 .word 0x40013400 4eb8: 40000400 .word 0x40000400 4ebc: 40000800 .word 0x40000800 4ec0: 40000c00 .word 0x40000c00 00004ec4 : * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { 4ec4: b480 push {r7} 4ec6: b087 sub sp, #28 4ec8: af00 add r7, sp, #0 4eca: 60f8 str r0, [r7, #12] 4ecc: 4608 mov r0, r1 4ece: 4611 mov r1, r2 4ed0: 461a mov r2, r3 4ed2: 4603 mov r3, r0 4ed4: 817b strh r3, [r7, #10] 4ed6: 460b mov r3, r1 4ed8: 813b strh r3, [r7, #8] 4eda: 4613 mov r3, r2 4edc: 80fb strh r3, [r7, #6] uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; 4ede: 2300 movs r3, #0 4ee0: 82bb strh r3, [r7, #20] 4ee2: 2300 movs r3, #0 4ee4: 82fb strh r3, [r7, #22] 4ee6: 2300 movs r3, #0 4ee8: 827b strh r3, [r7, #18] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); 4eea: 68fb ldr r3, [r7, #12] 4eec: 8c1b ldrh r3, [r3, #32] 4eee: b29b uxth r3, r3 4ef0: f023 0310 bic.w r3, r3, #16 4ef4: b29a uxth r2, r3 4ef6: 68fb ldr r3, [r7, #12] 4ef8: 841a strh r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 4efa: 68fb ldr r3, [r7, #12] 4efc: 8b1b ldrh r3, [r3, #24] 4efe: 82bb strh r3, [r7, #20] tmpccer = TIMx->CCER; 4f00: 68fb ldr r3, [r7, #12] 4f02: 8c1b ldrh r3, [r3, #32] 4f04: 82fb strh r3, [r7, #22] tmp = (uint16_t)(TIM_ICPolarity << 4); 4f06: 897b ldrh r3, [r7, #10] 4f08: 011b lsls r3, r3, #4 4f0a: 827b strh r3, [r7, #18] /* Select the Input and set the filter */ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); 4f0c: 8abb ldrh r3, [r7, #20] 4f0e: f423 7340 bic.w r3, r3, #768 ; 0x300 4f12: 051b lsls r3, r3, #20 4f14: 0d1b lsrs r3, r3, #20 4f16: 82bb strh r3, [r7, #20] tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); 4f18: 88fb ldrh r3, [r7, #6] 4f1a: 031b lsls r3, r3, #12 4f1c: b29a uxth r2, r3 4f1e: 8abb ldrh r3, [r7, #20] 4f20: 4313 orrs r3, r2 4f22: 82bb strh r3, [r7, #20] tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); 4f24: 893b ldrh r3, [r7, #8] 4f26: 021b lsls r3, r3, #8 4f28: b29a uxth r2, r3 4f2a: 8abb ldrh r3, [r7, #20] 4f2c: 4313 orrs r3, r2 4f2e: 82bb strh r3, [r7, #20] if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 4f30: 68fb ldr r3, [r7, #12] 4f32: 4a1c ldr r2, [pc, #112] ; (4fa4 ) 4f34: 4293 cmp r3, r2 4f36: d013 beq.n 4f60 4f38: 68fb ldr r3, [r7, #12] 4f3a: 4a1b ldr r2, [pc, #108] ; (4fa8 ) 4f3c: 4293 cmp r3, r2 4f3e: d00f beq.n 4f60 4f40: 68fb ldr r3, [r7, #12] 4f42: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 4f46: d00b beq.n 4f60 4f48: 68fb ldr r3, [r7, #12] 4f4a: 4a18 ldr r2, [pc, #96] ; (4fac ) 4f4c: 4293 cmp r3, r2 4f4e: d007 beq.n 4f60 4f50: 68fb ldr r3, [r7, #12] 4f52: 4a17 ldr r2, [pc, #92] ; (4fb0 ) 4f54: 4293 cmp r3, r2 4f56: d003 beq.n 4f60 (TIMx == TIM4) ||(TIMx == TIM5)) 4f58: 68fb ldr r3, [r7, #12] 4f5a: 4a16 ldr r2, [pc, #88] ; (4fb4 ) 4f5c: 4293 cmp r3, r2 4f5e: d10b bne.n 4f78 { /* Select the Polarity and set the CC2E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); 4f60: 8afb ldrh r3, [r7, #22] 4f62: f023 0320 bic.w r3, r3, #32 4f66: 82fb strh r3, [r7, #22] tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); 4f68: 8a7a ldrh r2, [r7, #18] 4f6a: 8afb ldrh r3, [r7, #22] 4f6c: 4313 orrs r3, r2 4f6e: b29b uxth r3, r3 4f70: f043 0310 orr.w r3, r3, #16 4f74: 82fb strh r3, [r7, #22] 4f76: e00a b.n 4f8e } else { /* Select the Polarity and set the CC2E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); 4f78: 8afb ldrh r3, [r7, #22] 4f7a: f023 03a0 bic.w r3, r3, #160 ; 0xa0 4f7e: 82fb strh r3, [r7, #22] tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); 4f80: 897a ldrh r2, [r7, #10] 4f82: 8afb ldrh r3, [r7, #22] 4f84: 4313 orrs r3, r2 4f86: b29b uxth r3, r3 4f88: f043 0310 orr.w r3, r3, #16 4f8c: 82fb strh r3, [r7, #22] } /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 4f8e: 68fb ldr r3, [r7, #12] 4f90: 8aba ldrh r2, [r7, #20] 4f92: 831a strh r2, [r3, #24] TIMx->CCER = tmpccer; 4f94: 68fb ldr r3, [r7, #12] 4f96: 8afa ldrh r2, [r7, #22] 4f98: 841a strh r2, [r3, #32] } 4f9a: bf00 nop 4f9c: 371c adds r7, #28 4f9e: 46bd mov sp, r7 4fa0: bc80 pop {r7} 4fa2: 4770 bx lr 4fa4: 40012c00 .word 0x40012c00 4fa8: 40013400 .word 0x40013400 4fac: 40000400 .word 0x40000400 4fb0: 40000800 .word 0x40000800 4fb4: 40000c00 .word 0x40000c00 00004fb8 : * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { 4fb8: b480 push {r7} 4fba: b087 sub sp, #28 4fbc: af00 add r7, sp, #0 4fbe: 60f8 str r0, [r7, #12] 4fc0: 4608 mov r0, r1 4fc2: 4611 mov r1, r2 4fc4: 461a mov r2, r3 4fc6: 4603 mov r3, r0 4fc8: 817b strh r3, [r7, #10] 4fca: 460b mov r3, r1 4fcc: 813b strh r3, [r7, #8] 4fce: 4613 mov r3, r2 4fd0: 80fb strh r3, [r7, #6] uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 4fd2: 2300 movs r3, #0 4fd4: 82bb strh r3, [r7, #20] 4fd6: 2300 movs r3, #0 4fd8: 82fb strh r3, [r7, #22] 4fda: 2300 movs r3, #0 4fdc: 827b strh r3, [r7, #18] /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); 4fde: 68fb ldr r3, [r7, #12] 4fe0: 8c1b ldrh r3, [r3, #32] 4fe2: b29b uxth r3, r3 4fe4: f423 7380 bic.w r3, r3, #256 ; 0x100 4fe8: b29a uxth r2, r3 4fea: 68fb ldr r3, [r7, #12] 4fec: 841a strh r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 4fee: 68fb ldr r3, [r7, #12] 4ff0: 8b9b ldrh r3, [r3, #28] 4ff2: 82bb strh r3, [r7, #20] tmpccer = TIMx->CCER; 4ff4: 68fb ldr r3, [r7, #12] 4ff6: 8c1b ldrh r3, [r3, #32] 4ff8: 82fb strh r3, [r7, #22] tmp = (uint16_t)(TIM_ICPolarity << 8); 4ffa: 897b ldrh r3, [r7, #10] 4ffc: 021b lsls r3, r3, #8 4ffe: 827b strh r3, [r7, #18] /* Select the Input and set the filter */ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); 5000: 8abb ldrh r3, [r7, #20] 5002: f023 03f3 bic.w r3, r3, #243 ; 0xf3 5006: 82bb strh r3, [r7, #20] tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); 5008: 88fb ldrh r3, [r7, #6] 500a: 011b lsls r3, r3, #4 500c: b29a uxth r2, r3 500e: 893b ldrh r3, [r7, #8] 5010: 4313 orrs r3, r2 5012: b29a uxth r2, r3 5014: 8abb ldrh r3, [r7, #20] 5016: 4313 orrs r3, r2 5018: 82bb strh r3, [r7, #20] if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 501a: 68fb ldr r3, [r7, #12] 501c: 4a1c ldr r2, [pc, #112] ; (5090 ) 501e: 4293 cmp r3, r2 5020: d013 beq.n 504a 5022: 68fb ldr r3, [r7, #12] 5024: 4a1b ldr r2, [pc, #108] ; (5094 ) 5026: 4293 cmp r3, r2 5028: d00f beq.n 504a 502a: 68fb ldr r3, [r7, #12] 502c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 5030: d00b beq.n 504a 5032: 68fb ldr r3, [r7, #12] 5034: 4a18 ldr r2, [pc, #96] ; (5098 ) 5036: 4293 cmp r3, r2 5038: d007 beq.n 504a 503a: 68fb ldr r3, [r7, #12] 503c: 4a17 ldr r2, [pc, #92] ; (509c ) 503e: 4293 cmp r3, r2 5040: d003 beq.n 504a (TIMx == TIM4) ||(TIMx == TIM5)) 5042: 68fb ldr r3, [r7, #12] 5044: 4a16 ldr r2, [pc, #88] ; (50a0 ) 5046: 4293 cmp r3, r2 5048: d10b bne.n 5062 { /* Select the Polarity and set the CC3E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); 504a: 8afb ldrh r3, [r7, #22] 504c: f423 7300 bic.w r3, r3, #512 ; 0x200 5050: 82fb strh r3, [r7, #22] tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); 5052: 8a7a ldrh r2, [r7, #18] 5054: 8afb ldrh r3, [r7, #22] 5056: 4313 orrs r3, r2 5058: b29b uxth r3, r3 505a: f443 7380 orr.w r3, r3, #256 ; 0x100 505e: 82fb strh r3, [r7, #22] 5060: e00a b.n 5078 } else { /* Select the Polarity and set the CC3E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); 5062: 8afb ldrh r3, [r7, #22] 5064: f423 6320 bic.w r3, r3, #2560 ; 0xa00 5068: 82fb strh r3, [r7, #22] tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); 506a: 897a ldrh r2, [r7, #10] 506c: 8afb ldrh r3, [r7, #22] 506e: 4313 orrs r3, r2 5070: b29b uxth r3, r3 5072: f443 7380 orr.w r3, r3, #256 ; 0x100 5076: 82fb strh r3, [r7, #22] } /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 5078: 68fb ldr r3, [r7, #12] 507a: 8aba ldrh r2, [r7, #20] 507c: 839a strh r2, [r3, #28] TIMx->CCER = tmpccer; 507e: 68fb ldr r3, [r7, #12] 5080: 8afa ldrh r2, [r7, #22] 5082: 841a strh r2, [r3, #32] } 5084: bf00 nop 5086: 371c adds r7, #28 5088: 46bd mov sp, r7 508a: bc80 pop {r7} 508c: 4770 bx lr 508e: bf00 nop 5090: 40012c00 .word 0x40012c00 5094: 40013400 .word 0x40013400 5098: 40000400 .word 0x40000400 509c: 40000800 .word 0x40000800 50a0: 40000c00 .word 0x40000c00 000050a4 : * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { 50a4: b480 push {r7} 50a6: b087 sub sp, #28 50a8: af00 add r7, sp, #0 50aa: 60f8 str r0, [r7, #12] 50ac: 4608 mov r0, r1 50ae: 4611 mov r1, r2 50b0: 461a mov r2, r3 50b2: 4603 mov r3, r0 50b4: 817b strh r3, [r7, #10] 50b6: 460b mov r3, r1 50b8: 813b strh r3, [r7, #8] 50ba: 4613 mov r3, r2 50bc: 80fb strh r3, [r7, #6] uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 50be: 2300 movs r3, #0 50c0: 82bb strh r3, [r7, #20] 50c2: 2300 movs r3, #0 50c4: 82fb strh r3, [r7, #22] 50c6: 2300 movs r3, #0 50c8: 827b strh r3, [r7, #18] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); 50ca: 68fb ldr r3, [r7, #12] 50cc: 8c1b ldrh r3, [r3, #32] 50ce: b29b uxth r3, r3 50d0: f423 5380 bic.w r3, r3, #4096 ; 0x1000 50d4: b29a uxth r2, r3 50d6: 68fb ldr r3, [r7, #12] 50d8: 841a strh r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 50da: 68fb ldr r3, [r7, #12] 50dc: 8b9b ldrh r3, [r3, #28] 50de: 82bb strh r3, [r7, #20] tmpccer = TIMx->CCER; 50e0: 68fb ldr r3, [r7, #12] 50e2: 8c1b ldrh r3, [r3, #32] 50e4: 82fb strh r3, [r7, #22] tmp = (uint16_t)(TIM_ICPolarity << 12); 50e6: 897b ldrh r3, [r7, #10] 50e8: 031b lsls r3, r3, #12 50ea: 827b strh r3, [r7, #18] /* Select the Input and set the filter */ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); 50ec: 8abb ldrh r3, [r7, #20] 50ee: f423 7340 bic.w r3, r3, #768 ; 0x300 50f2: 051b lsls r3, r3, #20 50f4: 0d1b lsrs r3, r3, #20 50f6: 82bb strh r3, [r7, #20] tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); 50f8: 893b ldrh r3, [r7, #8] 50fa: 021b lsls r3, r3, #8 50fc: b29a uxth r2, r3 50fe: 8abb ldrh r3, [r7, #20] 5100: 4313 orrs r3, r2 5102: 82bb strh r3, [r7, #20] tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); 5104: 88fb ldrh r3, [r7, #6] 5106: 031b lsls r3, r3, #12 5108: b29a uxth r2, r3 510a: 8abb ldrh r3, [r7, #20] 510c: 4313 orrs r3, r2 510e: 82bb strh r3, [r7, #20] if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 5110: 68fb ldr r3, [r7, #12] 5112: 4a1d ldr r2, [pc, #116] ; (5188 ) 5114: 4293 cmp r3, r2 5116: d013 beq.n 5140 5118: 68fb ldr r3, [r7, #12] 511a: 4a1c ldr r2, [pc, #112] ; (518c ) 511c: 4293 cmp r3, r2 511e: d00f beq.n 5140 5120: 68fb ldr r3, [r7, #12] 5122: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 5126: d00b beq.n 5140 5128: 68fb ldr r3, [r7, #12] 512a: 4a19 ldr r2, [pc, #100] ; (5190 ) 512c: 4293 cmp r3, r2 512e: d007 beq.n 5140 5130: 68fb ldr r3, [r7, #12] 5132: 4a18 ldr r2, [pc, #96] ; (5194 ) 5134: 4293 cmp r3, r2 5136: d003 beq.n 5140 (TIMx == TIM4) ||(TIMx == TIM5)) 5138: 68fb ldr r3, [r7, #12] 513a: 4a17 ldr r2, [pc, #92] ; (5198 ) 513c: 4293 cmp r3, r2 513e: d10b bne.n 5158 { /* Select the Polarity and set the CC4E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); 5140: 8afb ldrh r3, [r7, #22] 5142: f423 5300 bic.w r3, r3, #8192 ; 0x2000 5146: 82fb strh r3, [r7, #22] tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); 5148: 8a7a ldrh r2, [r7, #18] 514a: 8afb ldrh r3, [r7, #22] 514c: 4313 orrs r3, r2 514e: b29b uxth r3, r3 5150: f443 5380 orr.w r3, r3, #4096 ; 0x1000 5154: 82fb strh r3, [r7, #22] 5156: e00c b.n 5172 } else { /* Select the Polarity and set the CC4E Bit */ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); 5158: 8afb ldrh r3, [r7, #22] 515a: f423 7300 bic.w r3, r3, #512 ; 0x200 515e: 045b lsls r3, r3, #17 5160: 0c5b lsrs r3, r3, #17 5162: 82fb strh r3, [r7, #22] tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); 5164: 897a ldrh r2, [r7, #10] 5166: 8afb ldrh r3, [r7, #22] 5168: 4313 orrs r3, r2 516a: b29b uxth r3, r3 516c: f443 5380 orr.w r3, r3, #4096 ; 0x1000 5170: 82fb strh r3, [r7, #22] } /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 5172: 68fb ldr r3, [r7, #12] 5174: 8aba ldrh r2, [r7, #20] 5176: 839a strh r2, [r3, #28] TIMx->CCER = tmpccer; 5178: 68fb ldr r3, [r7, #12] 517a: 8afa ldrh r2, [r7, #22] 517c: 841a strh r2, [r3, #32] } 517e: bf00 nop 5180: 371c adds r7, #28 5182: 46bd mov sp, r7 5184: bc80 pop {r7} 5186: 4770 bx lr 5188: 40012c00 .word 0x40012c00 518c: 40013400 .word 0x40013400 5190: 40000400 .word 0x40000400 5194: 40000800 .word 0x40000800 5198: 40000c00 .word 0x40000c00 0000519c : * @param NewState: new state of the specified RTC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) { 519c: b480 push {r7} 519e: b083 sub sp, #12 51a0: af00 add r7, sp, #0 51a2: 4603 mov r3, r0 51a4: 460a mov r2, r1 51a6: 80fb strh r3, [r7, #6] 51a8: 4613 mov r3, r2 51aa: 717b strb r3, [r7, #5] /* Check the parameters */ assert_param(IS_RTC_IT(RTC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 51ac: 797b ldrb r3, [r7, #5] 51ae: 2b00 cmp r3, #0 51b0: d008 beq.n 51c4 { RTC->CRH |= RTC_IT; 51b2: 4b0c ldr r3, [pc, #48] ; (51e4 ) 51b4: 881b ldrh r3, [r3, #0] 51b6: b29a uxth r2, r3 51b8: 490a ldr r1, [pc, #40] ; (51e4 ) 51ba: 88fb ldrh r3, [r7, #6] 51bc: 4313 orrs r3, r2 51be: b29b uxth r3, r3 51c0: 800b strh r3, [r1, #0] } else { RTC->CRH &= (uint16_t)~RTC_IT; } } 51c2: e009 b.n 51d8 RTC->CRH &= (uint16_t)~RTC_IT; 51c4: 4b07 ldr r3, [pc, #28] ; (51e4 ) 51c6: 881b ldrh r3, [r3, #0] 51c8: b29a uxth r2, r3 51ca: 88fb ldrh r3, [r7, #6] 51cc: 43db mvns r3, r3 51ce: b29b uxth r3, r3 51d0: 4904 ldr r1, [pc, #16] ; (51e4 ) 51d2: 4013 ands r3, r2 51d4: b29b uxth r3, r3 51d6: 800b strh r3, [r1, #0] } 51d8: bf00 nop 51da: 370c adds r7, #12 51dc: 46bd mov sp, r7 51de: bc80 pop {r7} 51e0: 4770 bx lr 51e2: bf00 nop 51e4: 40002800 .word 0x40002800 000051e8 : * @brief Enters the RTC configuration mode. * @param None * @retval None */ void RTC_EnterConfigMode(void) { 51e8: b480 push {r7} 51ea: af00 add r7, sp, #0 /* Set the CNF flag to enter in the Configuration Mode */ RTC->CRL |= RTC_CRL_CNF; 51ec: 4b05 ldr r3, [pc, #20] ; (5204 ) 51ee: 889b ldrh r3, [r3, #4] 51f0: b29b uxth r3, r3 51f2: 4a04 ldr r2, [pc, #16] ; (5204 ) 51f4: f043 0310 orr.w r3, r3, #16 51f8: b29b uxth r3, r3 51fa: 8093 strh r3, [r2, #4] } 51fc: bf00 nop 51fe: 46bd mov sp, r7 5200: bc80 pop {r7} 5202: 4770 bx lr 5204: 40002800 .word 0x40002800 00005208 : * @brief Exits from the RTC configuration mode. * @param None * @retval None */ void RTC_ExitConfigMode(void) { 5208: b480 push {r7} 520a: af00 add r7, sp, #0 /* Reset the CNF flag to exit from the Configuration Mode */ RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); 520c: 4b05 ldr r3, [pc, #20] ; (5224 ) 520e: 889b ldrh r3, [r3, #4] 5210: b29b uxth r3, r3 5212: 4a04 ldr r2, [pc, #16] ; (5224 ) 5214: f023 0310 bic.w r3, r3, #16 5218: b29b uxth r3, r3 521a: 8093 strh r3, [r2, #4] } 521c: bf00 nop 521e: 46bd mov sp, r7 5220: bc80 pop {r7} 5222: 4770 bx lr 5224: 40002800 .word 0x40002800 00005228 : * @brief Gets the RTC counter value. * @param None * @retval RTC counter value. */ uint32_t RTC_GetCounter(void) { 5228: b480 push {r7} 522a: b083 sub sp, #12 522c: af00 add r7, sp, #0 uint16_t tmp = 0; 522e: 2300 movs r3, #0 5230: 80fb strh r3, [r7, #6] tmp = RTC->CNTL; 5232: 4b07 ldr r3, [pc, #28] ; (5250 ) 5234: 8b9b ldrh r3, [r3, #28] 5236: 80fb strh r3, [r7, #6] return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; 5238: 4b05 ldr r3, [pc, #20] ; (5250 ) 523a: 8b1b ldrh r3, [r3, #24] 523c: b29b uxth r3, r3 523e: 041a lsls r2, r3, #16 5240: 88fb ldrh r3, [r7, #6] 5242: 4313 orrs r3, r2 } 5244: 4618 mov r0, r3 5246: 370c adds r7, #12 5248: 46bd mov sp, r7 524a: bc80 pop {r7} 524c: 4770 bx lr 524e: bf00 nop 5250: 40002800 .word 0x40002800 00005254 : * @brief Sets the RTC counter value. * @param CounterValue: RTC counter new value. * @retval None */ void RTC_SetCounter(uint32_t CounterValue) { 5254: b580 push {r7, lr} 5256: b082 sub sp, #8 5258: af00 add r7, sp, #0 525a: 6078 str r0, [r7, #4] RTC_EnterConfigMode(); 525c: f7ff ffc4 bl 51e8 /* Set RTC COUNTER MSB word */ RTC->CNTH = CounterValue >> 16; 5260: 687b ldr r3, [r7, #4] 5262: 0c1a lsrs r2, r3, #16 5264: 4b06 ldr r3, [pc, #24] ; (5280 ) 5266: b292 uxth r2, r2 5268: 831a strh r2, [r3, #24] /* Set RTC COUNTER LSB word */ RTC->CNTL = (CounterValue & RTC_LSB_MASK); 526a: 4b05 ldr r3, [pc, #20] ; (5280 ) 526c: 687a ldr r2, [r7, #4] 526e: b292 uxth r2, r2 5270: 839a strh r2, [r3, #28] RTC_ExitConfigMode(); 5272: f7ff ffc9 bl 5208 } 5276: bf00 nop 5278: 3708 adds r7, #8 527a: 46bd mov sp, r7 527c: bd80 pop {r7, pc} 527e: bf00 nop 5280: 40002800 .word 0x40002800 00005284 : * @brief Sets the RTC prescaler value. * @param PrescalerValue: RTC prescaler new value. * @retval None */ void RTC_SetPrescaler(uint32_t PrescalerValue) { 5284: b580 push {r7, lr} 5286: b082 sub sp, #8 5288: af00 add r7, sp, #0 528a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_RTC_PRESCALER(PrescalerValue)); RTC_EnterConfigMode(); 528c: f7ff ffac bl 51e8 /* Set RTC PRESCALER MSB word */ RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; 5290: 687b ldr r3, [r7, #4] 5292: 0c1b lsrs r3, r3, #16 5294: b29b uxth r3, r3 5296: 4a07 ldr r2, [pc, #28] ; (52b4 ) 5298: f003 030f and.w r3, r3, #15 529c: b29b uxth r3, r3 529e: 8113 strh r3, [r2, #8] /* Set RTC PRESCALER LSB word */ RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); 52a0: 4b04 ldr r3, [pc, #16] ; (52b4 ) 52a2: 687a ldr r2, [r7, #4] 52a4: b292 uxth r2, r2 52a6: 819a strh r2, [r3, #12] RTC_ExitConfigMode(); 52a8: f7ff ffae bl 5208 } 52ac: bf00 nop 52ae: 3708 adds r7, #8 52b0: 46bd mov sp, r7 52b2: bd80 pop {r7, pc} 52b4: 40002800 .word 0x40002800 000052b8 : * @brief Sets the RTC alarm value. * @param AlarmValue: RTC alarm new value. * @retval None */ void RTC_SetAlarm(uint32_t AlarmValue) { 52b8: b580 push {r7, lr} 52ba: b082 sub sp, #8 52bc: af00 add r7, sp, #0 52be: 6078 str r0, [r7, #4] RTC_EnterConfigMode(); 52c0: f7ff ff92 bl 51e8 /* Set the ALARM MSB word */ RTC->ALRH = AlarmValue >> 16; 52c4: 687b ldr r3, [r7, #4] 52c6: 0c1a lsrs r2, r3, #16 52c8: 4b06 ldr r3, [pc, #24] ; (52e4 ) 52ca: b292 uxth r2, r2 52cc: 841a strh r2, [r3, #32] /* Set the ALARM LSB word */ RTC->ALRL = (AlarmValue & RTC_LSB_MASK); 52ce: 4b05 ldr r3, [pc, #20] ; (52e4 ) 52d0: 687a ldr r2, [r7, #4] 52d2: b292 uxth r2, r2 52d4: 849a strh r2, [r3, #36] ; 0x24 RTC_ExitConfigMode(); 52d6: f7ff ff97 bl 5208 } 52da: bf00 nop 52dc: 3708 adds r7, #8 52de: 46bd mov sp, r7 52e0: bd80 pop {r7, pc} 52e2: bf00 nop 52e4: 40002800 .word 0x40002800 000052e8 : * @brief Gets the RTC divider value. * @param None * @retval RTC Divider value. */ uint32_t RTC_GetDivider(void) { 52e8: b480 push {r7} 52ea: b083 sub sp, #12 52ec: af00 add r7, sp, #0 uint32_t tmp = 0x00; 52ee: 2300 movs r3, #0 52f0: 607b str r3, [r7, #4] tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; 52f2: 4b0a ldr r3, [pc, #40] ; (531c ) 52f4: 8a1b ldrh r3, [r3, #16] 52f6: b29b uxth r3, r3 52f8: 041b lsls r3, r3, #16 52fa: f403 2370 and.w r3, r3, #983040 ; 0xf0000 52fe: 607b str r3, [r7, #4] tmp |= RTC->DIVL; 5300: 4b06 ldr r3, [pc, #24] ; (531c ) 5302: 8a9b ldrh r3, [r3, #20] 5304: b29b uxth r3, r3 5306: 461a mov r2, r3 5308: 687b ldr r3, [r7, #4] 530a: 4313 orrs r3, r2 530c: 607b str r3, [r7, #4] return tmp; 530e: 687b ldr r3, [r7, #4] } 5310: 4618 mov r0, r3 5312: 370c adds r7, #12 5314: 46bd mov sp, r7 5316: bc80 pop {r7} 5318: 4770 bx lr 531a: bf00 nop 531c: 40002800 .word 0x40002800 00005320 : * @note This function must be called before any write to RTC registers. * @param None * @retval None */ void RTC_WaitForLastTask(void) { 5320: b480 push {r7} 5322: af00 add r7, sp, #0 /* Loop until RTOFF flag is set */ while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) 5324: bf00 nop 5326: 4b06 ldr r3, [pc, #24] ; (5340 ) 5328: 889b ldrh r3, [r3, #4] 532a: b29b uxth r3, r3 532c: f003 0320 and.w r3, r3, #32 5330: 2b00 cmp r3, #0 5332: d0f8 beq.n 5326 { } } 5334: bf00 nop 5336: bf00 nop 5338: 46bd mov sp, r7 533a: bc80 pop {r7} 533c: 4770 bx lr 533e: bf00 nop 5340: 40002800 .word 0x40002800 00005344 : * or an APB clock stop. * @param None * @retval None */ void RTC_WaitForSynchro(void) { 5344: b480 push {r7} 5346: af00 add r7, sp, #0 /* Clear RSF flag */ RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; 5348: 4b0a ldr r3, [pc, #40] ; (5374 ) 534a: 889b ldrh r3, [r3, #4] 534c: b29b uxth r3, r3 534e: 4a09 ldr r2, [pc, #36] ; (5374 ) 5350: f023 0308 bic.w r3, r3, #8 5354: b29b uxth r3, r3 5356: 8093 strh r3, [r2, #4] /* Loop until RSF flag is set */ while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) 5358: bf00 nop 535a: 4b06 ldr r3, [pc, #24] ; (5374 ) 535c: 889b ldrh r3, [r3, #4] 535e: b29b uxth r3, r3 5360: f003 0308 and.w r3, r3, #8 5364: 2b00 cmp r3, #0 5366: d0f8 beq.n 535a { } } 5368: bf00 nop 536a: bf00 nop 536c: 46bd mov sp, r7 536e: bc80 pop {r7} 5370: 4770 bx lr 5372: bf00 nop 5374: 40002800 .word 0x40002800 00005378 : * @arg RTC_FLAG_ALR: Alarm flag * @arg RTC_FLAG_SEC: Second flag * @retval The new state of RTC_FLAG (SET or RESET). */ FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) { 5378: b480 push {r7} 537a: b085 sub sp, #20 537c: af00 add r7, sp, #0 537e: 4603 mov r3, r0 5380: 80fb strh r3, [r7, #6] FlagStatus bitstatus = RESET; 5382: 2300 movs r3, #0 5384: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) 5386: 4b09 ldr r3, [pc, #36] ; (53ac ) 5388: 889b ldrh r3, [r3, #4] 538a: b29a uxth r2, r3 538c: 88fb ldrh r3, [r7, #6] 538e: 4013 ands r3, r2 5390: b29b uxth r3, r3 5392: 2b00 cmp r3, #0 5394: d002 beq.n 539c { bitstatus = SET; 5396: 2301 movs r3, #1 5398: 73fb strb r3, [r7, #15] 539a: e001 b.n 53a0 } else { bitstatus = RESET; 539c: 2300 movs r3, #0 539e: 73fb strb r3, [r7, #15] } return bitstatus; 53a0: 7bfb ldrb r3, [r7, #15] } 53a2: 4618 mov r0, r3 53a4: 3714 adds r7, #20 53a6: 46bd mov sp, r7 53a8: bc80 pop {r7} 53aa: 4770 bx lr 53ac: 40002800 .word 0x40002800 000053b0 : * @arg RTC_FLAG_ALR: Alarm flag * @arg RTC_FLAG_SEC: Second flag * @retval None */ void RTC_ClearFlag(uint16_t RTC_FLAG) { 53b0: b480 push {r7} 53b2: b083 sub sp, #12 53b4: af00 add r7, sp, #0 53b6: 4603 mov r3, r0 53b8: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); /* Clear the corresponding RTC flag */ RTC->CRL &= (uint16_t)~RTC_FLAG; 53ba: 4b07 ldr r3, [pc, #28] ; (53d8 ) 53bc: 889b ldrh r3, [r3, #4] 53be: b29a uxth r2, r3 53c0: 88fb ldrh r3, [r7, #6] 53c2: 43db mvns r3, r3 53c4: b29b uxth r3, r3 53c6: 4904 ldr r1, [pc, #16] ; (53d8 ) 53c8: 4013 ands r3, r2 53ca: b29b uxth r3, r3 53cc: 808b strh r3, [r1, #4] } 53ce: bf00 nop 53d0: 370c adds r7, #12 53d2: 46bd mov sp, r7 53d4: bc80 pop {r7} 53d6: 4770 bx lr 53d8: 40002800 .word 0x40002800 000053dc : * @arg RTC_IT_ALR: Alarm interrupt * @arg RTC_IT_SEC: Second interrupt * @retval The new state of the RTC_IT (SET or RESET). */ ITStatus RTC_GetITStatus(uint16_t RTC_IT) { 53dc: b480 push {r7} 53de: b085 sub sp, #20 53e0: af00 add r7, sp, #0 53e2: 4603 mov r3, r0 53e4: 80fb strh r3, [r7, #6] ITStatus bitstatus = RESET; 53e6: 2300 movs r3, #0 53e8: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_RTC_GET_IT(RTC_IT)); bitstatus = (ITStatus)(RTC->CRL & RTC_IT); 53ea: 4b0f ldr r3, [pc, #60] ; (5428 ) 53ec: 889b ldrh r3, [r3, #4] 53ee: b29b uxth r3, r3 53f0: b2da uxtb r2, r3 53f2: 88fb ldrh r3, [r7, #6] 53f4: b2db uxtb r3, r3 53f6: 4013 ands r3, r2 53f8: 73fb strb r3, [r7, #15] if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) 53fa: 4b0b ldr r3, [pc, #44] ; (5428 ) 53fc: 881b ldrh r3, [r3, #0] 53fe: b29a uxth r2, r3 5400: 88fb ldrh r3, [r7, #6] 5402: 4013 ands r3, r2 5404: b29b uxth r3, r3 5406: 2b00 cmp r3, #0 5408: d005 beq.n 5416 540a: 7bfb ldrb r3, [r7, #15] 540c: 2b00 cmp r3, #0 540e: d002 beq.n 5416 { bitstatus = SET; 5410: 2301 movs r3, #1 5412: 73fb strb r3, [r7, #15] 5414: e001 b.n 541a } else { bitstatus = RESET; 5416: 2300 movs r3, #0 5418: 73fb strb r3, [r7, #15] } return bitstatus; 541a: 7bfb ldrb r3, [r7, #15] } 541c: 4618 mov r0, r3 541e: 3714 adds r7, #20 5420: 46bd mov sp, r7 5422: bc80 pop {r7} 5424: 4770 bx lr 5426: bf00 nop 5428: 40002800 .word 0x40002800 0000542c : * @arg RTC_IT_ALR: Alarm interrupt * @arg RTC_IT_SEC: Second interrupt * @retval None */ void RTC_ClearITPendingBit(uint16_t RTC_IT) { 542c: b480 push {r7} 542e: b083 sub sp, #12 5430: af00 add r7, sp, #0 5432: 4603 mov r3, r0 5434: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_RTC_IT(RTC_IT)); /* Clear the corresponding RTC pending bit */ RTC->CRL &= (uint16_t)~RTC_IT; 5436: 4b07 ldr r3, [pc, #28] ; (5454 ) 5438: 889b ldrh r3, [r3, #4] 543a: b29a uxth r2, r3 543c: 88fb ldrh r3, [r7, #6] 543e: 43db mvns r3, r3 5440: b29b uxth r3, r3 5442: 4904 ldr r1, [pc, #16] ; (5454 ) 5444: 4013 ands r3, r2 5446: b29b uxth r3, r3 5448: 808b strh r3, [r1, #4] } 544a: bf00 nop 544c: 370c adds r7, #12 544e: 46bd mov sp, r7 5450: bc80 pop {r7} 5452: 4770 bx lr 5454: 40002800 .word 0x40002800 00005458 : * @brief Deinitializes the DAC peripheral registers to their default reset values. * @param None * @retval None */ void DAC_DeInit(void) { 5458: b580 push {r7, lr} 545a: af00 add r7, sp, #0 /* Enable DAC reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); 545c: 2101 movs r1, #1 545e: f04f 5000 mov.w r0, #536870912 ; 0x20000000 5462: f7fc f9ab bl 17bc /* Release DAC from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); 5466: 2100 movs r1, #0 5468: f04f 5000 mov.w r0, #536870912 ; 0x20000000 546c: f7fc f9a6 bl 17bc } 5470: bf00 nop 5472: bd80 pop {r7, pc} 00005474 : * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that * contains the configuration information for the specified DAC channel. * @retval None */ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) { 5474: b480 push {r7} 5476: b085 sub sp, #20 5478: af00 add r7, sp, #0 547a: 6078 str r0, [r7, #4] 547c: 6039 str r1, [r7, #0] uint32_t tmpreg1 = 0, tmpreg2 = 0; 547e: 2300 movs r3, #0 5480: 60fb str r3, [r7, #12] 5482: 2300 movs r3, #0 5484: 60bb str r3, [r7, #8] assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); /*---------------------------- DAC CR Configuration --------------------------*/ /* Get the DAC CR value */ tmpreg1 = DAC->CR; 5486: 4b13 ldr r3, [pc, #76] ; (54d4 ) 5488: 681b ldr r3, [r3, #0] 548a: 60fb str r3, [r7, #12] /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); 548c: f640 72fe movw r2, #4094 ; 0xffe 5490: 687b ldr r3, [r7, #4] 5492: fa02 f303 lsl.w r3, r2, r3 5496: 43db mvns r3, r3 5498: 68fa ldr r2, [r7, #12] 549a: 4013 ands r3, r2 549c: 60fb str r3, [r7, #12] mask/amplitude for wave generation */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set WAVEx bits according to DAC_WaveGeneration value */ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | 549e: 683b ldr r3, [r7, #0] 54a0: 681a ldr r2, [r3, #0] 54a2: 683b ldr r3, [r7, #0] 54a4: 685b ldr r3, [r3, #4] 54a6: 431a orrs r2, r3 DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); 54a8: 683b ldr r3, [r7, #0] 54aa: 689b ldr r3, [r3, #8] tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | 54ac: 431a orrs r2, r3 DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); 54ae: 683b ldr r3, [r7, #0] 54b0: 68db ldr r3, [r3, #12] tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | 54b2: 4313 orrs r3, r2 54b4: 60bb str r3, [r7, #8] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << DAC_Channel; 54b6: 68ba ldr r2, [r7, #8] 54b8: 687b ldr r3, [r7, #4] 54ba: fa02 f303 lsl.w r3, r2, r3 54be: 68fa ldr r2, [r7, #12] 54c0: 4313 orrs r3, r2 54c2: 60fb str r3, [r7, #12] /* Write to DAC CR */ DAC->CR = tmpreg1; 54c4: 4a03 ldr r2, [pc, #12] ; (54d4 ) 54c6: 68fb ldr r3, [r7, #12] 54c8: 6013 str r3, [r2, #0] } 54ca: bf00 nop 54cc: 3714 adds r7, #20 54ce: 46bd mov sp, r7 54d0: bc80 pop {r7} 54d2: 4770 bx lr 54d4: 40007400 .word 0x40007400 000054d8 : * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will * be initialized. * @retval None */ void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) { 54d8: b480 push {r7} 54da: b083 sub sp, #12 54dc: af00 add r7, sp, #0 54de: 6078 str r0, [r7, #4] /*--------------- Reset DAC init structure parameters values -----------------*/ /* Initialize the DAC_Trigger member */ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; 54e0: 687b ldr r3, [r7, #4] 54e2: 2200 movs r2, #0 54e4: 601a str r2, [r3, #0] /* Initialize the DAC_WaveGeneration member */ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; 54e6: 687b ldr r3, [r7, #4] 54e8: 2200 movs r2, #0 54ea: 605a str r2, [r3, #4] /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; 54ec: 687b ldr r3, [r7, #4] 54ee: 2200 movs r2, #0 54f0: 609a str r2, [r3, #8] /* Initialize the DAC_OutputBuffer member */ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; 54f2: 687b ldr r3, [r7, #4] 54f4: 2200 movs r2, #0 54f6: 60da str r2, [r3, #12] } 54f8: bf00 nop 54fa: 370c adds r7, #12 54fc: 46bd mov sp, r7 54fe: bc80 pop {r7} 5500: 4770 bx lr 00005502 : * @param NewState: new state of the DAC channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) { 5502: b480 push {r7} 5504: b083 sub sp, #12 5506: af00 add r7, sp, #0 5508: 6078 str r0, [r7, #4] 550a: 460b mov r3, r1 550c: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 550e: 78fb ldrb r3, [r7, #3] 5510: 2b00 cmp r3, #0 5512: d009 beq.n 5528 { /* Enable the selected DAC channel */ DAC->CR |= (DAC_CR_EN1 << DAC_Channel); 5514: 4b0c ldr r3, [pc, #48] ; (5548 ) 5516: 681a ldr r2, [r3, #0] 5518: 2101 movs r1, #1 551a: 687b ldr r3, [r7, #4] 551c: fa01 f303 lsl.w r3, r1, r3 5520: 4909 ldr r1, [pc, #36] ; (5548 ) 5522: 4313 orrs r3, r2 5524: 600b str r3, [r1, #0] else { /* Disable the selected DAC channel */ DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); } } 5526: e009 b.n 553c DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); 5528: 4b07 ldr r3, [pc, #28] ; (5548 ) 552a: 681a ldr r2, [r3, #0] 552c: 2101 movs r1, #1 552e: 687b ldr r3, [r7, #4] 5530: fa01 f303 lsl.w r3, r1, r3 5534: 43db mvns r3, r3 5536: 4904 ldr r1, [pc, #16] ; (5548 ) 5538: 4013 ands r3, r2 553a: 600b str r3, [r1, #0] } 553c: bf00 nop 553e: 370c adds r7, #12 5540: 46bd mov sp, r7 5542: bc80 pop {r7} 5544: 4770 bx lr 5546: bf00 nop 5548: 40007400 .word 0x40007400 0000554c : * @param NewState: new state of the selected DAC channel DMA request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) { 554c: b480 push {r7} 554e: b083 sub sp, #12 5550: af00 add r7, sp, #0 5552: 6078 str r0, [r7, #4] 5554: 460b mov r3, r1 5556: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 5558: 78fb ldrb r3, [r7, #3] 555a: 2b00 cmp r3, #0 555c: d00a beq.n 5574 { /* Enable the selected DAC channel DMA request */ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); 555e: 4b0d ldr r3, [pc, #52] ; (5594 ) 5560: 681a ldr r2, [r3, #0] 5562: f44f 5180 mov.w r1, #4096 ; 0x1000 5566: 687b ldr r3, [r7, #4] 5568: fa01 f303 lsl.w r3, r1, r3 556c: 4909 ldr r1, [pc, #36] ; (5594 ) 556e: 4313 orrs r3, r2 5570: 600b str r3, [r1, #0] else { /* Disable the selected DAC channel DMA request */ DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); } } 5572: e00a b.n 558a DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); 5574: 4b07 ldr r3, [pc, #28] ; (5594 ) 5576: 681a ldr r2, [r3, #0] 5578: f44f 5180 mov.w r1, #4096 ; 0x1000 557c: 687b ldr r3, [r7, #4] 557e: fa01 f303 lsl.w r3, r1, r3 5582: 43db mvns r3, r3 5584: 4903 ldr r1, [pc, #12] ; (5594 ) 5586: 4013 ands r3, r2 5588: 600b str r3, [r1, #0] } 558a: bf00 nop 558c: 370c adds r7, #12 558e: 46bd mov sp, r7 5590: bc80 pop {r7} 5592: 4770 bx lr 5594: 40007400 .word 0x40007400 00005598 : * @param NewState: new state of the selected DAC channel software trigger. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) { 5598: b480 push {r7} 559a: b083 sub sp, #12 559c: af00 add r7, sp, #0 559e: 6078 str r0, [r7, #4] 55a0: 460b mov r3, r1 55a2: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 55a4: 78fb ldrb r3, [r7, #3] 55a6: 2b00 cmp r3, #0 55a8: d00a beq.n 55c0 { /* Enable software trigger for the selected DAC channel */ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); 55aa: 4b0d ldr r3, [pc, #52] ; (55e0 ) 55ac: 685a ldr r2, [r3, #4] 55ae: 687b ldr r3, [r7, #4] 55b0: 091b lsrs r3, r3, #4 55b2: 2101 movs r1, #1 55b4: fa01 f303 lsl.w r3, r1, r3 55b8: 4909 ldr r1, [pc, #36] ; (55e0 ) 55ba: 4313 orrs r3, r2 55bc: 604b str r3, [r1, #4] else { /* Disable software trigger for the selected DAC channel */ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); } } 55be: e00a b.n 55d6 DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); 55c0: 4b07 ldr r3, [pc, #28] ; (55e0 ) 55c2: 685a ldr r2, [r3, #4] 55c4: 687b ldr r3, [r7, #4] 55c6: 091b lsrs r3, r3, #4 55c8: 2101 movs r1, #1 55ca: fa01 f303 lsl.w r3, r1, r3 55ce: 43db mvns r3, r3 55d0: 4903 ldr r1, [pc, #12] ; (55e0 ) 55d2: 4013 ands r3, r2 55d4: 604b str r3, [r1, #4] } 55d6: bf00 nop 55d8: 370c adds r7, #12 55da: 46bd mov sp, r7 55dc: bc80 pop {r7} 55de: 4770 bx lr 55e0: 40007400 .word 0x40007400 000055e4 : * @param NewState: new state of the DAC channels software triggers. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) { 55e4: b480 push {r7} 55e6: b083 sub sp, #12 55e8: af00 add r7, sp, #0 55ea: 4603 mov r3, r0 55ec: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 55ee: 79fb ldrb r3, [r7, #7] 55f0: 2b00 cmp r3, #0 55f2: d006 beq.n 5602 { /* Enable software trigger for both DAC channels */ DAC->SWTRIGR |= DUAL_SWTRIG_SET ; 55f4: 4b08 ldr r3, [pc, #32] ; (5618 ) 55f6: 685b ldr r3, [r3, #4] 55f8: 4a07 ldr r2, [pc, #28] ; (5618 ) 55fa: f043 0303 orr.w r3, r3, #3 55fe: 6053 str r3, [r2, #4] else { /* Disable software trigger for both DAC channels */ DAC->SWTRIGR &= DUAL_SWTRIG_RESET; } } 5600: e005 b.n 560e DAC->SWTRIGR &= DUAL_SWTRIG_RESET; 5602: 4b05 ldr r3, [pc, #20] ; (5618 ) 5604: 685b ldr r3, [r3, #4] 5606: 4a04 ldr r2, [pc, #16] ; (5618 ) 5608: f023 0303 bic.w r3, r3, #3 560c: 6053 str r3, [r2, #4] } 560e: bf00 nop 5610: 370c adds r7, #12 5612: 46bd mov sp, r7 5614: bc80 pop {r7} 5616: 4770 bx lr 5618: 40007400 .word 0x40007400 0000561c : * @param NewState: new state of the selected DAC channel wave generation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) { 561c: b480 push {r7} 561e: b085 sub sp, #20 5620: af00 add r7, sp, #0 5622: 60f8 str r0, [r7, #12] 5624: 60b9 str r1, [r7, #8] 5626: 4613 mov r3, r2 5628: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_WAVE(DAC_Wave)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 562a: 79fb ldrb r3, [r7, #7] 562c: 2b00 cmp r3, #0 562e: d009 beq.n 5644 { /* Enable the selected wave generation for the selected DAC channel */ DAC->CR |= DAC_Wave << DAC_Channel; 5630: 4b0c ldr r3, [pc, #48] ; (5664 ) 5632: 681a ldr r2, [r3, #0] 5634: 68b9 ldr r1, [r7, #8] 5636: 68fb ldr r3, [r7, #12] 5638: fa01 f303 lsl.w r3, r1, r3 563c: 4909 ldr r1, [pc, #36] ; (5664 ) 563e: 4313 orrs r3, r2 5640: 600b str r3, [r1, #0] else { /* Disable the selected wave generation for the selected DAC channel */ DAC->CR &= ~(DAC_Wave << DAC_Channel); } } 5642: e009 b.n 5658 DAC->CR &= ~(DAC_Wave << DAC_Channel); 5644: 4b07 ldr r3, [pc, #28] ; (5664 ) 5646: 681a ldr r2, [r3, #0] 5648: 68b9 ldr r1, [r7, #8] 564a: 68fb ldr r3, [r7, #12] 564c: fa01 f303 lsl.w r3, r1, r3 5650: 43db mvns r3, r3 5652: 4904 ldr r1, [pc, #16] ; (5664 ) 5654: 4013 ands r3, r2 5656: 600b str r3, [r1, #0] } 5658: bf00 nop 565a: 3714 adds r7, #20 565c: 46bd mov sp, r7 565e: bc80 pop {r7} 5660: 4770 bx lr 5662: bf00 nop 5664: 40007400 .word 0x40007400 00005668 : * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data : Data to be loaded in the selected data holding register. * @retval None */ void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) { 5668: b480 push {r7} 566a: b085 sub sp, #20 566c: af00 add r7, sp, #0 566e: 6078 str r0, [r7, #4] 5670: 460b mov r3, r1 5672: 807b strh r3, [r7, #2] __IO uint32_t tmp = 0; 5674: 2300 movs r3, #0 5676: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)DAC_BASE; 5678: 4b07 ldr r3, [pc, #28] ; (5698 ) 567a: 60fb str r3, [r7, #12] tmp += DHR12R1_OFFSET + DAC_Align; 567c: 68fa ldr r2, [r7, #12] 567e: 687b ldr r3, [r7, #4] 5680: 4413 add r3, r2 5682: 3308 adds r3, #8 5684: 60fb str r3, [r7, #12] /* Set the DAC channel1 selected data holding register */ *(__IO uint32_t *) tmp = Data; 5686: 68fb ldr r3, [r7, #12] 5688: 461a mov r2, r3 568a: 887b ldrh r3, [r7, #2] 568c: 6013 str r3, [r2, #0] } 568e: bf00 nop 5690: 3714 adds r7, #20 5692: 46bd mov sp, r7 5694: bc80 pop {r7} 5696: 4770 bx lr 5698: 40007400 .word 0x40007400 0000569c : * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data : Data to be loaded in the selected data holding register. * @retval None */ void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) { 569c: b480 push {r7} 569e: b085 sub sp, #20 56a0: af00 add r7, sp, #0 56a2: 6078 str r0, [r7, #4] 56a4: 460b mov r3, r1 56a6: 807b strh r3, [r7, #2] __IO uint32_t tmp = 0; 56a8: 2300 movs r3, #0 56aa: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)DAC_BASE; 56ac: 4b07 ldr r3, [pc, #28] ; (56cc ) 56ae: 60fb str r3, [r7, #12] tmp += DHR12R2_OFFSET + DAC_Align; 56b0: 68fa ldr r2, [r7, #12] 56b2: 687b ldr r3, [r7, #4] 56b4: 4413 add r3, r2 56b6: 3314 adds r3, #20 56b8: 60fb str r3, [r7, #12] /* Set the DAC channel2 selected data holding register */ *(__IO uint32_t *)tmp = Data; 56ba: 68fb ldr r3, [r7, #12] 56bc: 461a mov r2, r3 56be: 887b ldrh r3, [r7, #2] 56c0: 6013 str r3, [r2, #0] } 56c2: bf00 nop 56c4: 3714 adds r7, #20 56c6: 46bd mov sp, r7 56c8: bc80 pop {r7} 56ca: 4770 bx lr 56cc: 40007400 .word 0x40007400 000056d0 : * @param Data1: Data for DAC Channel1 to be loaded in the selected data * holding register. * @retval None */ void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) { 56d0: b480 push {r7} 56d2: b085 sub sp, #20 56d4: af00 add r7, sp, #0 56d6: 6078 str r0, [r7, #4] 56d8: 460b mov r3, r1 56da: 807b strh r3, [r7, #2] 56dc: 4613 mov r3, r2 56de: 803b strh r3, [r7, #0] uint32_t data = 0, tmp = 0; 56e0: 2300 movs r3, #0 56e2: 60fb str r3, [r7, #12] 56e4: 2300 movs r3, #0 56e6: 60bb str r3, [r7, #8] assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data1)); assert_param(IS_DAC_DATA(Data2)); /* Calculate and set dual DAC data holding register value */ if (DAC_Align == DAC_Align_8b_R) 56e8: 687b ldr r3, [r7, #4] 56ea: 2b08 cmp r3, #8 56ec: d105 bne.n 56fa { data = ((uint32_t)Data2 << 8) | Data1; 56ee: 887b ldrh r3, [r7, #2] 56f0: 021a lsls r2, r3, #8 56f2: 883b ldrh r3, [r7, #0] 56f4: 4313 orrs r3, r2 56f6: 60fb str r3, [r7, #12] 56f8: e004 b.n 5704 } else { data = ((uint32_t)Data2 << 16) | Data1; 56fa: 887b ldrh r3, [r7, #2] 56fc: 041a lsls r2, r3, #16 56fe: 883b ldrh r3, [r7, #0] 5700: 4313 orrs r3, r2 5702: 60fb str r3, [r7, #12] } tmp = (uint32_t)DAC_BASE; 5704: 4b07 ldr r3, [pc, #28] ; (5724 ) 5706: 60bb str r3, [r7, #8] tmp += DHR12RD_OFFSET + DAC_Align; 5708: 687a ldr r2, [r7, #4] 570a: 68bb ldr r3, [r7, #8] 570c: 4413 add r3, r2 570e: 3320 adds r3, #32 5710: 60bb str r3, [r7, #8] /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; 5712: 68bb ldr r3, [r7, #8] 5714: 68fa ldr r2, [r7, #12] 5716: 601a str r2, [r3, #0] } 5718: bf00 nop 571a: 3714 adds r7, #20 571c: 46bd mov sp, r7 571e: bc80 pop {r7} 5720: 4770 bx lr 5722: bf00 nop 5724: 40007400 .word 0x40007400 00005728 : * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) { 5728: b480 push {r7} 572a: b085 sub sp, #20 572c: af00 add r7, sp, #0 572e: 6078 str r0, [r7, #4] __IO uint32_t tmp = 0; 5730: 2300 movs r3, #0 5732: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); tmp = (uint32_t) DAC_BASE ; 5734: 4b07 ldr r3, [pc, #28] ; (5754 ) 5736: 60fb str r3, [r7, #12] tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); 5738: 687b ldr r3, [r7, #4] 573a: 089a lsrs r2, r3, #2 573c: 68fb ldr r3, [r7, #12] 573e: 4413 add r3, r2 5740: 332c adds r3, #44 ; 0x2c 5742: 60fb str r3, [r7, #12] /* Returns the DAC channel data output register value */ return (uint16_t) (*(__IO uint32_t*) tmp); 5744: 68fb ldr r3, [r7, #12] 5746: 681b ldr r3, [r3, #0] 5748: b29b uxth r3, r3 } 574a: 4618 mov r0, r3 574c: 3714 adds r7, #20 574e: 46bd mov sp, r7 5750: bc80 pop {r7} 5752: 4770 bx lr 5754: 40007400 .word 0x40007400 00005758 : * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority * 0 bits for subpriority * @retval None */ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) { 5758: b480 push {r7} 575a: b083 sub sp, #12 575c: af00 add r7, sp, #0 575e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; 5760: 4a05 ldr r2, [pc, #20] ; (5778 ) 5762: 687b ldr r3, [r7, #4] 5764: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 5768: f443 3300 orr.w r3, r3, #131072 ; 0x20000 576c: 60d3 str r3, [r2, #12] } 576e: bf00 nop 5770: 370c adds r7, #12 5772: 46bd mov sp, r7 5774: bc80 pop {r7} 5776: 4770 bx lr 5778: e000ed00 .word 0xe000ed00 0000577c : * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains * the configuration information for the specified NVIC peripheral. * @retval None */ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) { 577c: b480 push {r7} 577e: b087 sub sp, #28 5780: af00 add r7, sp, #0 5782: 6078 str r0, [r7, #4] uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; 5784: 2300 movs r3, #0 5786: 617b str r3, [r7, #20] 5788: 2300 movs r3, #0 578a: 613b str r3, [r7, #16] 578c: 230f movs r3, #15 578e: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 5790: 687b ldr r3, [r7, #4] 5792: 78db ldrb r3, [r3, #3] 5794: 2b00 cmp r3, #0 5796: d03a beq.n 580e { /* Compute the Corresponding IRQ Priority --------------------------------*/ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 5798: 4b27 ldr r3, [pc, #156] ; (5838 ) 579a: 68db ldr r3, [r3, #12] 579c: 43db mvns r3, r3 579e: 0a1b lsrs r3, r3, #8 57a0: f003 0307 and.w r3, r3, #7 57a4: 617b str r3, [r7, #20] tmppre = (0x4 - tmppriority); 57a6: 697b ldr r3, [r7, #20] 57a8: f1c3 0304 rsb r3, r3, #4 57ac: 613b str r3, [r7, #16] tmpsub = tmpsub >> tmppriority; 57ae: 68fa ldr r2, [r7, #12] 57b0: 697b ldr r3, [r7, #20] 57b2: fa22 f303 lsr.w r3, r2, r3 57b6: 60fb str r3, [r7, #12] tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 57b8: 687b ldr r3, [r7, #4] 57ba: 785b ldrb r3, [r3, #1] 57bc: 461a mov r2, r3 57be: 693b ldr r3, [r7, #16] 57c0: fa02 f303 lsl.w r3, r2, r3 57c4: 617b str r3, [r7, #20] tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; 57c6: 687b ldr r3, [r7, #4] 57c8: 789b ldrb r3, [r3, #2] 57ca: 461a mov r2, r3 57cc: 68fb ldr r3, [r7, #12] 57ce: 4013 ands r3, r2 57d0: 697a ldr r2, [r7, #20] 57d2: 4313 orrs r3, r2 57d4: 617b str r3, [r7, #20] tmppriority = tmppriority << 0x04; 57d6: 697b ldr r3, [r7, #20] 57d8: 011b lsls r3, r3, #4 57da: 617b str r3, [r7, #20] NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 57dc: 4a17 ldr r2, [pc, #92] ; (583c ) 57de: 687b ldr r3, [r7, #4] 57e0: 781b ldrb r3, [r3, #0] 57e2: 6979 ldr r1, [r7, #20] 57e4: b2c9 uxtb r1, r1 57e6: 4413 add r3, r2 57e8: 460a mov r2, r1 57ea: f883 2300 strb.w r2, [r3, #768] ; 0x300 /* Enable the Selected IRQ Channels --------------------------------------*/ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 57ee: 687b ldr r3, [r7, #4] 57f0: 781b ldrb r3, [r3, #0] 57f2: f003 031f and.w r3, r3, #31 NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 57f6: 4911 ldr r1, [pc, #68] ; (583c ) 57f8: 687a ldr r2, [r7, #4] 57fa: 7812 ldrb r2, [r2, #0] 57fc: 0952 lsrs r2, r2, #5 57fe: b2d2 uxtb r2, r2 5800: 4610 mov r0, r2 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 5802: 2201 movs r2, #1 5804: fa02 f303 lsl.w r3, r2, r3 NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 5808: f841 3020 str.w r3, [r1, r0, lsl #2] { /* Disable the Selected IRQ Channels -------------------------------------*/ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } } 580c: e00f b.n 582e (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 580e: 687b ldr r3, [r7, #4] 5810: 781b ldrb r3, [r3, #0] 5812: f003 031f and.w r3, r3, #31 NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 5816: 4909 ldr r1, [pc, #36] ; (583c ) 5818: 687a ldr r2, [r7, #4] 581a: 7812 ldrb r2, [r2, #0] 581c: 0952 lsrs r2, r2, #5 581e: b2d2 uxtb r2, r2 5820: 4610 mov r0, r2 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 5822: 2201 movs r2, #1 5824: 409a lsls r2, r3 NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 5826: f100 0320 add.w r3, r0, #32 582a: f841 2023 str.w r2, [r1, r3, lsl #2] } 582e: bf00 nop 5830: 371c adds r7, #28 5832: 46bd mov sp, r7 5834: bc80 pop {r7} 5836: 4770 bx lr 5838: e000ed00 .word 0xe000ed00 583c: e000e100 .word 0xe000e100 00005840 : * @param Offset: Vector Table base offset field. This value must be a multiple * of 0x200. * @retval None */ void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) { 5840: b480 push {r7} 5842: b083 sub sp, #12 5844: af00 add r7, sp, #0 5846: 6078 str r0, [r7, #4] 5848: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); assert_param(IS_NVIC_OFFSET(Offset)); SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); 584a: 683b ldr r3, [r7, #0] 584c: f023 4360 bic.w r3, r3, #3758096384 ; 0xe0000000 5850: f023 037f bic.w r3, r3, #127 ; 0x7f 5854: 4904 ldr r1, [pc, #16] ; (5868 ) 5856: 687a ldr r2, [r7, #4] 5858: 4313 orrs r3, r2 585a: 608b str r3, [r1, #8] } 585c: bf00 nop 585e: 370c adds r7, #12 5860: 46bd mov sp, r7 5862: bc80 pop {r7} 5864: 4770 bx lr 5866: bf00 nop 5868: e000ed00 .word 0xe000ed00 0000586c : * @arg NVIC_LP_SLEEPONEXIT * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. * @retval None */ void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) { 586c: b480 push {r7} 586e: b083 sub sp, #12 5870: af00 add r7, sp, #0 5872: 4603 mov r3, r0 5874: 460a mov r2, r1 5876: 71fb strb r3, [r7, #7] 5878: 4613 mov r3, r2 587a: 71bb strb r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_LP(LowPowerMode)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 587c: 79bb ldrb r3, [r7, #6] 587e: 2b00 cmp r3, #0 5880: d006 beq.n 5890 { SCB->SCR |= LowPowerMode; 5882: 4b09 ldr r3, [pc, #36] ; (58a8 ) 5884: 691a ldr r2, [r3, #16] 5886: 79fb ldrb r3, [r7, #7] 5888: 4907 ldr r1, [pc, #28] ; (58a8 ) 588a: 4313 orrs r3, r2 588c: 610b str r3, [r1, #16] } else { SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); } } 588e: e006 b.n 589e SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 5890: 4b05 ldr r3, [pc, #20] ; (58a8 ) 5892: 691a ldr r2, [r3, #16] 5894: 79fb ldrb r3, [r7, #7] 5896: 43db mvns r3, r3 5898: 4903 ldr r1, [pc, #12] ; (58a8 ) 589a: 4013 ands r3, r2 589c: 610b str r3, [r1, #16] } 589e: bf00 nop 58a0: 370c adds r7, #12 58a2: 46bd mov sp, r7 58a4: bc80 pop {r7} 58a6: 4770 bx lr 58a8: e000ed00 .word 0xe000ed00 000058ac : * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) { 58ac: b480 push {r7} 58ae: b083 sub sp, #12 58b0: af00 add r7, sp, #0 58b2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 58b4: 687b ldr r3, [r7, #4] 58b6: 2b04 cmp r3, #4 58b8: d106 bne.n 58c8 { SysTick->CTRL |= SysTick_CLKSource_HCLK; 58ba: 4b09 ldr r3, [pc, #36] ; (58e0 ) 58bc: 681b ldr r3, [r3, #0] 58be: 4a08 ldr r2, [pc, #32] ; (58e0 ) 58c0: f043 0304 orr.w r3, r3, #4 58c4: 6013 str r3, [r2, #0] } else { SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; } } 58c6: e005 b.n 58d4 SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 58c8: 4b05 ldr r3, [pc, #20] ; (58e0 ) 58ca: 681b ldr r3, [r3, #0] 58cc: 4a04 ldr r2, [pc, #16] ; (58e0 ) 58ce: f023 0304 bic.w r3, r3, #4 58d2: 6013 str r3, [r2, #0] } 58d4: bf00 nop 58d6: 370c adds r7, #12 58d8: 46bd mov sp, r7 58da: bc80 pop {r7} 58dc: 4770 bx lr 58de: bf00 nop 58e0: e000e010 .word 0xe000e010 000058e4 : #define USE_STDPERIPH_DRIVER #include "stm32_p103.h" #include "myprintk.h" void sleep() { 58e4: b480 push {r7} 58e6: b083 sub sp, #12 58e8: af00 add r7, sp, #0 int i=1000000; 58ea: 4b07 ldr r3, [pc, #28] ; (5908 ) 58ec: 607b str r3, [r7, #4] while(i-->0); 58ee: bf00 nop 58f0: 687b ldr r3, [r7, #4] 58f2: 1e5a subs r2, r3, #1 58f4: 607a str r2, [r7, #4] 58f6: 2b00 cmp r3, #0 58f8: dcfa bgt.n 58f0 } 58fa: bf00 nop 58fc: bf00 nop 58fe: 370c adds r7, #12 5900: 46bd mov sp, r7 5902: bc80 pop {r7} 5904: 4770 bx lr 5906: bf00 nop 5908: 000f4240 .word 0x000f4240 0000590c
: int main(void) { 590c: b580 push {r7, lr} 590e: b086 sub sp, #24 5910: af02 add r7, sp, #8 uint8_t b; int32_t num1=0x1234; 5912: f241 2334 movw r3, #4660 ; 0x1234 5916: 60fb str r3, [r7, #12] char *str1="Strings"; 5918: 4b08 ldr r3, [pc, #32] ; (593c ) 591a: 60bb str r3, [r7, #8] char ch1='Z'; 591c: 235a movs r3, #90 ; 0x5a 591e: 71fb strb r3, [r7, #7] //first init myprintf device(usart2) myprintf_init(); 5920: f7fa ffbe bl 8a0 while(1) { myprintf("test num %d=0x%x str %s ch %c\n",num1,num1,str1,ch1); 5924: 79fb ldrb r3, [r7, #7] 5926: 9300 str r3, [sp, #0] 5928: 68bb ldr r3, [r7, #8] 592a: 68fa ldr r2, [r7, #12] 592c: 68f9 ldr r1, [r7, #12] 592e: 4804 ldr r0, [pc, #16] ; (5940 ) 5930: f7fb fbfb bl 112a sleep(); 5934: f7ff ffd6 bl 58e4 myprintf("test num %d=0x%x str %s ch %c\n",num1,num1,str1,ch1); 5938: e7f4 b.n 5924 593a: bf00 nop 593c: 00005a84 .word 0x00005a84 5940: 00005a8c .word 0x00005a8c 00005944 : 5944: b4f0 push {r4, r5, r6, r7} 5946: 0786 lsls r6, r0, #30 5948: d046 beq.n 59d8 594a: 1e54 subs r4, r2, #1 594c: 2a00 cmp r2, #0 594e: d03c beq.n 59ca 5950: 4603 mov r3, r0 5952: b2ca uxtb r2, r1 5954: e001 b.n 595a 5956: 3c01 subs r4, #1 5958: d337 bcc.n 59ca 595a: f803 2b01 strb.w r2, [r3], #1 595e: 079d lsls r5, r3, #30 5960: d1f9 bne.n 5956 5962: 2c03 cmp r4, #3 5964: d92a bls.n 59bc 5966: b2cd uxtb r5, r1 5968: ea45 2505 orr.w r5, r5, r5, lsl #8 596c: 2c0f cmp r4, #15 596e: ea45 4505 orr.w r5, r5, r5, lsl #16 5972: d934 bls.n 59de 5974: f1a4 0210 sub.w r2, r4, #16 5978: f022 0c0f bic.w ip, r2, #15 597c: f103 0720 add.w r7, r3, #32 5980: 0916 lsrs r6, r2, #4 5982: 4467 add r7, ip 5984: f103 0210 add.w r2, r3, #16 5988: e942 5504 strd r5, r5, [r2, #-16] 598c: e942 5502 strd r5, r5, [r2, #-8] 5990: 3210 adds r2, #16 5992: 42ba cmp r2, r7 5994: d1f8 bne.n 5988 5996: 1c72 adds r2, r6, #1 5998: f014 0f0c tst.w r4, #12 599c: eb03 1202 add.w r2, r3, r2, lsl #4 59a0: f004 060f and.w r6, r4, #15 59a4: d013 beq.n 59ce 59a6: 1f33 subs r3, r6, #4 59a8: f023 0303 bic.w r3, r3, #3 59ac: 3304 adds r3, #4 59ae: 4413 add r3, r2 59b0: f842 5b04 str.w r5, [r2], #4 59b4: 4293 cmp r3, r2 59b6: d1fb bne.n 59b0 59b8: f006 0403 and.w r4, r6, #3 59bc: b12c cbz r4, 59ca 59be: b2ca uxtb r2, r1 59c0: 441c add r4, r3 59c2: f803 2b01 strb.w r2, [r3], #1 59c6: 429c cmp r4, r3 59c8: d1fb bne.n 59c2 59ca: bcf0 pop {r4, r5, r6, r7} 59cc: 4770 bx lr 59ce: 4634 mov r4, r6 59d0: 4613 mov r3, r2 59d2: 2c00 cmp r4, #0 59d4: d1f3 bne.n 59be 59d6: e7f8 b.n 59ca 59d8: 4614 mov r4, r2 59da: 4603 mov r3, r0 59dc: e7c1 b.n 5962 59de: 461a mov r2, r3 59e0: 4626 mov r6, r4 59e2: e7e0 b.n 59a6 000059e4 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 59e4: 2100 movs r1, #0 b LoopCopyDataInit 59e6: e003 b.n 59f0 000059e8 : CopyDataInit: ldr r3, =_sidata 59e8: 4b0a ldr r3, [pc, #40] ; (5a14 ) ldr r3, [r3, r1] 59ea: 585b ldr r3, [r3, r1] str r3, [r0, r1] 59ec: 5043 str r3, [r0, r1] adds r1, r1, #4 59ee: 3104 adds r1, #4 000059f0 : LoopCopyDataInit: ldr r0, =_sdata 59f0: 4809 ldr r0, [pc, #36] ; (5a18 ) ldr r3, =_edata 59f2: 4b0a ldr r3, [pc, #40] ; (5a1c ) adds r2, r0, r1 59f4: 1842 adds r2, r0, r1 cmp r2, r3 59f6: 429a cmp r2, r3 bcc CopyDataInit 59f8: d3f6 bcc.n 59e8 ldr r2, =_sbss 59fa: 4a09 ldr r2, [pc, #36] ; (5a20 ) b LoopFillZerobss 59fc: e002 b.n 5a04 000059fe : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 59fe: 2300 movs r3, #0 str r3, [r2], #4 5a00: f842 3b04 str.w r3, [r2], #4 00005a04 : LoopFillZerobss: ldr r3, = _ebss 5a04: 4b07 ldr r3, [pc, #28] ; (5a24 ) cmp r2, r3 5a06: 429a cmp r2, r3 bcc FillZerobss 5a08: d3f9 bcc.n 59fe /* Call the clock system intitialization function.*/ bl SystemInit 5a0a: f7fa fca9 bl 360 /* Call the application's entry point.*/ bl main 5a0e: f7ff ff7d bl 590c
bx lr 5a12: 4770 bx lr ldr r3, =_sidata 5a14: 00005bad .word 0x00005bad ldr r0, =_sdata 5a18: 20000000 .word 0x20000000 ldr r3, =_edata 5a1c: 20000028 .word 0x20000028 ldr r2, =_sbss 5a20: 20000028 .word 0x20000028 ldr r3, = _ebss 5a24: 20000028 .word 0x20000028 00005a28 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 5a28: e7fe b.n 5a28 5a2a: 0000 movs r0, r0 5a2c: 33323130 .word 0x33323130 5a30: 37363534 .word 0x37363534 5a34: 62613938 .word 0x62613938 5a38: 66656463 .word 0x66656463 5a3c: 6a696867 .word 0x6a696867 5a40: 6e6d6c6b .word 0x6e6d6c6b 5a44: 7271706f .word 0x7271706f 5a48: 76757473 .word 0x76757473 5a4c: 7a797877 .word 0x7a797877 5a50: 00000000 .word 0x00000000 5a54: 33323130 .word 0x33323130 5a58: 37363534 .word 0x37363534 5a5c: 42413938 .word 0x42413938 5a60: 46454443 .word 0x46454443 5a64: 4a494847 .word 0x4a494847 5a68: 4e4d4c4b .word 0x4e4d4c4b 5a6c: 5251504f .word 0x5251504f 5a70: 56555453 .word 0x56555453 5a74: 5a595857 .word 0x5a595857 5a78: 00000000 .word 0x00000000 5a7c: 4c554e3c .word 0x4c554e3c 5a80: 00003e4c .word 0x00003e4c 5a84: 69727453 .word 0x69727453 5a88: 0073676e .word 0x0073676e 5a8c: 74736574 .word 0x74736574 5a90: 6d756e20 .word 0x6d756e20 5a94: 3d642520 .word 0x3d642520 5a98: 78257830 .word 0x78257830 5a9c: 72747320 .word 0x72747320 5aa0: 20732520 .word 0x20732520 5aa4: 25206863 .word 0x25206863 5aa8: 00000a63 .word 0x00000a63 00005aac <_ctype_>: 5aac: 20202000 20202020 28282020 20282828 . ((((( 5abc: 20202020 20202020 20202020 20202020 5acc: 10108820 10101010 10101010 10101010 ............... 5adc: 04040410 04040404 10040404 10101010 ................ 5aec: 41411010 41414141 01010101 01010101 ..AAAAAA........ 5afc: 01010101 01010101 01010101 10101010 ................ 5b0c: 42421010 42424242 02020202 02020202 ..BBBBBB........ 5b1c: 02020202 02020202 02020202 10101010 ................ 5b2c: 00000020 00000000 00000000 00000000 ............... ...