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83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
#ifndef __SWM320_SDRAM_H__
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#define __SWM320_SDRAM_H__
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typedef struct {
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uint8_t CellSize; // SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM_CELLSIZE_16Mb<4D><62>SDRAM_CELLSIZE_64Mb<4D><62>SDRAM_CELLSIZE_128Mb<4D><62>SDRAM_CELLSIZE_256Mb
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uint8_t CellBank; // SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD>м<EFBFBD><D0BC><EFBFBD>bank<6E><6B>SDRAM_CELLBANK_2<5F><32>SDRAM_CELLBANK_4
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uint8_t CellWidth; // SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>SDRAM_CELLWIDTH_16<31><36>SDRAM_CELLWIDTH_32
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uint8_t CASLatency; // <20>е<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SDRAM_CASLATENCY_2<5F><32>SDRAM_CASLATENCY_3
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uint8_t TimeTMRD; // MRS to New Command
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uint8_t TimeTRRD; // Activate to activate on different banks
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uint8_t TimeTRAS; // Self refresh time<6D><65><EFBFBD><EFBFBD>СSelf-refresh<73><68><EFBFBD><EFBFBD>
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uint8_t TimeTRC; // Row cycle delay<61><79>Refresh<73><68><EFBFBD>Activate<74><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Refresh<73><68><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
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uint8_t TimeTRCD; // Row to column delay<61><79><EFBFBD>е<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>е<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ҳ<EFBFBD><D2B2>Activate<74><65><EFBFBD><EFBFBD><EEB5BD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
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uint8_t TimeTRP; // Row precharge delay<61><79>Precharge<67><65><EFBFBD><EFBFBD><EEB5BD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ
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} SDRAM_InitStructure;
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#define SDRAM_CELLSIZE_16Mb 3
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#define SDRAM_CELLSIZE_64Mb 0
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#define SDRAM_CELLSIZE_128Mb 1
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#define SDRAM_CELLSIZE_256Mb 2
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#define SDRAM_CELLBANK_2 0
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#define SDRAM_CELLBANK_4 1
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#define SDRAM_CELLWIDTH_16 0
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#define SDRAM_CELLWIDTH_32 1
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#define SDRAM_CASLATENCY_2 2
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#define SDRAM_CASLATENCY_3 3
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#define SDRAM_TMRD_3 3
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#define SDRAM_TMRD_4 4
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#define SDRAM_TMRD_5 5
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#define SDRAM_TMRD_6 6
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#define SDRAM_TMRD_7 7
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#define SDRAM_TRRD_2 2
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#define SDRAM_TRRD_3 3
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#define SDRAM_TRAS_2 2
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#define SDRAM_TRAS_3 3
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#define SDRAM_TRAS_4 4
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#define SDRAM_TRAS_5 5
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#define SDRAM_TRAS_6 6
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#define SDRAM_TRAS_7 7
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#define SDRAM_TRC_2 2
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#define SDRAM_TRC_3 3
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#define SDRAM_TRC_4 4
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#define SDRAM_TRC_5 5
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#define SDRAM_TRC_6 6
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#define SDRAM_TRC_7 7
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#define SDRAM_TRC_8 8
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#define SDRAM_TRC_9 9
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#define SDRAM_TRC_10 10
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#define SDRAM_TRC_11 11
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#define SDRAM_TRC_12 12
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#define SDRAM_TRC_13 13
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#define SDRAM_TRC_14 14
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#define SDRAM_TRC_15 15
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#define SDRAM_TRCD_3 3
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#define SDRAM_TRCD_4 4
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#define SDRAM_TRCD_5 5
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#define SDRAM_TRCD_6 6
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#define SDRAM_TRCD_7 7
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#define SDRAM_TRP_3 3
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#define SDRAM_TRP_4 4
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#define SDRAM_TRP_5 5
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#define SDRAM_TRP_6 6
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#define SDRAM_TRP_7 7
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void SDRAM_Init(SDRAM_InitStructure * initStruct);
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void SDRAM_Enable(void);
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void SDRAM_Disable(void);
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#endif //__SWM320_SDRAM_H__
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