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263 lines
12 KiB
C
263 lines
12 KiB
C
#ifndef __WM_DMA_H__
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#define __WM_DMA_H__
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#include "wm_type_def.h"
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#include "wm_regs.h"
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typedef enum
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{
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HAL_DMA_STATE_RESET = 0x00U,
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HAL_DMA_STATE_READY = 0x01U,
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HAL_DMA_STATE_BUSY = 0x02U,
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HAL_DMA_STATE_TIMEOUT = 0x03U
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}HAL_DMA_StateTypeDef;
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typedef struct
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{
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uint32_t Direction; /* Specifies if the data will be transferred from memory to peripheral,
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from peripheral to memory or from memmory to memory.
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This parameter can be a value of @ref DMA_DATA_TRANSFER_DIRECTION*/
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uint32_t DestInc; /* Specifies weather the destination address should be incremented or not.
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When mode is DMA_MODE_NORMAL_CIRCULAR and destination address need increment,
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must choose DMA_DINC_CIRCULAR.
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This parameter can be a value of @ref DMA_DEST_ADDR_INCREMENT*/
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uint32_t SrcInc; /* Specifies weather the source address should be incremented or not.
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When mode is DMA_MODE_NORMAL_CIRCULAR and Source address need increment,
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must choose DMA_SINC_CIRCULAR.
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This parameter can be a value of @ref DMA_SRC_ADDR_INCREMENT*/
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uint32_t DataAlignment; /* Specifies the transport unit.
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This parameter can be a value of @ref DMA_DATAALIGN*/
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uint32_t Mode; /* Specifies the operation mode of the DMA channelx. When you need to
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use half-complete interrupts, you must use link mode.
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This parameter can be a value of @ref DMA_MODE*/
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uint32_t RequestSourceSel; /* Specifies the request source of DMA.
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This parameter can be a value of @ref DMA_REQUEST_SOURCE*/
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uint32_t RequestUartSel; /* Specifies the UART number when the RequestSourceSel is DMA_REQUEST_SOURCE_UART_RX
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or DMA_REQUEST_SOURCE_UART_TX. This parameter can be a value of @ref DMA_UART_CHANNEL_SEL*/
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} DMA_InitTypeDef;
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/* The descriptor structure is used internally by the driver layer,
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and the user layer does not need to be assigned. */
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typedef struct __DMA_LinkDescriptor
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{
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uint32_t Valid; /* According to the Bit31 to indicate whether the data pointed to by the
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descriptor is valid. Bit31 equal to 1 means valid, equal to 0 means invalid */
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uint32_t Control; /* Equal to the value of register CR2[23:1] */
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uint32_t SrcAddr; /* Data source address */
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uint32_t DestAddr; /* Data destinathion address */
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struct __DMA_LinkDescriptor *Next; /* Point to the address of the next descriptor structure */
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} DMA_LinkDescriptor;
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typedef enum
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{
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HAL_DMA_HALF_TRANSFER = 0,
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HAL_DMA_FULL_TRANSFER = 1
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} HAL_DMA_LevelCompleteTypeDef;
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typedef struct __DMA_HandleTypeDef
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{
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DMA_Channel_TypeDef *Instance; /* Register base address of the channel used.
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Need user layer assignment.*/
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DMA_InitTypeDef Init; /* DMA communication parameters. Need user layer assignment*/
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HAL_LockTypeDef Lock; /* DMA locking object. */
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HAL_DMA_StateTypeDef State; /* DMA transfer state. */
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void *Parent; /* Parent object state. Need user layer assignment*/
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void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /* DMA transfer complete callback. */
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void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /* DMA Half transfer complete callback. */
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void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /* DMA transfer abort callback. */
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DMA_TypeDef *DmaBaseAddress; /* DMA register base address. */
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uint32_t ChannelIndex; /* DMA Channel Index. */
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__IO uint32_t ErrorCode; /* DMA error code. */
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DMA_LinkDescriptor *LinkDesc; /* Points to the descriptor address. When user need to use the
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DMA half-completed interrupt, assign a value in the user layer.
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E.g DMA_LinkDescriptor desc[2], Size must be 2. */
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uint32_t offset; /* For internal use, the user does not need to assign a value. */
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} DMA_HandleTypeDef;
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// DMA register base address and channel base address.
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#define DMA ((DMA_TypeDef *)DMA_BASE)
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#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
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#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
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#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
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#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
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#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
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#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
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#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
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#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)
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// DMA Error Code
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#define HAL_DMA_ERROR_NONE 0x0U // No error
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#define HAL_DMA_ERROR_NO_XFER 0x1U // no ongoing transfer
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#define HAL_DMA_ERROR_TIMEOUT 0x2U // Timout error
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#define HAL_DMA_ERROR_NOT_SUPPORTED 0x4U // Not supported mode
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// DMA_DATA_TRANSFER_DIRECTION
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#define DMA_PERIPH_TO_MEMORY ((uint32_t)DMA_MODE_SHM) // Peripheral to memory direction
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#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_MODE_SHM) // Memory to peripheral direction
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#define DMA_MEMORY_TO_MEMORY 0x00000000U // Memory to memory direction
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// DMA_DEST_ADDR_INCREMENT
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#define DMA_DINC_ENABLE ((uint32_t)DMA_CR2_DINC_ENABLE) // Destination address increment mode Enable
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#define DMA_DINC_DISABLE ((uint32_t)DMA_CR2_DINC_DISABLE) // Destination address increment mode Disable
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#define DMA_DINC_CIRCULAR ((uint32_t)DMA_CR2_DINC_CYCLE) // Destination address circular mode. Only when Mode = DMA_MODE_NORMAL_CIRCULAR
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// DMA_SRC_ADDR_INCREMENT
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#define DMA_SINC_ENABLE ((uint32_t)DMA_CR2_SINC_ENABLE) // Source address increment mode Enable
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#define DMA_SINC_DISABLE ((uint32_t)DMA_CR2_SINC_DISABLE) // Source address increment mode Disable
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#define DMA_SINC_CIRCULAR ((uint32_t)DMA_CR2_SINC_CYCLE) // Source address circular mode. Only when Mode = DMA_MODE_NORMAL_CIRCULAR
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// DMA_DATAALIGN
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#define DMA_DATAALIGN_BYTE ((uint32_t)DMA_CR2_TRANS_SIZE_BYTE) // Memory data alignment: Byte
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#define DMA_DATAALIGN_HALFWORD ((uint32_t)DMA_CR2_TRANS_SIZE_HALFWORD) // Memory data alignment: HalfWord
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#define DMA_DATAALIGN_WORD ((uint32_t)DMA_CR2_TRANS_SIZE_WORD) // Memory data alignment: Word
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// DMA_MODE
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#define DMA_MODE_NORMAL_SINGLE 0x00000000U // Normal single mode
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#define DMA_MODE_NORMAL_CIRCULAR 0x00000001U // Normal circular mode
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#define DMA_MODE_LINK_SINGLE 0x00000002U // Link singal mode
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#define DMA_MODE_LINK_CIRCULAR 0x00000003U // Link circular mode
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// DMA_INTERRUPT_TYPE
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#define DMA_FLAG_TF_DONE DMA_IF_TRANSFER_DONE // Transfer complete interrupt
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#define DMA_FLAG_BURST_DONE DMA_IF_BURST_DONE // Burst complete interrupt
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// DMA_REQUEST_SOURCE
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#define DMA_REQUEST_SOURCE_UART_RX DMA_MODE_CH_UART_RX
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#define DMA_REQUEST_SOURCE_UART_TX DMA_MODE_CH_UART_TX
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#define DMA_REQUEST_SOURCE_PWM_CAP0 DMA_MODE_CH_PWM_CAP0
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#define DMA_REQUEST_SOURCE_PWM_CAP1 DMA_MODE_CH_PWM_CAP1
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#define DMA_REQUEST_SOURCE_SPI_RX DMA_MODE_CH_LSPI_RX
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#define DMA_REQUEST_SOURCE_SPI_TX DMA_MODE_CH_LSPI_TX
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#define DMA_REQUEST_SOURCE_ADC_CH0 DMA_MODE_CH_ADC0
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#define DMA_REQUEST_SOURCE_ADC_CH1 DMA_MODE_CH_ADC1
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#define DMA_REQUEST_SOURCE_ADC_CH2 DMA_MODE_CH_ADC2
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#define DMA_REQUEST_SOURCE_ADC_CH3 DMA_MODE_CH_ADC3
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#define DMA_REQUEST_SOURCE_I2S_RX DMA_MODE_CH_I2SRX
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#define DMA_REQUEST_SOURCE_I2S_TX DMA_MODE_CH_I2STX
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#define DMA_REQUEST_SOURCE_SDIO DMA_MODE_CH_SDIO
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// DMA_UART_CHANNEL_SEL
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#define DMA_UART_CHANNEL_SEL_UART0 DMA_REQCH_UART0
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#define DMA_UART_CHANNEL_SEL_UART1 DMA_REQCH_UART1
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#define DMA_UART_CHANNEL_SEL_UART2 DMA_REQCH_UART2
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#define DMA_UART_CHANNEL_SEL_UART3 DMA_REQCH_UART3
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#define DMA_UART_CHANNEL_SEL_UART4 DMA_REQCH_UART4
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#define DMA_UART_CHANNEL_SEL_UART5 DMA_REQCH_UART5
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#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA_Channel0) || \
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((INSTANCE) == DMA_Channel1) || \
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((INSTANCE) == DMA_Channel2) || \
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((INSTANCE) == DMA_Channel3) || \
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((INSTANCE) == DMA_Channel4) || \
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((INSTANCE) == DMA_Channel5) || \
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((INSTANCE) == DMA_Channel6) || \
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((INSTANCE) == DMA_Channel7))
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#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \
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((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
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((DIRECTION) == DMA_MEMORY_TO_MEMORY))
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#define IS_DMA_DEST_INC_STATE(STATE) (((STATE) == DMA_DINC_ENABLE) || \
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((STATE) == DMA_DINC_DISABLE))
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#define IS_DMA_SRC_INC_STATE(STATE) (((STATE) == DMA_SINC_ENABLE) || \
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((STATE) == DMA_SINC_DISABLE))
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#define IS_DMA_DATA_SIZE(SIZE) (((SIZE) == DMA_DATAALIGN_BYTE) || \
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((SIZE) == DMA_DATAALIGN_HALFWORD) || \
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((SIZE) == DMA_DATAALIGN_WORD))
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#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_NORMAL_SINGLE) || \
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((MODE) == DMA_MODE_NORMAL_CIRCULAR) || \
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((MODE) == DMA_MODE_LINK_SINGLE) || \
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((MODE) == DMA_MODE_LINK_CIRCULAR))
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#define IS_DMA_REQUEST_SOURCE(SEL) (((SEL) == DMA_REQUEST_SOURCE_UART_RX) || \
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((SEL) == DMA_REQUEST_SOURCE_UART_TX) || \
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((SEL) == DMA_REQUEST_SOURCE_PWM_CAP0) || \
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((SEL) == DMA_REQUEST_SOURCE_PWM_CAP1) || \
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((SEL) == DMA_REQUEST_SOURCE_SPI_RX) || \
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((SEL) == DMA_REQUEST_SOURCE_SPI_TX) || \
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((SEL) == DMA_REQUEST_SOURCE_ADC_CH0) || \
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((SEL) == DMA_REQUEST_SOURCE_ADC_CH1) || \
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((SEL) == DMA_REQUEST_SOURCE_ADC_CH2) || \
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((SEL) == DMA_REQUEST_SOURCE_ADC_CH3) || \
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((SEL) == DMA_REQUEST_SOURCE_I2S_RX) || \
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((SEL) == DMA_REQUEST_SOURCE_I2S_TX) || \
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((SEL) == DMA_REQUEST_SOURCE_SDIO))
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#define IS_DMA_UART_CHANNEL(CHANNEL) (((CHANNEL) == DMA_UART_CHANNEL_SEL_UART0) || \
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((CHANNEL) == DMA_UART_CHANNEL_SEL_UART1) || \
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((CHANNEL) == DMA_UART_CHANNEL_SEL_UART2) || \
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((CHANNEL) == DMA_UART_CHANNEL_SEL_UART3) || \
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((CHANNEL) == DMA_UART_CHANNEL_SEL_UART4) || \
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((CHANNEL) == DMA_UART_CHANNEL_SEL_UART5))
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#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
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#define IS_DMA_SRC_ADDR(SRC) (((SRC) % 4) == 0)
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#define IS_DMA_DEST_ADDR(DEST) (((DEST) % 4) == 0)
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#define IS_DMA_LENGTH(DATAALIGN, LEN) ((((DATAALIGN) == DMA_DATAALIGN_BYTE) && (((LEN) % 1) == 0)) || \
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(((DATAALIGN) == DMA_DATAALIGN_HALFWORD) && (((LEN) % 2) == 0)) || \
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(((DATAALIGN) == DMA_DATAALIGN_WORD) && (((LEN) % 4) == 0)))
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#define IS_DMA_LINK_LENGTH(LEN) (((LINK) % 8) == 0)
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#define IS_DMA_COMPLETELEVEL(LEVEL) (((LEVEL) == HAL_DMA_HALF_TRANSFER) || ((LEVEL) = HAL_DMA_FULL_TRANSFER))
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#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, DMA_CR1_START))
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#define __HAL_DMA_DISABLE(__HANDLE__) do { \
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SET_BIT((__HANDLE__)->Instance->CR1, DMA_CR1_STOP); \
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while ((__HANDLE__)->Instance->CR1 & DMA_CR1_START); \
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} while (0)
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#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->DmaBaseAddress->IM, (__INTERRUPT__)))
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#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->DmaBaseAddress->IM, (__INTERRUPT__)))
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#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->DmaBaseAddress->IF) & (__FLAG__))
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#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT((__HANDLE__)->DmaBaseAddress->IF, (__FLAG__)))
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HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
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HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
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HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint16_t DataLength);
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HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint16_t DataLength);
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HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
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HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
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HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
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void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
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HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
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uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
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#endif |