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249 lines
9.8 KiB
C
249 lines
9.8 KiB
C
#ifndef __WM_I2S_H__
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#define __WM_I2S_H__
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#include "wm_hal.h"
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#include "wm_dma.h"
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/**
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* @brief I2S Init structure definition
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*/
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typedef struct
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{
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uint32_t Mode; /* Specifies the I2S operating mode.
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This parameter can be a value of @ref I2S_MODE */
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uint32_t Standard; /* Specifies the standard used for the I2S communication.
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This parameter can be a value of @ref I2S_STANDARD */
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uint32_t DataFormat; /* Specifies the data format for the I2S communication.
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This parameter can be a value of @ref I2S_DATA_FORMAT */
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uint32_t MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not.
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This parameter can be a value of @ref I2S_MCLK_OUTPUT */
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uint32_t AudioFreq; /* Specifies the frequency selected for the I2S communication.
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This parameter can be a value of @ref I2S_AUDIO_FREQUENCY */
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uint32_t Channel; /* Specifies the data is mono or stereo.
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This parameter can be a value of @ref I2S_CHANNEL */
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uint32_t ChannelSel; /* Specifies the left channel or the right channel when Channel is mono.
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This parameter can be a value of @ref I2S_CHANNELSEL */
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} I2S_InitTypeDef;
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/**
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* @brief HAL State structures definition
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*/
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typedef enum
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{
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HAL_I2S_STATE_RESET = 0x00, // I2S not yet initialized or disabled
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HAL_I2S_STATE_READY = 0x01, // I2S initialized and ready for use
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HAL_I2S_STATE_BUSY = 0x02, // I2S internal process is ongoing
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HAL_I2S_STATE_BUSY_TX = 0x03, // Data Transmission process is ongoing
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HAL_I2S_STATE_BUSY_RX = 0x04, // Data Reception process is ongoing
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HAL_I2S_STATE_BUSY_TXRX = 0x05, // Data Transmission and Reception process is ongoing
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HAL_I2S_STATE_TIMEOUT = 0x06, // I2S timeout state
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HAL_I2S_STATE_ERROR = 0x07 // I2S error state
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} HAL_I2S_StateTypeDef;
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/**
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* @brief I2S handle Structure definition
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*/
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typedef struct
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{
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I2S_TypeDef *Instance; /* I2S registers base address */
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I2S_InitTypeDef Init; /* I2S communication parameters */
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uint32_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
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__IO uint32_t TxXferSize; /* I2S Tx transfer size */
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__IO uint32_t TxXferCount; /* I2S Tx transfer Counter */
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uint32_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
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__IO uint32_t RxXferSize; /* I2S Rx transfer size */
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__IO uint32_t RxXferCount; /* I2S Rx transfer counter
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(This field is initialized at the
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same value as transfer size at the
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beginning of the transfer and
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decremented when a sample is received
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NbSamplesReceived = RxBufferSize-RxBufferCount) */
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DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
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DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
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__IO HAL_LockTypeDef Lock; /* I2S locking object */
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__IO HAL_I2S_StateTypeDef State; /* I2S communication state */
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__IO uint32_t ErrorCode; /* I2S Error code
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This parameter can be a value of @ref I2S_ERROR */
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} I2S_HandleTypeDef;
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#define I2S (I2S_TypeDef *)I2S_BASE // I2S register base address
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// I2S_ERROR
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#define HAL_I2S_ERROR_NONE (0x00) // No error
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#define HAL_I2S_ERROR_TIMEOUT (0x01) // Timeout error
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#define HAL_I2S_ERROR_TXERR (0x02) // Tx error
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#define HAL_I2S_ERROR_RXERR (0x04) // Rx error
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#define HAL_I2S_ERROR_DMA (0x08) // DMA transfer error
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#define HAL_I2S_ERROR_PRESCALER (0x10) // Prescaler Calculation error
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// I2S_MODE
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#define I2S_MODE_MASTER (0x00000000U)
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#define I2S_MODE_SLAVE (I2S_CR_MODE)
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// I2S_STANDARD
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#define I2S_STANDARD_PHILIPS I2S_CR_FORMAT_I2S
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#define I2S_STANDARD_MSB I2S_CR_FORMAT_MSBJUSTIFIED
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#define I2S_STANDARD_PCMA I2S_CR_FORMAT_PCMA
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#define I2S_STANDARD_PCMB I2S_CR_FORMAT_PCMB
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// I2S_DATA_FORMAT
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#define I2S_DATAFORMAT_8B I2S_CR_DATALEN_8BIT
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#define I2S_DATAFORMAT_16B I2S_CR_DATALEN_16BIT
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#define I2S_DATAFORMAT_24B I2S_CR_DATALEN_24BIT
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#define I2S_DATAFORMAT_32B I2S_CR_DATALEN_32BIT
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// I2S_MCLK_OUTPUT
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#define I2S_MCLKOUTPUT_ENABLE RCC_I2S_CLK_MCLK_EN
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#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
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// I2S_AUDIO_FREQUENCY
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#define I2S_AUDIOFREQ_192K (192000U)
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#define I2S_AUDIOFREQ_96K (96000U)
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#define I2S_AUDIOFREQ_48K (48000U)
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#define I2S_AUDIOFREQ_44K (44100U)
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#define I2S_AUDIOFREQ_32K (32000U)
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#define I2S_AUDIOFREQ_24K (24000U)
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#define I2S_AUDIOFREQ_22K (22050U)
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#define I2S_AUDIOFREQ_16K (16000U)
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#define I2S_AUDIOFREQ_12K (12000U)
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#define I2S_AUDIOFREQ_11K (11025U)
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#define I2S_AUDIOFREQ_8K (8000U)
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#define I2S_AUDIOFREQ_DEFAULT (2U)
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// I2S_CHANNEL
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#define I2S_CHANNEL_MONO (I2S_CR_MONO_STEREO)
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#define I2S_CHANNEL_STEREO (0x00000000U)
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// I2S_CHANNELSEL
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#define I2S_CHANNELSEL_LEFT I2S_CR_RXLRCH
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#define I2S_CHANNELSEL_RIGHT (0x00000000U)
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#define I2S_FIFO_FULL 8
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#define I2S_TIMEOUT_FLAG 100U
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#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2S)
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#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \
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((__MODE__) == I2S_MODE_MASTER_RX) || \
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((__MODE__) == I2S_MODE_MASTER_TX_RX) || \
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((__MODE__) == I2S_MODE_SLAVE_TX) || \
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((__MODE__) == I2S_MODE_SLAVE_RX) || \
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((__MODE__) == I2S_MODE_SLAVE_TX_RX))
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#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
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((__STANDARD__) == I2S_STANDARD_MSB) || \
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((__STANDARD__) == I2S_STANDARD_PCMA) || \
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((__STANDARD__) == I2S_STANDARD_PCMB))
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#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_8B) || \
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((__FORMAT__) == I2S_DATAFORMAT_16B) || \
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((__FORMAT__) == I2S_DATAFORMAT_24B) || \
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((__FORMAT__) == I2S_DATAFORMAT_32B))
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#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
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((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
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#define IS_I2S_AUDIO_FREQ(__FREQ__) (((__FREQ__) == I2S_AUDIOFREQ_192K) || \
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((__FREQ__) == I2S_AUDIOFREQ_96K) || \
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((__FREQ__) == I2S_AUDIOFREQ_48K) || \
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((__FREQ__) == I2S_AUDIOFREQ_44K) || \
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((__FREQ__) == I2S_AUDIOFREQ_32K) || \
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((__FREQ__) == I2S_AUDIOFREQ_24K) || \
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((__FREQ__) == I2S_AUDIOFREQ_22K) || \
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((__FREQ__) == I2S_AUDIOFREQ_16K) || \
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((__FREQ__) == I2S_AUDIOFREQ_12K) || \
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((__FREQ__) == I2S_AUDIOFREQ_11K) || \
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((__FREQ__) == I2S_AUDIOFREQ_8K) || \
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((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
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#define IS_I2S_CHANNEL(__CHANNEL__) (((__CHANNEL__) == I2S_AUDIO_MONO) || \
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((__CHANNEL__) == I2S_AUIDO_STEREO))
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#define IS_I2S_CHANNELSEL(__SEL__) (((__SEL__) == I2S_CHANNELSEL_LEFT) || \
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((__SEL__) == I2S_CHANNELSEL_RIGHT))
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#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, I2S_CR_EN))
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#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, I2S_CR_EN))
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#define __HAL_I2S_ENABLE_TX(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, I2S_CR_TXEN))
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#define __HAL_I2S_DISABLE_TX(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, I2S_CR_TXEN))
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#define __HAL_I2S_ENABLE_RX(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, I2S_CR_RXEN))
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#define __HAL_I2S_DISABLE_RX(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, I2S_CR_RXEN))
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#define __HAL_I2S_GET_TXFIFO(__HANDLE__) (((__HANDLE__)->Instance->SR & I2S_SR_TXCNT) >> I2S_SR_TXCNT_Pos)
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#define __HAL_I2S_GET_RXFIFO(__HANDLE__) ((__HANDLE__)->Instance->SR & I2S_SR_RXCNT)
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#define __HAL_I2S_ENABLE_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IM &= ~(__FLAG__))
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#define __HAL_I2S_DISABLE_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IM |= (__FLAG__))
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#define __HAL_I2S_GET_IT(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->IF) & (__FLAG__))
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#define __HAL_I2S_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IF |= (__FLAG__))
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HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
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HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
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void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
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void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
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HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint32_t *pData, uint32_t Size, uint32_t Timeout);
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HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint32_t *pData, uint32_t Size, uint32_t Timeout);
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HAL_StatusTypeDef HAL_I2S_TransmitReceive(I2S_HandleTypeDef *hi2s, uint32_t *pTxData, uint32_t *pRxData,
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uint32_t Size, uint32_t Timeout);
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HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint32_t *pData, uint32_t Size);
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HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *pData, uint32_t Size);
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HAL_StatusTypeDef HAL_I2S_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint32_t *pTxData, uint32_t *pRxData,
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uint32_t Size);
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void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
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HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint32_t *pData, uint32_t Size);
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HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *pData, uint32_t Size);
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HAL_StatusTypeDef HAL_I2S_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *pTxData, uint32_t *pRxData,
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uint32_t Size);
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HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
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HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
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HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
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void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
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void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
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void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
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void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
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void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
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void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
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void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
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HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
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uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
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#endif |