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618 lines
14 KiB
C
618 lines
14 KiB
C
/*!
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* @file system_apm32e10x.c
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*
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File
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*
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* @version V1.0.0
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*
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* @date 2021-07-26
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*
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*/
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#include "apm32e10x.h"
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//#define SYSTEM_CLOCK_HSE HSE_VALUE
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//#define SYSTEM_CLOCK_24MHz (24000000)
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//#define SYSTEM_CLOCK_36MHz (36000000)
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//#define SYSTEM_CLOCK_48MHz (48000000)
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//#define SYSTEM_CLOCK_56MHz (56000000)
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#define SYSTEM_CLOCK_72MHz (72000000)
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//#define SYSTEM_CLOCK_96MHz (96000000)
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//#define SYSTEM_CLOCK_120MHz (120000000)
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00
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#ifdef SYSTEM_CLOCK_HSE
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uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE;
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#elif defined SYSTEM_CLOCK_24MHz
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uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz;
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#elif defined SYSTEM_CLOCK_36MHz
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uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz;
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#elif defined SYSTEM_CLOCK_48MHz
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uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz;
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#elif defined SYSTEM_CLOCK_56MHz
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uint32_t SystemCoreClock = SYSTEM_CLOCK_56MHz;
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#elif defined SYSTEM_CLOCK_72MHz
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uint32_t SystemCoreClock = SYSTEM_CLOCK_72MHz;
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#elif defined SYSTEM_CLOCK_96MHz
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uint32_t SystemCoreClock = SYSTEM_CLOCK_96MHz;
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#else
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uint32_t SystemCoreClock = SYSTEM_CLOCK_120MHz;
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#endif
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static void SystemClockConfig(void);
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#ifdef SYSTEM_CLOCK_HSE
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static void SystemClockHSE(void);
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#elif defined SYSTEM_CLOCK_24MHz
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static void SystemClock24M(void);
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#elif defined SYSTEM_CLOCK_36MHz
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static void SystemClock36M(void);
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#elif defined SYSTEM_CLOCK_48MHz
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static void SystemClock48M(void);
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#elif defined SYSTEM_CLOCK_56MHz
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static void SystemClock56M(void);
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#elif defined SYSTEM_CLOCK_72MHz
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static void SystemClock72M(void);
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#elif defined SYSTEM_CLOCK_96MHz
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static void SystemClock96M(void);
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#elif defined SYSTEM_CLOCK_120MHz
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static void SystemClock120M(void);
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#endif
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/*!
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* @brief Setup the microcontroller system
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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void SystemInit (void)
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{
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/** Set HSIEN bit */
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RCM->CTRL_B.HSIEN = BIT_SET;
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/** Reset SCLKSW, AHBPSC, APB1PSC, APB2PSC, ADCPSC and MCOSEL bits */
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RCM->CFG &= (uint32_t)0xF8FF0000;
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/** Reset HSEEN, CSSEN and PLLEN bits */
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RCM->CTRL &= (uint32_t)0xFEF6FFFF;
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/** Reset HSEBCFG bit */
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RCM->CTRL_B.HSEBCFG = BIT_RESET;
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/** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG and USBDIV bits */
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RCM->CFG &= (uint32_t)0xFF80FFFF;
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/** Disable all interrupts and clear pending bits */
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RCM->INT = 0x009F0000;
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SystemClockConfig();
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
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#else
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SCB->VTOR = FMC_BASE | VECT_TAB_OFFSET;
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#endif
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}
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/*!
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* @brief Update SystemCoreClock variable according to Clock Register Values
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* The SystemCoreClock variable contains the core clock (HCLK)
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t sysClock, pllMull, pllSource, Prescaler;
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uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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sysClock = RCM->CFG_B.SCLKSWSTS;
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switch(sysClock)
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{
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/** sys clock is HSI */
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case 0:
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SystemCoreClock = HSI_VALUE;
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break;
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/** sys clock is HSE */
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case 1:
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SystemCoreClock = HSE_VALUE;
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break;
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/** sys clock is PLL */
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case 2:
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pllMull = RCM->CFG_B.PLLMULCFG + 2;
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pllSource = RCM->CFG_B.PLLSRCSEL;
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/** PLL entry clock source is HSE */
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if(pllSource == BIT_SET)
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{
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SystemCoreClock = HSE_VALUE * pllMull;
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/** HSE clock divided by 2 */
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if(pllSource == RCM->CFG_B.PLLHSEPSC)
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{
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SystemCoreClock >>= 1;
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}
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}
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/** PLL entry clock source is HSI/2 */
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else
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{
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SystemCoreClock = (HSI_VALUE >> 1) * pllMull;
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}
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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Prescaler = AHBPrescTable[RCM->CFG_B.AHBPSC];
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SystemCoreClock >>= Prescaler;
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}
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/*!
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClockConfig(void)
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{
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#ifdef SYSTEM_CLOCK_HSE
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SystemClockHSE();
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#elif defined SYSTEM_CLOCK_24MHz
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SystemClock24M();
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#elif defined SYSTEM_CLOCK_36MHz
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SystemClock36M();
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#elif defined SYSTEM_CLOCK_48MHz
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SystemClock48M();
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#elif defined SYSTEM_CLOCK_56MHz
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SystemClock56M();
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#elif defined SYSTEM_CLOCK_72MHz
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SystemClock72M();
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#elif defined SYSTEM_CLOCK_96MHz
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SystemClock96M();
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#elif defined SYSTEM_CLOCK_120MHz
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SystemClock120M();
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#endif
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}
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#if defined SYSTEM_CLOCK_HSE
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/*!
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* @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClockHSE(void)
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{
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__IO uint32_t i;
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RCM->CTRL_B.HSEEN= BIT_SET;
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for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if(RCM->CTRL_B.HSERDYFLG)
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{
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break;
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}
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}
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if(RCM->CTRL_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 0 wait state */
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FMC->CTRL1_B.WS = 0;
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/* HCLK = SYSCLK */
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RCM->CFG_B.AHBPSC= 0X00;
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/* PCLK2 = HCLK */
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RCM->CFG_B.APB2PSC= 0;
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/* PCLK1 = HCLK */
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RCM->CFG_B.APB1PSC = 0;
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/* Select HSE as system clock source */
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RCM->CFG_B.SCLKSW = 1;
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/** Wait till HSE is used as system clock source */
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while(RCM->CFG_B.SCLKSWSTS!= 0x01);
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}
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}
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#elif defined SYSTEM_CLOCK_24MHz
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/*!
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* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClock24M(void)
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{
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__IO uint32_t i;
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RCM->CTRL_B.HSEEN= BIT_SET;
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for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if(RCM->CTRL_B.HSERDYFLG)
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{
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break;
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}
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}
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if(RCM->CTRL_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 0 wait state */
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FMC->CTRL1_B.WS = 0;
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/* HCLK = SYSCLK */
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RCM->CFG_B.AHBPSC= 0X00;
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/* PCLK2 = HCLK */
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RCM->CFG_B.APB2PSC= 0;
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/* PCLK1 = HCLK */
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RCM->CFG_B.APB1PSC = 0;
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/** PLL: (HSE / 2) * 6 */
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RCM->CFG_B.PLLSRCSEL = 1;
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RCM->CFG_B.PLLHSEPSC = 1;
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RCM->CFG_B.PLLMULCFG = 4;
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/** Enable PLL */
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RCM->CTRL_B.PLLEN = 1;
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/** Wait PLL Ready */
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while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
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/* Select PLL as system clock source */
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RCM->CFG_B.SCLKSW = 2;
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/* Wait till PLL is used as system clock source */
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while(RCM->CFG_B.SCLKSWSTS!= 0x02);
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}
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}
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#elif defined SYSTEM_CLOCK_36MHz
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/*!
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* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClock36M(void)
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{
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__IO uint32_t i;
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RCM->CTRL_B.HSEEN= BIT_SET;
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for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if(RCM->CTRL_B.HSERDYFLG)
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{
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break;
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}
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}
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if(RCM->CTRL_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 1 wait state */
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FMC->CTRL1_B.WS = 1;
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/* HCLK = SYSCLK */
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RCM->CFG_B.AHBPSC= 0X00;
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/* PCLK2 = HCLK */
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RCM->CFG_B.APB2PSC= 0;
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/* PCLK1 = HCLK */
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RCM->CFG_B.APB1PSC = 0;
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/** PLL: (HSE / 2) * 9 */
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RCM->CFG_B.PLLSRCSEL = 1;
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RCM->CFG_B.PLLHSEPSC = 1;
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RCM->CFG_B.PLLMULCFG = 7;
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/** Enable PLL */
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RCM->CTRL_B.PLLEN = 1;
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/** Wait PLL Ready */
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while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
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/* Select PLL as system clock source */
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RCM->CFG_B.SCLKSW = 2;
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/* Wait till PLL is used as system clock source */
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while(RCM->CFG_B.SCLKSWSTS != 0x02);
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}
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}
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#elif defined SYSTEM_CLOCK_48MHz
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/*!
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* @brief Sets System clock frequency to 46MHz and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClock48M(void)
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{
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__IO uint32_t i;
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RCM->CTRL_B.HSEEN= BIT_SET;
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for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if(RCM->CTRL_B.HSERDYFLG)
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{
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break;
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}
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}
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if(RCM->CTRL_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 1 wait state */
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FMC->CTRL1_B.WS = 1;
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/* HCLK = SYSCLK */
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RCM->CFG_B.AHBPSC= 0X00;
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/* PCLK2 = HCLK */
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RCM->CFG_B.APB2PSC= 0;
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/* PCLK1 = HCLK / 2 */
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RCM->CFG_B.APB1PSC = 4;
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/** PLL: HSE * 6 */
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RCM->CFG_B.PLLSRCSEL = 1;
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RCM->CFG_B.PLLMULCFG = 4;
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/** Enable PLL */
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RCM->CTRL_B.PLLEN = 1;
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/** Wait PLL Ready */
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while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
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/* Select PLL as system clock source */
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RCM->CFG_B.SCLKSW = 2;
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/* Wait till PLL is used as system clock source */
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while(RCM->CFG_B.SCLKSWSTS!= 0x02);
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}
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}
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#elif defined SYSTEM_CLOCK_56MHz
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/*!
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* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClock56M(void)
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{
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__IO uint32_t i;
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RCM->CTRL_B.HSEEN= BIT_SET;
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for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if(RCM->CTRL_B.HSERDYFLG)
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{
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break;
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}
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}
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if(RCM->CTRL_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 2 wait state */
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FMC->CTRL1_B.WS = 2;
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/* HCLK = SYSCLK */
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RCM->CFG_B.AHBPSC= 0X00;
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/* PCLK2 = HCLK */
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RCM->CFG_B.APB2PSC= 0;
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/* PCLK1 = HCLK / 2 */
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RCM->CFG_B.APB1PSC = 4;
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/** PLL: HSE * 7 */
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RCM->CFG_B.PLLSRCSEL = 1;
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RCM->CFG_B.PLLMULCFG = 5;
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/** Enable PLL */
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RCM->CTRL_B.PLLEN = 1;
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/** Wait PLL Ready */
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while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
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/* Select PLL as system clock source */
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RCM->CFG_B.SCLKSW = 2;
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/* Wait till PLL is used as system clock source */
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while(RCM->CFG_B.SCLKSWSTS!= 0x02);
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}
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}
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#elif defined SYSTEM_CLOCK_72MHz
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/*!
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* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClock72M(void)
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{
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__IO uint32_t i;
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RCM->CTRL_B.HSEEN= BIT_SET;
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for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if(RCM->CTRL_B.HSERDYFLG)
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{
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break;
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}
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}
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if(RCM->CTRL_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 2 wait state */
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FMC->CTRL1_B.WS = 2;
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/* HCLK = SYSCLK */
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RCM->CFG_B.AHBPSC= 0X00;
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/* PCLK2 = HCLK */
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RCM->CFG_B.APB2PSC= 0;
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/* PCLK1 = HCLK / 2 */
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RCM->CFG_B.APB1PSC = 4;
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/** PLL: HSE * 9 */
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RCM->CFG_B.PLLSRCSEL = 1;
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RCM->CFG_B.PLLMULCFG = 7;
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/** Enable PLL */
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RCM->CTRL_B.PLLEN = 1;
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/** Wait PLL Ready */
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while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
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/* Select PLL as system clock source */
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RCM->CFG_B.SCLKSW = 2;
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/* Wait till PLL is used as system clock source */
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while(RCM->CFG_B.SCLKSWSTS!= 0x02);
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}
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}
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#elif defined SYSTEM_CLOCK_96MHz
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/*!
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* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClock96M(void)
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{
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__IO uint32_t i;
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RCM->CTRL_B.HSEEN= BIT_SET;
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for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if(RCM->CTRL_B.HSERDYFLG)
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{
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break;
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}
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}
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if(RCM->CTRL_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 3 wait state */
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FMC->CTRL1_B.WS = 3;
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/* HCLK = SYSCLK */
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RCM->CFG_B.AHBPSC= 0X00;
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/* PCLK2 = HCLK */
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RCM->CFG_B.APB2PSC= 0;
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/* PCLK1 = HCLK / 2 */
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RCM->CFG_B.APB1PSC = 4;
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/** PLL: HSE * 12 */
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RCM->CFG_B.PLLSRCSEL = 1;
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RCM->CFG_B.PLLMULCFG = 10;
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/** Enable PLL */
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RCM->CTRL_B.PLLEN = 1;
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/** Wait PLL Ready */
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while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
|
|
|
|
/* Select PLL as system clock source */
|
|
RCM->CFG_B.SCLKSW = 2;
|
|
/* Wait till PLL is used as system clock source */
|
|
while(RCM->CFG_B.SCLKSWSTS!= 0x02);
|
|
}
|
|
}
|
|
|
|
#elif defined SYSTEM_CLOCK_120MHz
|
|
/*!
|
|
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers
|
|
*
|
|
* @param None
|
|
*
|
|
* @retval None
|
|
*
|
|
* @note
|
|
*/
|
|
static void SystemClock120M(void)
|
|
{
|
|
__IO uint32_t i;
|
|
|
|
RCM->CTRL_B.HSEEN= BIT_SET;
|
|
|
|
for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
|
|
{
|
|
if(RCM->CTRL_B.HSERDYFLG)
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
|
|
if(RCM->CTRL_B.HSERDYFLG)
|
|
{
|
|
/* Enable Prefetch Buffer */
|
|
FMC->CTRL1_B.PBEN = BIT_SET;
|
|
/* Flash 3 wait state */
|
|
FMC->CTRL1_B.WS = 3;
|
|
|
|
/* HCLK = SYSCLK */
|
|
RCM->CFG_B.AHBPSC= 0X00;
|
|
/* PCLK2 = HCLK */
|
|
RCM->CFG_B.APB2PSC= 0;
|
|
/* PCLK1 = HCLK / 2 */
|
|
RCM->CFG_B.APB1PSC = 4;
|
|
|
|
/** PLL: HSE * 15 */
|
|
RCM->CFG_B.PLLSRCSEL = 1;
|
|
RCM->CFG_B.PLLMULCFG = 13;
|
|
|
|
/** Enable PLL */
|
|
RCM->CTRL_B.PLLEN = 1;
|
|
/** Wait PLL Ready */
|
|
while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
|
|
|
|
/* Select PLL as system clock source */
|
|
RCM->CFG_B.SCLKSW = 2;
|
|
/* Wait till PLL is used as system clock source */
|
|
while(RCM->CFG_B.SCLKSWSTS!= 0x02);
|
|
}
|
|
}
|
|
#endif
|
|
|