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356 lines
8.2 KiB
C
356 lines
8.2 KiB
C
/*!
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* @file apm32e10x_emmc.h
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*
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* @brief This file contains all the functions prototypes for the EMMC firmware library
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*
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* @version V1.0.0
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*
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* @date 2021-07-26
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*
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*/
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#ifndef __APM32E10X_EMMC_H
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#define __APM32E10X_EMMC_H
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#include "apm32e10x.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup Peripherals_Library Standard Peripheral Library
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@{
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*/
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/** @addtogroup EMMC_Driver EMMC Driver
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@{
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*/
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/** @addtogroup EMMC_Enumerations Enumerations
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@{
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*/
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/**
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* @brief EMMC NORSRAM_Bank
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*/
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typedef enum
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{
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EMMC_BANK1_NORSRAM_1 = 0x00000000,
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EMMC_BANK1_NORSRAM_2 = 0x00000002,
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EMMC_BANK1_NORSRAM_3 = 0x00000004,
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EMMC_BANK1_NORSRAM_4 = 0x00000006
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} EMMC_BANK1_NORSRAM_T;
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/**
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* @brief EMMC NAND and PC Card Bank
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*/
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typedef enum
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{
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EMMC_BANK2_NAND = 0x00000010,
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EMMC_BANK3_NAND = 0x00000100,
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EMMC_BANK4_PCCARD = 0x00001000
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} EMMC_BANK_NAND_T;
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/**
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* @brief EMMC_Data_Address_Bus_Multiplexing
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*/
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typedef enum
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{
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EMMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000,
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EMMC_DATA_ADDRESS_MUX_ENABLE = 0x00000002
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} EMMC_DATA_ADDRESS_MUX_T;
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/**
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* @brief EMMC_Memory_Type
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*/
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typedef enum
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{
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EMMC_MEMORY_TYPE_SRAM = 0x00000000,
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EMMC_MEMORY_TYPE_PSRAM = 0x00000004,
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EMMC_MEMORY_TYPE_NOR = 0x00000008
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} EMMC_MEMORY_TYPE_T;
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/**
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* @brief EMMC_Data_Width
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*/
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typedef enum
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{
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EMMC_MEMORY_DATA_WIDTH_8BIT = 0x00000000,
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EMMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010
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} EMMC_MEMORY_DATA_WIDTH_T;
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/**
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* @brief EMMC_Burst_Access_Mode
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*/
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typedef enum
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{
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EMMC_BURST_ACCESS_MODE_DISABLE = 0x00000000,
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EMMC_BURST_ACCESS_MODE_ENABLE = 0x00000100
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} EMMC_BURST_ACCESS_MODE_T;
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/**
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* @brief EMMC_AsynchronousWait
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*/
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typedef enum
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{
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EMMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000,
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EMMC_ASYNCHRONOUS_WAIT_ENABLE = 0x00008000
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} EMMC_ASYNCHRONOUS_WAIT_T;
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/**
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* @brief EMMC_Wait_Signal_Polarity
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*/
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typedef enum
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{
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EMMC_WAIT_SIGNAL_POLARITY_LOW = 0x00000000,
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EMMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200
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} EMMC_WAIT_SIGNAL_POLARITY_T;
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/**
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* @brief EMMC_Wrap_Mode
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*/
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typedef enum
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{
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EMMC_WRAP_MODE_DISABLE = 0x00000000,
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EMMC_WRAP_MODE_ENABLE = 0x00000400
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} EMMC_WRAP_MODE_T;
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/**
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* @brief EMMC_Wait_Timing
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*/
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typedef enum
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{
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EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000,
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EMMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800
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} EMMC_WAIT_SIGNAL_ACTIVE_T;
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/**
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* @brief EMMC_Write_Operation
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*/
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typedef enum
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{
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EMMC_WRITE_OPERATION_DISABLE = 0x00000000,
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EMMC_WRITE_OPERATION_ENABLE = 0x00001000
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} EMMC_WRITE_OPERATION_T;
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/**
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* @brief EMMC_Wait_Signal
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*/
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typedef enum
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{
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EMMC_WAITE_SIGNAL_DISABLE = 0x00000000,
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EMMC_WAITE_SIGNAL_ENABLE = 0x00002000
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} EMMC_WAITE_SIGNAL_T;
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/**
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* @brief EMMC_Extended_Mode
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*/
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typedef enum
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{
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EMMC_EXTENDEN_MODE_DISABLE = 0x00000000,
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EMMC_EXTENDEN_MODE_ENABLE = 0x00004000
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} EMMC_EXTENDEN_MODE_T;
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/**
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* @brief EMMC_Write_Burst
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*/
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typedef enum
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{
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EMMC_WRITE_BURST_DISABLE = 0x00000000,
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EMMC_WRITE_BURST_ENABLE = 0x00080000
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} EMMC_WRITE_BURST_T;
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/**
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* @brief EMMC_WAIT_FEATURE
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*/
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typedef enum
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{
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EMMC_WAIT_FEATURE_DISABLE = 0x00000000,
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EMMC_WAIT_FEATURE_ENABLE = 0x00000002
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} EMMC_WAIT_FEATURE_T;
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/**
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* @brief EMMC_ECC
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*/
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typedef enum
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{
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EMMC_ECC_DISABLE = 0x00000000,
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EMMC_ECC_ENABLE = 0x00000040
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} EMMC_ECC_T;
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/**
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* @brief EMMC_ECC_Page_Size
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*/
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typedef enum
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{
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EMMC_ECC_PAGE_SIZE_BYTE_256 = 0x00000000,
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EMMC_ECC_PAGE_SIZE_BYTE_512 = 0x00020000,
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EMMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000,
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EMMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000,
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EMMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000,
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EMMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000
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} EMMC_ECC_PAGE_SIZE_BYTE_T;
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/**
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* @brief EMMC_Access_Mode
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*/
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typedef enum
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{
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EMMC_ACCESS_MODE_A = 0x00000000,
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EMMC_ACCESS_MODE_B = 0x10000000,
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EMMC_ACCESS_MODE_C = 0x20000000,
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EMMC_ACCESS_MODE_D = 0x30000000
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} EMMC_ACCESS_MODE_T;
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/**
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* @brief EMMC_Interrupt_sources
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*/
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typedef enum
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{
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EMMC_INT_EDGE_RISING = 0x00000008,
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EMMC_INT_LEVEL_HIGH = 0x00000010,
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EMMC_INT_EDGE_FALLING = 0x00000020
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} EMMC_INT_T;
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/**
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* @brief EMMC_Flags
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*/
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typedef enum
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{
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EMMC_FLAG_EDGE_RISING = 0x00000001,
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EMMC_FLAG_LEVEL_HIGH = 0x00000002,
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EMMC_FLAG_EDGE_FALLING = 0x00000004,
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EMMC_FLAG_FIFO_EMPTY = 0x00000040
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} EMMC_FLAG_T;
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/**@} end of group EMMC_Enumerations*/
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/** @addtogroup EMMC_Structure Data Structure
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@{
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*/
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/**
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* @brief Timing parameters for NOR/SRAM Banks
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*/
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typedef struct
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{
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uint32_t addressSetupTime;
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uint32_t addressHodeTime;
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uint32_t dataSetupTime;
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uint32_t busTurnaroundTime;
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uint32_t clockDivision;
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uint32_t dataLatency;
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EMMC_ACCESS_MODE_T accessMode;
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} EMMC_NORSRAMTimingConfig_T;
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/**
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* @brief EMMC NOR/SRAM Config structure
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*/
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typedef struct
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{
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EMMC_BANK1_NORSRAM_T bank;
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EMMC_DATA_ADDRESS_MUX_T dataAddressMux;
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EMMC_MEMORY_TYPE_T memoryType;
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EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth;
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EMMC_BURST_ACCESS_MODE_T burstAcceesMode;
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EMMC_ASYNCHRONOUS_WAIT_T asynchronousWait;
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EMMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity;
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EMMC_WRAP_MODE_T wrapMode;
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EMMC_WAIT_SIGNAL_ACTIVE_T waitSignalActive;
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EMMC_WRITE_OPERATION_T writeOperation;
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EMMC_WAITE_SIGNAL_T waiteSignal;
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EMMC_EXTENDEN_MODE_T extendedMode;
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EMMC_WRITE_BURST_T writeBurst;
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EMMC_NORSRAMTimingConfig_T* readWriteTimingStruct;
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EMMC_NORSRAMTimingConfig_T* writeTimingStruct;
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} EMMC_NORSRAMConfig_T;
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/**
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* @brief Timing parameters for NAND and PCCARD Banks
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*/
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typedef struct
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{
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uint32_t setupTime;
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uint32_t waitSetupTime;
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uint32_t holdSetupTime;
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uint32_t HiZSetupTime;
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} EMMC_NAND_PCCARDTimingConfig_T;
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/**
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* @brief EMMC NAND Config structure
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*/
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typedef struct
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{
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EMMC_BANK_NAND_T bank;
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EMMC_WAIT_FEATURE_T waitFeature;
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EMMC_MEMORY_DATA_WIDTH_T memoryDataWidth;
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EMMC_ECC_T ECC;
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EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
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uint32_t TCLRSetupTime;
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uint32_t TARSetupTime;
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EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
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EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
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} EMMC_NANDConfig_T;
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/**
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* @brief EMMC PCCARD Config structure
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*/
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typedef struct
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{
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EMMC_WAIT_FEATURE_T waitFeature;
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uint32_t TCLRSetupTime;
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uint32_t TARSetupTime;
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EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
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EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
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EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
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} EMMC_PCCARDConfig_T;
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/**@} end of group EMMC_Structure*/
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/** @addtogroup EMMC_Fuctions Fuctions
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@{
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*/
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/** EMMC reset */
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void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank);
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void EMMC_ResetNAND(EMMC_BANK_NAND_T bank);
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void EMMC_ResetPCCard(void);
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/** EMMC Configuration */
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void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
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void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig);
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void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig);
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void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
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void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig);
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void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig);
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/** EMMC bank control */
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void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
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void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
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void EMMC_EnableNAND(EMMC_BANK_NAND_T bank);
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void EMMC_DisableNAND(EMMC_BANK_NAND_T bank);
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void EMMC_EnablePCCARD(void);
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void EMMC_DisablePCCARD(void);
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void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank);
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void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank);
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uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank);
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/** Interrupt and flag */
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void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
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void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
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uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag);
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void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
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uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag);
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void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
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/**@} end of group EMMC_Fuctions*/
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/**@} end of group EMMC_Driver */
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/**@} end of group Peripherals_Library*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __APM32E10X_EMMC_H */
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