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366 lines
7.9 KiB
C
366 lines
7.9 KiB
C
/*!
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* @file apm32e10x_rcm.h
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*
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* @brief This file contains all the functions prototypes for the RCM firmware library
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*
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* @version V1.0.0
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*
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* @date 2021-07-26
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*
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*/
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#ifndef __APM32E10X_RCM_H
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#define __APM32E10X_RCM_H
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#include "apm32e10x.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup Peripherals_Library Standard Peripheral Library
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@{
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*/
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/** @addtogroup RCM_Driver RCM Driver
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@{
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*/
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/** @addtogroup RCM_Enumerations Enumerations
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@{
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*/
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/**
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* @brief HSE state
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*/
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typedef enum
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{
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RCM_HSE_CLOSE, //!< CLOSE HSE
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RCM_HSE_OPEN, //!< OPEN HSE
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RCM_HSE_BYPASS, //!< HSE BYPASS
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} RCM_HSE_T;
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/**
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* @brief PLL multiplication factor
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*/
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typedef enum
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{
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RCM_PLLMF_2,
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RCM_PLLMF_3,
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RCM_PLLMF_4,
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RCM_PLLMF_5,
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RCM_PLLMF_6,
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RCM_PLLMF_7,
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RCM_PLLMF_8,
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RCM_PLLMF_9,
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RCM_PLLMF_10,
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RCM_PLLMF_11,
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RCM_PLLMF_12,
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RCM_PLLMF_13,
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RCM_PLLMF_14,
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RCM_PLLMF_15,
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RCM_PLLMF_16,
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} RCM_PLLMF_T;
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/**
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* @brief System clock select
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*/
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typedef enum
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{
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RCM_SYSCLK_SEL_HSI,
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RCM_SYSCLK_SEL_HSE,
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RCM_SYSCLK_SEL_PLL
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} RCM_SYSCLK_SEL_T;
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/**
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* @brief AHB divider Number
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*/
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typedef enum
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{
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RCM_AHB_DIV_1 = 7,
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RCM_AHB_DIV_2,
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RCM_AHB_DIV_4,
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RCM_AHB_DIV_8,
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RCM_AHB_DIV_16,
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RCM_AHB_DIV_64,
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RCM_AHB_DIV_128,
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RCM_AHB_DIV_256,
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RCM_AHB_DIV_512,
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} RCM_AHB_DIV_T;
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/**
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* @brief APB divider Number
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*/
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typedef enum
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{
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RCM_APB_DIV_1 = 3,
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RCM_APB_DIV_2,
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RCM_APB_DIV_4,
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RCM_APB_DIV_8,
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RCM_APB_DIV_16
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} RCM_APB_DIV_T;
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/**
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* @brief USB divider Number
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*/
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typedef enum
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{
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RCM_USB_DIV_1_5,
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RCM_USB_DIV_1,
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RCM_USB_DIV_2,
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RCM_USB_DIV_2_5
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} RCM_USB_DIV_T;
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/**
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* @brief FPU divider Number
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*/
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typedef enum
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{
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RCM_FPU_DIV_1,
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RCM_FPU_DIV_2,
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} RCM_FPU_DIV_T;
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/**
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* @brief ADC divider Number
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*/
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typedef enum
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{
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RCM_PCLK2_DIV_2,
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RCM_PCLK2_DIV_4,
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RCM_PCLK2_DIV_6,
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RCM_PCLK2_DIV_8,
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} RCM_PCLK2_DIV_T;
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/**
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* @brief LSE State
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*/
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typedef enum
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{
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RCM_LSE_CLOSE,
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RCM_LSE_OPEN,
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RCM_LSE_BYPASS
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} RCM_LSE_T;
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/**
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* @brief RTC clock select
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*/
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typedef enum
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{
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RCM_RTCCLK_LSE = 1,
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RCM_RTCCLK_LSI,
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RCM_RTCCLK_HSE_DIV_128
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} RCM_RTCCLK_T;
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/**
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* @brief Clock output control
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*/
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typedef enum
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{
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RCM_MCOCLK_NO_CLOCK = 3,
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RCM_MCOCLK_SYSCLK,
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RCM_MCOCLK_HSI,
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RCM_MCOCLK_HSE,
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RCM_MCOCLK_PLLCLK_DIV_2,
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} RCM_MCOCLK_T;
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/**
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* @brief PLL entry clock select
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*/
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typedef enum
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{
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RCM_PLLSEL_HSI_DIV_2 = 0,
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RCM_PLLSEL_HSE = 1,
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RCM_PLLSEL_HSE_DIV2 = 3,
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} RCM_PLLSEL_T;
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/**
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* @brief RCM Interrupt Source
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*/
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typedef enum
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{
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RCM_INT_LSIRDY = BIT0, //!< LSI ready interrupt
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RCM_INT_LSERDY = BIT1, //!< LSE ready interrupt
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RCM_INT_HSIRDY = BIT2, //!< HSI ready interrupt
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RCM_INT_HSERDY = BIT3, //!< HSE ready interrupt
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RCM_INT_PLLRDY = BIT4, //!< PLL ready interrupt
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RCM_INT_CSS = BIT7 //!< Clock security system interrupt
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} RCM_INT_T;
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/**
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* @brief AHB peripheral
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*/
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typedef enum
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{
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RCM_AHB_PERIPH_DMA1 = BIT0,
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RCM_AHB_PERIPH_DMA2 = BIT1,
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RCM_AHB_PERIPH_SRAM = BIT2,
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RCM_AHB_PERIPH_FPU = BIT3,
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RCM_AHB_PERIPH_FMC = BIT4,
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RCM_AHB_PERIPH_QSPI = BIT5,
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RCM_AHB_PERIPH_CRC = BIT6,
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RCM_AHB_PERIPH_EMMC = BIT8,
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RCM_AHB_PERIPH_SDIO = BIT10,
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} RCM_AHB_PERIPH_T;
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/**
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* @brief AHB2 peripheral
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*/
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typedef enum
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{
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RCM_APB2_PERIPH_AFIO = BIT0,
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RCM_APB2_PERIPH_GPIOA = BIT2,
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RCM_APB2_PERIPH_GPIOB = BIT3,
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RCM_APB2_PERIPH_GPIOC = BIT4,
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RCM_APB2_PERIPH_GPIOD = BIT5,
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RCM_APB2_PERIPH_GPIOE = BIT6,
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RCM_APB2_PERIPH_GPIOF = BIT7,
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RCM_APB2_PERIPH_GPIOG = BIT8,
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RCM_APB2_PERIPH_ADC1 = BIT9,
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RCM_APB2_PERIPH_ADC2 = BIT10,
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RCM_APB2_PERIPH_TMR1 = BIT11,
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RCM_APB2_PERIPH_SPI1 = BIT12,
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RCM_APB2_PERIPH_TMR8 = BIT13,
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RCM_APB2_PERIPH_USART1 = BIT14,
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RCM_APB2_PERIPH_ADC3 = BIT15,
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} RCM_APB2_PERIPH_T;
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/**
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* @brief AHB1 peripheral
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*/
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typedef enum
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{
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RCM_APB1_PERIPH_TMR2 = BIT0,
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RCM_APB1_PERIPH_TMR3 = BIT1,
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RCM_APB1_PERIPH_TMR4 = BIT2,
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RCM_APB1_PERIPH_TMR5 = BIT3,
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RCM_APB1_PERIPH_TMR6 = BIT4,
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RCM_APB1_PERIPH_TMR7 = BIT5,
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RCM_APB1_PERIPH_WWDT = BIT11,
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RCM_APB1_PERIPH_SPI2 = BIT14,
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RCM_APB1_PERIPH_SPI3 = BIT15,
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RCM_APB1_PERIPH_USART2 = BIT17,
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RCM_APB1_PERIPH_USART3 = BIT18,
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RCM_APB1_PERIPH_UART4 = BIT19,
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RCM_APB1_PERIPH_UART5 = BIT20,
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RCM_APB1_PERIPH_I2C1 = BIT21,
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RCM_APB1_PERIPH_I2C2 = BIT22,
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RCM_APB1_PERIPH_USB = BIT23,
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RCM_APB1_PERIPH_CAN1 = BIT25,
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RCM_APB1_PERIPH_CAN2 = BIT26,
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RCM_APB1_PERIPH_BAKR = BIT27,
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RCM_APB1_PERIPH_PMU = BIT28,
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RCM_APB1_PERIPH_DAC = BIT29,
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} RCM_APB1_PERIPH_T;
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/**
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* @brief RCM FLAG define
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*/
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typedef enum
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{
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RCM_FLAG_HSIRDY = 0x001, //!< HSI Ready Flag
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RCM_FLAG_HSERDY = 0x011, //!< HSE Ready Flag
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RCM_FLAG_PLLRDY = 0x019, //!< PLL Ready Flag
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RCM_FLAG_LSERDY = 0x101, //!< LSE Ready Flag
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RCM_FLAG_LSIRDY = 0x201, //!< LSI Ready Flag
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RCM_FLAG_PINRST = 0x21A, //!< PIN reset flag
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RCM_FLAG_PORRST = 0x21B, //!< POR/PDR reset flag
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RCM_FLAG_SWRST = 0x21C, //!< Software reset flag
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RCM_FLAG_IWDTRST = 0x21D, //!< Independent watchdog reset flag
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RCM_FLAG_WWDTRST = 0x21E, //!< Window watchdog reset flag
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RCM_FLAG_LPRRST = 0x21F, //!< Low-power reset flag
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} RCM_FLAG_T;
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/**@} end of group RCM_Enumerations*/
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/** @addtogroup RCM_Fuctions Fuctions
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@{
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*/
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/** Function description */
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/** RCM Reset */
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void RCM_Reset(void);
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/** HSE clock */
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void RCM_ConfigHSE(RCM_HSE_T state);
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uint8_t RCM_WaitHSEReady(void);
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/** HSI clock */
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void RCM_SetHSITrim(uint8_t HSITrim);
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void RCM_EnableHSI(void);
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void RCM_DisableHSI(void);
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/** LSE and LSI clock */
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void RCM_ConfigLSE(RCM_LSE_T state);
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void RCM_EnableLSI(void);
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void RCM_DisableLSI(void);
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/** PLL clock */
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void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf);
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void RCM_EnablePLL(void);
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void RCM_DisablePLL(void);
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/** Clock Security System */
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void RCM_EnableCSS(void);
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void RCM_DisableCSS(void);
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void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock);
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void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect);
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RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void);
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/** Config clock prescaler of AHB, APB1, APB2, USB and ADC */
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void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv);
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void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div);
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void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div);
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void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv);
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void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv);
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void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv);
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/** RTC clock */
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void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect);
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void RCM_EnableRTCCLK(void);
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void RCM_DisableRTCCLK(void);
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/** Reads the clock frequency */
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uint32_t RCM_ReadSYSCLKFreq(void);
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uint32_t RCM_ReadHCLKFreq(void);
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void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2);
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uint32_t RCM_ReadADCCLKFreq(void);
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/** Enable or disable Periph Clock */
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void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph);
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void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph);
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void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph);
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void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph);
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void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph);
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void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph);
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/** Enable or disable Periph Reset */
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void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph);
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void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph);
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void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph);
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void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph);
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/** Backup domain reset */
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void RCM_EnableBackupReset(void);
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void RCM_DisableBackupReset(void);
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/** Interrupts and flags */
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void RCM_EnableInterrupt(uint32_t interrupt);
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void RCM_DisableInterrupt(uint32_t interrupt);
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uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag);
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void RCM_ClearStatusFlag(void);
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uint8_t RCM_ReadIntFlag(RCM_INT_T flag);
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void RCM_ClearIntFlag(uint32_t flag);
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/**@} end of group RCM_Fuctions*/
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/**@} end of group RCM_Driver*/
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/**@} end of group Peripherals_Library*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __APM32E10X_RCM_H */
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