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660 lines
17 KiB
C
660 lines
17 KiB
C
/*!
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* @file apm32e10x_tmr.h
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*
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* @brief This file contains all the functions prototypes for the TMR firmware library.
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*
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* @version V1.0.0
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*
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* @date 2021-07-26
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*
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*/
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#ifndef __APM32E10X_TMR_H
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#define __APM32E10X_TMR_H
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#include "apm32e10x.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup Peripherals_Library Standard Peripheral Library
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@{
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*/
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/** @addtogroup TMR_Driver TMR Driver
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@{
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*/
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/** @addtogroup TMR_Enumerations Enumerations
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@{
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*/
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/**
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* @brief TMR Counter Mode
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*/
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typedef enum
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{
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TMR_COUNTER_MODE_UP = 0x0000,
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TMR_COUNTER_MODE_DOWN = 0x0010,
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TMR_COUNTER_MODE_CENTERALIGNED1 = 0x0020,
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TMR_COUNTER_MODE_CENTERALIGNED2 = 0x0040,
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TMR_COUNTER_MODE_CENTERALIGNED3 = 0x0060
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} TMR_COUNTER_MODE_T;
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/**
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* @brief TMR Clock division
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*/
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typedef enum
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{
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TMR_CLOCK_DIV_1,
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TMR_CLOCK_DIV_2,
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TMR_CLOCK_DIV_4
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} TMR_CLOCK_DIV_T;
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/**
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* @brief TMR Output Compare and PWM modes
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*/
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typedef enum
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{
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TMR_OC_MODE_TMRING = 0x00,
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TMR_OC_MODE_ACTIVE = 0x01,
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TMR_OC_MODE_INACTIVE = 0x02,
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TMR_OC_MODE_TOGGEL = 0x03,
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TMR_OC_MODE_LOWLEVEL = 0x04,
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TMR_OC_MODE_HIGHLEVEL = 0x05,
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TMR_OC_MODE_PWM1 = 0x06,
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TMR_OC_MODE_PWM2 = 0x07,
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} TMR_OC_MODE_T;
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/**
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* @brief TMR Output Compare state
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*/
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typedef enum
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{
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TMR_OC_STATE_DISABLE,
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TMR_OC_STATE_ENABLE
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} TMR_OC_STATE_T;
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/**
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* @brief TMR Output Compare N state
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*/
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typedef enum
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{
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TMR_OC_NSTATE_DISABLE,
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TMR_OC_NSTATE_ENABLE
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} TMR_OC_NSTATE_T;
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/**
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* @brief TMR Output Compare Polarity
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*/
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typedef enum
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{
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TMR_OC_POLARITY_HIGH,
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TMR_OC_POLARITY_LOW
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} TMR_OC_POLARITY_T;
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/**
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* @brief TMR Output Compare N Polarity
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*/
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typedef enum
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{
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TMR_OC_NPOLARITY_HIGH,
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TMR_OC_NPOLARITY_LOW
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} TMR_OC_NPOLARITY_T;
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/**
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* @brief TMR Output Compare Idle State
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*/
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typedef enum
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{
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TMR_OC_IDLE_STATE_RESET,
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TMR_OC_IDLE_STATE_SET
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} TMR_OC_IDLE_STATE_T;
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/**
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* @brief TMR Output Compare N Idle State
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*/
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typedef enum
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{
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TMR_OC_NIDLE_STATE_RESET,
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TMR_OC_NIDLE_STATE_SET
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} TMR_OC_NIDLE_STATE_T;
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/**
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* @brief TMR Input Capture Init structure definition
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*/
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typedef enum
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{
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TMR_CHANNEL_1 = 0x0000,
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TMR_CHANNEL_2 = 0x0004,
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TMR_CHANNEL_3 = 0x0008,
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TMR_CHANNEL_4 = 0x000C
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} TMR_CHANNEL_T;
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/**
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* @brief TMR Input Capture Polarity
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*/
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typedef enum
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{
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TMR_IC_POLARITY_RISING = 0x00,
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TMR_IC_POLARITY_FALLING = 0x02,
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TMR_IC_POLARITY_BOTHEDGE = 0x0A
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} TMR_IC_POLARITY_T;
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/**
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* @brief TMR Input Capture Selection
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*/
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typedef enum
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{
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TMR_IC_SELECTION_DIRECT_TI = 0x01,
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TMR_IC_SELECTION_INDIRECT_TI = 0x02,
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TMR_IC_SELECTION_TRC = 0x03
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} TMR_IC_SELECTION_T;
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/**
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* @brief TMR Input Capture Prescaler
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*/
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typedef enum
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{
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TMR_IC_PSC_1,
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TMR_IC_PSC_2,
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TMR_IC_PSC_4,
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TMR_IC_PSC_8
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} TMR_IC_PSC_T;
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/**
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* @brief TMR Specifies the Off-State selection used in Run mode
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*/
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typedef enum
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{
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TMR_RMOS_STATE_DISABLE,
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TMR_RMOS_STATE_ENABLE
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} TMR_RMOS_STATE_T;
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/**
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* @brief TMR Closed state configuration in idle mode
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*/
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typedef enum
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{
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TMR_IMOS_STATE_DISABLE,
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TMR_IMOS_STATE_ENABLE
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} TMR_IMOS_STATE_T;
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/**
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* @brief TMR Protect mode configuration values
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*/
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typedef enum
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{
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TMR_LOCK_LEVEL_OFF,
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TMR_LOCK_LEVEL_1,
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TMR_LOCK_LEVEL_2,
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TMR_LOCK_LEVEL_3
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} TMR_LOCK_LEVEL_T;
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/**
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* @brief TMR BRK state
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*/
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typedef enum
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{
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TMR_BRK_STATE_DISABLE,
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TMR_BRK_STATE_ENABLE
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} TMR_BRK_STATE_T;
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/**
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* @brief TMR Specifies the Break Input pin polarity.
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*/
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typedef enum
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{
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TMR_BRK_POLARITY_LOW,
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TMR_BRK_POLARITY_HIGH
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} TMR_BRK_POLARITY_T;
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/**
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* @brief TMR Specifies the Break Input pin polarity.
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*/
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typedef enum
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{
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TMR_AUTOMATIC_OUTPUT_DISABLE,
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TMR_AUTOMATIC_OUTPUT_ENABLE
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} TMR_AUTOMATIC_OUTPUT_T;
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/**
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* @brief TMR_interrupt_sources
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*/
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typedef enum
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{
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TMR_INT_UPDATE = 0x0001,
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TMR_INT_CC1 = 0x0002,
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TMR_INT_CC2 = 0x0004,
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TMR_INT_CC3 = 0x0008,
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TMR_INT_CC4 = 0x0010,
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TMR_INT_COM = 0x0020,
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TMR_INT_TRG = 0x0040,
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TMR_INT_BRK = 0x0080
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} TMR_INT_T;
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/**
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* @brief TMR event sources
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*/
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typedef enum
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{
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TMR_EVENT_UPDATE = 0x001,
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TMR_EVENT_CC1 = 0x002,
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TMR_EVENT_CC2 = 0x004,
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TMR_EVENT_CC3 = 0x008,
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TMR_EVENT_CC4 = 0x010,
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TMR_EVENT_COM = 0x020,
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TMR_EVENT_TRG = 0x040,
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TMR_EVENT_BRK = 0x080
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} TMR_EVENT_T;
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/**
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* @brief TMR DMA Base Address
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*/
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typedef enum
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{
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TMR_DMA_BASE_CTRL1 = 0x0000,
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TMR_DMA_BASE_CTRL2 = 0x0001,
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TMR_DMA_BASE_SMCTRL = 0x0002,
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TMR_DMA_BASE_DIEN = 0x0003,
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TMR_DMA_BASE_STS = 0x0004,
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TMR_DMA_BASE_CEG = 0x0005,
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TMR_DMA_BASE_CCM1 = 0x0006,
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TMR_DMA_BASE_CCM2 = 0x0007,
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TMR_DMA_BASE_CCEN = 0x0008,
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TMR_DMA_BASE_CNT = 0x0009,
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TMR_DMA_BASE_PSC = 0x000A,
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TMR_DMA_BASE_AUTORLD = 0x000B,
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TMR_DMA_BASE_REPCNT = 0x000C,
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TMR_DMA_BASE_CC1 = 0x000D,
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TMR_DMA_BASE_CC2 = 0x000E,
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TMR_DMA_BASE_CC3 = 0x000F,
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TMR_DMA_BASE_CC4 = 0x0010,
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TMR_DMA_BASE_BDT = 0x0011,
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TMR_DMA_BASE_DCTRL = 0x0012
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} TMR_DMA_BASE_T;
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/**
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* @brief TMR DMA Burst Length
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*/
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typedef enum
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{
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TMR_DMA_BURSTLENGTH_1TRANSFER = 0x0000,
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TMR_DMA_BURSTLENGTH_2TRANSFERS = 0x0100,
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TMR_DMA_BURSTLENGTH_3TRANSFERS = 0x0200,
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TMR_DMA_BURSTLENGTH_4TRANSFERS = 0x0300,
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TMR_DMA_BURSTLENGTH_5TRANSFERS = 0x0400,
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TMR_DMA_BURSTLENGTH_6TRANSFERS = 0x0500,
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TMR_DMA_BURSTLENGTH_7TRANSFERS = 0x0600,
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TMR_DMA_BURSTLENGTH_8TRANSFERS = 0x0700,
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TMR_DMA_BURSTLENGTH_9TRANSFERS = 0x0800,
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TMR_DMA_BURSTLENGTH_10TRANSFERS = 0x0900,
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TMR_DMA_BURSTLENGTH_11TRANSFERS = 0x0A00,
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TMR_DMA_BURSTLENGTH_12TRANSFERS = 0x0B00,
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TMR_DMA_BURSTLENGTH_13TRANSFERS = 0x0C00,
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TMR_DMA_BURSTLENGTH_14TRANSFERS = 0x0D00,
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TMR_DMA_BURSTLENGTH_15TRANSFERS = 0x0E00,
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TMR_DMA_BURSTLENGTH_16TRANSFERS = 0x0F00,
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TMR_DMA_BURSTLENGTH_17TRANSFERS = 0x1000,
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TMR_DMA_BURSTLENGTH_18TRANSFERS = 0x1100,
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} TMR_DMA_BURSTLENGTH_T;
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/**
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* @brief TMR DMA Soueces
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*/
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typedef enum
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{
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TMR_DMA_SOURCE_UPDATE = 0x0100,
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TMR_DMA_SOURCE_CC1 = 0x0200,
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TMR_DMA_SOURCE_CC2 = 0x0400,
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TMR_DMA_SOURCE_CC3 = 0x0800,
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TMR_DMA_SOURCE_CC4 = 0x1000,
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TMR_DMA_SOURCE_COM = 0x2000,
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TMR_DMA_SOURCE_TRG = 0x4000
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} TMR_DMA_SOURCE_T;
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/**
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* @brief TMR Internal Trigger Selection
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*/
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typedef enum
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{
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TMR_TRIGGER_SOURCE_ITR0 = 0x00,
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TMR_TRIGGER_SOURCE_ITR1 = 0x01,
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TMR_TRIGGER_SOURCE_ITR2 = 0x02,
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TMR_TRIGGER_SOURCE_ITR3 = 0x03,
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TMR_TRIGGER_SOURCE_TI1F_ED = 0x04,
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TMR_TRIGGER_SOURCE_TI1FP1 = 0x05,
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TMR_TRIGGER_SOURCE_TI2FP2 = 0x06,
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TMR_TRIGGER_SOURCE_ETRF = 0x07
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} TMR_TRIGGER_SOURCE_T;
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/**
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* @brief TMR The external Trigger Prescaler.
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*/
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typedef enum
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{
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TMR_EXTTRG_PSC_OFF = 0x00,
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TMR_EXTTRG_PSC_DIV2 = 0x01,
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TMR_EXTTRG_PSC_DIV4 = 0x02,
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TMR_EXTTRG_PSC_DIV8 = 0x03
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} TMR_EXTTRG_PSC_T;
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/**
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* @brief TMR External Trigger Polarity
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*/
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typedef enum
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{
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TMR_EXTTGR_POL_NONINVERTED,
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TMR_EXTTRG_POL_INVERTED
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} TMR_EXTTRG_POL_T;
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/**
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* @brief TMR Prescaler Reload Mode
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*/
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typedef enum
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{
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TMR_PRESCALER_RELOAD_UPDATA,
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TMR_PRESCALER_RELOAD_IMMEDIATE
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} TMR_PRESCALER_RELOAD_T;
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/**
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* @brief TMR Encoder Mode
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*/
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typedef enum
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{
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TMR_ENCODER_MODE_TI1 = 0x01,
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TMR_ENCODER_MODE_TI2 = 0x02,
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TMR_ENCODER_MODE_TI12 = 0x03
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} TMR_ENCODER_MODE_T;
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/**
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* @brief TMR Forced Action
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*/
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typedef enum
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{
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TMR_FORCED_ACTION_INACTIVE = 0x04,
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TMR_FORCED_ACTION_ACTIVE = 0x05
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} TMR_FORCED_ACTION_T;
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/**
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* @brief TMR Output Compare Preload State
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*/
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typedef enum
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{
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TMR_OC_PRELOAD_DISABLE,
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TMR_OC_PRELOAD_ENABLE
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} TMR_OC_PRELOAD_T;
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/**
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* @brief TMR Output Compare Preload State
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*/
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typedef enum
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{
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TMR_OC_FAST_DISABLE,
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TMR_OC_FAST_ENABLE
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} TMR_OC_FAST_T;
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/**
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* @brief TMR Output Compare Preload State
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*/
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typedef enum
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{
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TMR_OC_CLEAR_DISABLE,
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TMR_OC_CLEAR_ENABLE
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} TMR_OC_CLEAR_T;
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/**
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* @brief TMR UpdateSource
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*/
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typedef enum
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{
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TMR_UPDATE_SOURCE_GLOBAL,
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TMR_UPDATE_SOURCE_REGULAR,
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} TMR_UPDATE_SOURCE_T;
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/**
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* @brief TMR Single Pulse Mode
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*/
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typedef enum
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{
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TMR_SPM_REPETITIVE,
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TMR_SPM_SINGLE,
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} TMR_SPM_T;
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/**
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* @brief TMR Trigger Output Source
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*/
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typedef enum
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{
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TMR_TRGO_SOURCE_RESET,
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TMR_TRGO_SOURCE_ENABLE,
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TMR_TRGO_SOURCE_UPDATE,
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TMR_TRGO_SOURCE_OC1,
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TMR_TRGO_SOURCE_OC1REF,
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TMR_TRGO_SOURCE_OC2REF,
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TMR_TRGO_SOURCE_OC3REF,
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TMR_TRGO_SOURCE_OC4REF
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} TMR_TRGO_SOURCE_T;
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/**
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* @brief TMR Slave Mode
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*/
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typedef enum
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{
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TMR_SLAVE_MODE_RESET = 0x04,
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TMR_SLAVE_MODE_GATED = 0x05,
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TMR_SLAVE_MODE_TRIGGER = 0x06,
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TMR_SLAVE_MODE_EXTERNALL = 0x07
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} TMR_SLAVE_MODE_T;
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/**
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* @brief TMR Flag
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*/
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typedef enum
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{
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TMR_FLAG_UPDATE = 0x0001,
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TMR_FLAG_CC1 = 0x0002,
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TMR_FLAG_CC2 = 0x0004,
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TMR_FLAG_CC3 = 0x0008,
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TMR_FLAG_CC4 = 0x0010,
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TMR_FLAG_COM = 0x0020,
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TMR_FLAG_TRG = 0x0040,
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TMR_FLAG_BRK = 0x0080,
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TMR_FLAG_CC1RC = 0x0200,
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TMR_FLAG_CC2RC = 0x0400,
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TMR_FLAG_CC3RC = 0x0800,
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TMR_FLAG_CC4RC = 0x1000
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} TMR_FLAG_T;
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/**@} end of group TMR_Enumerations*/
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/** @addtogroup TMR_Structure Data Structure
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@{
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*/
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/**
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* @brief TMR Config struct definition
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*/
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typedef struct
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{
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TMR_COUNTER_MODE_T countMode;
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TMR_CLOCK_DIV_T clockDivision;
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uint16_t period; //!< This must between 0x0000 and 0xFFFF
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uint16_t division; //!< This must between 0x0000 and 0xFFFF
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uint8_t repetitionCounter; //!< This must between 0x00 and 0xFF, only for TMR1 and TMR8.
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} TMR_BaseConfig_T; ;
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/**
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* @brief TMR Config struct definition
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*/
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typedef struct
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{
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TMR_OC_MODE_T mode;
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TMR_OC_STATE_T outputState;
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TMR_OC_NSTATE_T outputNState;
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TMR_OC_POLARITY_T polarity;
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TMR_OC_NPOLARITY_T nPolarity;
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TMR_OC_IDLE_STATE_T idleState;
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TMR_OC_NIDLE_STATE_T nIdleState;
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uint16_t pulse; //!< This must between 0x0000 and 0xFFFF
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} TMR_OCConfig_T;
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/**
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* @brief TMR BDT structure definition
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*/
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typedef struct
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{
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TMR_RMOS_STATE_T RMOS;
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TMR_IMOS_STATE_T IMOS;
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TMR_LOCK_LEVEL_T lockLevel;
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uint16_t deadTime;
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TMR_BRK_STATE_T BRKState;
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TMR_BRK_POLARITY_T BRKPolarity;
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TMR_AUTOMATIC_OUTPUT_T automaticOutput;
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} TMR_BDTConfig_T;
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/**
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* @brief TMR Input Capture Config struct definition
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*/
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typedef struct
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{
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TMR_CHANNEL_T channel;
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TMR_IC_POLARITY_T polarity;
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TMR_IC_SELECTION_T selection;
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TMR_IC_PSC_T prescaler;
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uint16_t filter; //!< This must between 0x00 and 0x0F
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} TMR_ICConfig_T;
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/**@} end of group TMR_Structure*/
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/** @addtogroup TMR_Fuctions Fuctions
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@{
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*/
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/** Reset and Configuration */
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void TMR_Reset(TMR_T* tmr);
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void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T *baseConfig);
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void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T *OC1Config);
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void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T *OC2Config);
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void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T *OC3Config);
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void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T *OC4Config);
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void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T *ICConfig);
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void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T *BDTConfig);
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void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig);
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void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig);
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void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig);
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void TMR_ConfigBDTStructInit( TMR_BDTConfig_T *BDTConfig);
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void TMR_Enable(TMR_T* tmr);
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void TMR_Disable(TMR_T* tmr);
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/* PWM Configuration */
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void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T *PWMConfig);
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void TMR_EnablePWMOutputs(TMR_T* tmr);
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void TMR_DisablePWMOutputs(TMR_T* tmr);
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/** DMA */
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void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength);
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void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource);
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void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource);
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/** Configuration */
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void TMR_ConfigInternalClock(TMR_T* tmr);
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void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource);
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void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
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TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter);
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void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
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TMR_EXTTRG_POL_T polarity, uint16_t filter);
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void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
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TMR_EXTTRG_POL_T polarity, uint16_t filter);
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void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
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TMR_EXTTRG_POL_T polarity, uint16_t filter);
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void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PRESCALER_RELOAD_T pscReloadMode);
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void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode);
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void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSouce);
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void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
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TMR_IC_POLARITY_T IC2Polarity);
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void TMR_ConfigForcedOC1(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
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void TMR_ConfigForcedOC2(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
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void TMR_ConfigForcedOC3(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
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void TMR_ConfigForcedOC4(TMR_T* tmr,TMR_FORCED_ACTION_T forcesAction);
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void TMR_EnableAUTOReload(TMR_T* tmr);
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void TMR_DisableAUTOReload(TMR_T* tmr);
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void TMR_EnableSelectCOM(TMR_T* tmr);
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void TMR_DisableSelectCOM(TMR_T* tmr);
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void TMR_EnableCCDMA(TMR_T* tmr);
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void TMR_DisableCCDMA(TMR_T* tmr);
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void TMR_EnableCCPreload(TMR_T* tmr);
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void TMR_DisableCCPreload(TMR_T* tmr);
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void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
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void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
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void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
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void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload);
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void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
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void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
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void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
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void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast);
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void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
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void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
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void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
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void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear);
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void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
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void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
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void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
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void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
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void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
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void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity);
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void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity);
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void TMR_EnableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
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void TMR_DisableCCxChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
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void TMR_EnableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
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void TMR_DisableCCxNChannel(TMR_T* tmr,TMR_CHANNEL_T channel);
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void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T OCMode);
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void TMR_EnableNoUpdate(TMR_T* tmr);
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void TMR_DisableNoUpdate(TMR_T* tmr);
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void TMR_ConfigUPdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource);
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void TMR_EnableHallSensor(TMR_T* tmr);
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void TMR_DisableHallSensor(TMR_T* tmr);
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void TMR_SelectSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode);
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void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource);
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void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode);
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void TMR_EnableMasterSlaveMode(TMR_T* tmr);
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void TMR_DisableMasterSlaveMode(TMR_T* tmr);
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void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter);
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void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload);
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void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1);
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void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2);
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void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3);
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void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4);
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void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
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void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
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void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
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void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler);
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void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision);
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uint16_t TMR_ReadCaputer1(TMR_T* tmr);
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uint16_t TMR_ReadCaputer2(TMR_T* tmr);
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uint16_t TMR_ReadCaputer3(TMR_T* tmr);
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uint16_t TMR_ReadCaputer4(TMR_T* tmr);
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uint16_t TMR_ReadCounter(TMR_T* tmr);
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uint16_t TMR_ReadPrescaler(TMR_T* tmr);
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/** Interrupts and Event */
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void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt);
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void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt);
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void TMR_GenerateEvent(TMR_T* tmr,uint16_t eventSources);
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/** flags */
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uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag);
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void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag);
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uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag);
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void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag);
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/**@} end of group TMR_Fuctions*/
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/**@} end of group TMR_Driver */
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/**@} end of group Peripherals_Library*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __APM32E10X_TMR_H */
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