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376 lines
8.3 KiB
C
376 lines
8.3 KiB
C
/*!
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* @file system_apm32f0xx.c
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*
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
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*
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* @version V1.0.1
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*
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* @date 2021-07-01
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*
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*/
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#include "apm32f0xx.h"
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#define SYSTEM_CLOCK_HSE HSE_VALUE
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//#define SYSTEM_CLOCK_24MHz (24000000)
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//#define SYSTEM_CLOCK_36MHz (36000000)
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//#define SYSTEM_CLOCK_48MHz (48000000)
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#ifdef SYSTEM_CLOCK_HSE
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uint32_t SystemCoreClock = SYSTEM_CLOCK_HSE;
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#elif defined SYSTEM_CLOCK_24MHz
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uint32_t SystemCoreClock = SYSTEM_CLOCK_24MHz;
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#elif defined SYSTEM_CLOCK_36MHz
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uint32_t SystemCoreClock = SYSTEM_CLOCK_36MHz;
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#elif defined SYSTEM_CLOCK_48MHz
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uint32_t SystemCoreClock = SYSTEM_CLOCK_48MHz;
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#else
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uint32_t SystemCoreClock = HSI_VALUE;
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#endif
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static void SystemClockConfig(void);
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#ifdef SYSTEM_CLOCK_HSE
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static void SystemClockHSE(void);
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#elif defined SYSTEM_CLOCK_24MHz
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static void SystemClock24M(void);
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#elif defined SYSTEM_CLOCK_36MHz
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static void SystemClock36M(void);
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#elif defined SYSTEM_CLOCK_48MHz
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static void SystemClock48M(void);
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#endif
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/*!
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* @brief Setup the microcontroller system
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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void SystemInit (void)
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{
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/** Set HSIEN bit */
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RCM->CTRL1_B.HSIEN = BIT_SET;
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/** Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and COC bits */
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RCM->CFG1 &= (uint32_t)0x08FFB80CU;
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/** Reset HSEEN, CSSEN and PLLEN bits */
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RCM->CTRL1 &= (uint32_t)0xFEF6FFFFU;
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/** Reset HSEBCFG bit */
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RCM->CTRL1_B.HSEBCFG = BIT_RESET;
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/** Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG bits */
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RCM->CFG1 &= (uint32_t)0xFFC0FFFFU;
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/** Reset PREDIV[3:0] bits */
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RCM->CFG1 &= (uint32_t)0xFFFFFFF0U;
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/** Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
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RCM->CFG3 &= (uint32_t)0xFFFFFEAC;
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/* Reset HSI14 bit */
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RCM->CTRL2_B.HSI14EN = BIT_RESET;
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/** Disable all interrupts */
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RCM->INT = 0x00000000U;
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SystemClockConfig();
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}
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/*!
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* @brief Update SystemCoreClock variable according to Clock Register Values
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* The SystemCoreClock variable contains the core clock (HCLK)
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t sysClock, pllMull, pllSource, Prescaler;
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uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/* Get SYSCLK source -------------------------------------------------------*/
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sysClock = RCM->CFG1_B.SCLKSWSTS;
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switch (sysClock)
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{
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case 0:
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SystemCoreClock = HSI_VALUE;
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break;
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/** sys clock is HSE */
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case 1:
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SystemCoreClock = HSE_VALUE;
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break;
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/** sys clock is PLL */
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case 2:
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pllMull = RCM->CFG1_B.PLLMULCFG + 2;
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pllSource = RCM->CFG1_B.PLLSRCSEL;
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/** PLL entry clock source is HSE */
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if (pllSource == BIT_SET)
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{
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SystemCoreClock = HSE_VALUE * pllMull;
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/** HSE clock divided by 2 */
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if (pllSource == RCM->CFG1_B.PLLHSEPSC)
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{
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SystemCoreClock >>= 1;
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}
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}
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/** PLL entry clock source is HSI/2 */
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else
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{
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SystemCoreClock = (HSI_VALUE >> 1) * pllMull;
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}
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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Prescaler = AHBPrescTable[(RCM->CFG1_B.AHBPSC)];
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SystemCoreClock >>= Prescaler;
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}
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/*!
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClockConfig(void)
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{
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#ifdef SYSTEM_CLOCK_HSE
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SystemClockHSE();
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#elif defined SYSTEM_CLOCK_24MHz
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SystemClock24M();
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#elif defined SYSTEM_CLOCK_36MHz
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SystemClock36M();
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#elif defined SYSTEM_CLOCK_48MHz
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SystemClock48M();
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#endif
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}
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#if defined SYSTEM_CLOCK_HSE
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/*!
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* @brief Selects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClockHSE(void)
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{
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uint32_t i;
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RCM->CTRL1_B.HSEEN= BIT_SET;
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for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if (RCM->CTRL1_B.HSERDYFLG)
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{
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break;
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}
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}
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if (RCM->CTRL1_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 0 wait state */
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FMC->CTRL1_B.WS = 0;
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/* HCLK = SYSCLK */
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RCM->CFG1_B.AHBPSC= 0X00;
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/* PCLK = HCLK */
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RCM->CFG1_B.APB1PSC = 0X00;
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/* Select HSE as system clock source */
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RCM->CFG1_B.SCLKSEL = 1;
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/** Wait till HSE is used as system clock source */
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while (RCM->CFG1_B.SCLKSWSTS!= 0x01);
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}
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}
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#elif defined SYSTEM_CLOCK_24MHz
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/*!
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* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClock24M(void)
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{
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uint32_t i;
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RCM->CTRL1_B.HSEEN= BIT_SET;
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for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if (RCM->CTRL1_B.HSERDYFLG)
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{
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break;
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}
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}
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if (RCM->CTRL1_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 1 wait state */
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FMC->CTRL1_B.WS = 1;
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/* HCLK = SYSCLK */
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RCM->CFG1_B.AHBPSC= 0X00;
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/* PCLK = HCLK */
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RCM->CFG1_B.APB1PSC = 0X00;
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/** PLL: (HSE / 2) * 6 */
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RCM->CFG1_B.PLLSRCSEL = 1;
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RCM->CFG1_B.PLLHSEPSC = 1;
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RCM->CFG1_B.PLLMULCFG = 4;
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/** Enable PLL */
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RCM->CTRL1_B.PLLEN = 1;
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/** Wait PLL Ready */
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while (RCM->CTRL1_B.PLLRDYFLG == BIT_RESET);
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/* Select PLL as system clock source */
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RCM->CFG1_B.SCLKSEL = 2;
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/* Wait till PLL is used as system clock source */
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while (RCM->CFG1_B.SCLKSWSTS!= 0x02);
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}
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}
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#elif defined SYSTEM_CLOCK_36MHz
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/*!
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* @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClock36M(void)
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{
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uint32_t i;
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RCM->CTRL1_B.HSEEN= BIT_SET;
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for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if (RCM->CTRL1_B.HSERDYFLG)
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{
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break;
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}
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}
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if (RCM->CTRL1_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 1 wait state */
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FMC->CTRL1_B.WS = 1;
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/* HCLK = SYSCLK */
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RCM->CFG1_B.AHBPSC= 0X00;
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/* PCLK = HCLK */
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RCM->CFG1_B.APB1PSC = 0X00;
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/** PLL: (HSE / 2) * 9 */
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RCM->CFG1_B.PLLSRCSEL = 1;
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RCM->CFG1_B.PLLHSEPSC = 1;
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RCM->CFG1_B.PLLMULCFG = 7;
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/** Enable PLL */
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RCM->CTRL1_B.PLLEN = 1;
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/** Wait PLL Ready */
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while (RCM->CTRL1_B.PLLRDYFLG == BIT_RESET);
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/* Select PLL as system clock source */
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RCM->CFG1_B.SCLKSEL = 2;
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/* Wait till PLL is used as system clock source */
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while (RCM->CFG1_B.SCLKSWSTS != 0x02);
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}
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}
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#elif defined SYSTEM_CLOCK_48MHz
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/*!
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* @brief Sets System clock frequency to 46MHz and configure HCLK, PCLK2 and PCLK1 prescalers
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*
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* @param None
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*
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* @retval None
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*
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* @note
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*/
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static void SystemClock48M(void)
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{
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uint32_t i;
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RCM->CTRL1_B.HSEEN= BIT_SET;
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for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
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{
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if (RCM->CTRL1_B.HSERDYFLG)
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{
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break;
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}
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}
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if (RCM->CTRL1_B.HSERDYFLG)
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{
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/* Enable Prefetch Buffer */
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FMC->CTRL1_B.PBEN = BIT_SET;
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/* Flash 1 wait state */
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FMC->CTRL1_B.WS = 1;
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/* HCLK = SYSCLK */
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RCM->CFG1_B.AHBPSC= 0X00;
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/* PCLK = HCLK */
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RCM->CFG1_B.APB1PSC = 0X00;
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/** PLL: HSE * 6 */
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RCM->CFG1_B.PLLSRCSEL = 1;
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RCM->CFG1_B.PLLMULCFG = 4;
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/** Enable PLL */
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RCM->CTRL1_B.PLLEN = 1;
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/** Wait PLL Ready */
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while (RCM->CTRL1_B.PLLRDYFLG == BIT_RESET);
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/* Select PLL as system clock source */
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RCM->CFG1_B.SCLKSEL = 2;
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/* Wait till PLL is used as system clock source */
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while (RCM->CFG1_B.SCLKSWSTS!= 0x02);
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}
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}
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#endif
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